TimeQuest Timing Analyzer report for atari800core
Sat Mar 28 00:12:59 2015
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Parallel Compilation
  4. SDC File List
  5. Clocks
  6. Slow 1200mV 85C Model Fmax Summary
  7. Timing Closure Recommendations
  8. Slow 1200mV 85C Model Setup Summary
  9. Slow 1200mV 85C Model Hold Summary
 10. Slow 1200mV 85C Model Recovery Summary
 11. Slow 1200mV 85C Model Removal Summary
 12. Slow 1200mV 85C Model Minimum Pulse Width Summary
 13. Slow 1200mV 85C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 14. Slow 1200mV 85C Model Setup: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 15. Slow 1200mV 85C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 16. Slow 1200mV 85C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'
 17. Slow 1200mV 85C Model Hold: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 18. Slow 1200mV 85C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'
 19. Slow 1200mV 85C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 20. Slow 1200mV 85C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 21. Slow 1200mV 85C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 22. Slow 1200mV 85C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 23. Slow 1200mV 85C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'
 24. Slow 1200mV 85C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 25. Slow 1200mV 85C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 26. Slow 1200mV 85C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'
 27. Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 28. Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'
 29. Slow 1200mV 85C Model Minimum Pulse Width: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 30. Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 31. Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]'
 32. Slow 1200mV 85C Model Minimum Pulse Width: 'FPGA_CLK'
 33. Setup Times
 34. Hold Times
 35. Clock to Output Times
 36. Minimum Clock to Output Times
 37. Output Enable Times
 38. Minimum Output Enable Times
 39. Output Disable Times
 40. Minimum Output Disable Times
 41. Slow 1200mV 85C Model Metastability Report
 42. Slow 1200mV 0C Model Fmax Summary
 43. Slow 1200mV 0C Model Setup Summary
 44. Slow 1200mV 0C Model Hold Summary
 45. Slow 1200mV 0C Model Recovery Summary
 46. Slow 1200mV 0C Model Removal Summary
 47. Slow 1200mV 0C Model Minimum Pulse Width Summary
 48. Slow 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 49. Slow 1200mV 0C Model Setup: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 50. Slow 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 51. Slow 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'
 52. Slow 1200mV 0C Model Hold: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 53. Slow 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'
 54. Slow 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 55. Slow 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 56. Slow 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 57. Slow 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 58. Slow 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'
 59. Slow 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 60. Slow 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 61. Slow 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'
 62. Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 63. Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'
 64. Slow 1200mV 0C Model Minimum Pulse Width: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 65. Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 66. Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]'
 67. Slow 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'
 68. Setup Times
 69. Hold Times
 70. Clock to Output Times
 71. Minimum Clock to Output Times
 72. Output Enable Times
 73. Minimum Output Enable Times
 74. Output Disable Times
 75. Minimum Output Disable Times
 76. Slow 1200mV 0C Model Metastability Report
 77. Fast 1200mV 0C Model Setup Summary
 78. Fast 1200mV 0C Model Hold Summary
 79. Fast 1200mV 0C Model Recovery Summary
 80. Fast 1200mV 0C Model Removal Summary
 81. Fast 1200mV 0C Model Minimum Pulse Width Summary
 82. Fast 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 83. Fast 1200mV 0C Model Setup: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 84. Fast 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 85. Fast 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'
 86. Fast 1200mV 0C Model Hold: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 87. Fast 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'
 88. Fast 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 89. Fast 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 90. Fast 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 91. Fast 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 92. Fast 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'
 93. Fast 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 94. Fast 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 95. Fast 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'
 96. Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 97. Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'
 98. Fast 1200mV 0C Model Minimum Pulse Width: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 99. Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
100. Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]'
101. Fast 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'
102. Setup Times
103. Hold Times
104. Clock to Output Times
105. Minimum Clock to Output Times
106. Output Enable Times
107. Minimum Output Enable Times
108. Output Disable Times
109. Minimum Output Disable Times
110. Fast 1200mV 0C Model Metastability Report
111. Multicorner Timing Analysis Summary
112. Setup Times
113. Hold Times
114. Clock to Output Times
115. Minimum Clock to Output Times
116. Board Trace Model Assignments
117. Input Transition Times
118. Slow Corner Signal Integrity Metrics
119. Fast Corner Signal Integrity Metrics
120. Setup Transfers
121. Hold Transfers
122. Recovery Transfers
123. Removal Transfers
124. Report TCCS
125. Report RSKM
126. Unconstrained Paths
127. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
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to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                                      ;
+--------------------+-------------------------------------------------------------------+
; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ;
; Revision Name      ; atari800core                                                      ;
; Device Family      ; Cyclone III                                                       ;
; Device Name        ; EP3C16E144C8                                                      ;
; Timing Models      ; Final                                                             ;
; Delay Model        ; Combined                                                          ;
; Rise/Fall Delays   ; Enabled                                                           ;
+--------------------+-------------------------------------------------------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 4           ;
; Maximum allowed            ; 2           ;
;                            ;             ;
; Average used               ; 1.21        ;
; Maximum used               ; 2           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processor 2            ;  21.4%      ;
;     Processors 3-4         ;   0.0%      ;
+----------------------------+-------------+


+------------------------------------------------------+
; SDC File List                                        ;
+------------------+--------+--------------------------+
; SDC File Path    ; Status ; Read at                  ;
+------------------+--------+--------------------------+
; atari800core.sdc ; OK     ; Sat Mar 28 00:12:46 2015 ;
+------------------+--------+--------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                                                                                                                                                                                                                                                                                                                             ;
+-------------------------------------------------------------------------------+-----------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+------------------------------------------------------------------------------+---------------------------------------------------------------------------------+-----------------------------------------------------------------------------------+
; Clock Name                                                                    ; Type      ; Period  ; Frequency ; Rise  ; Fall    ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master                                                                       ; Source                                                                          ; Targets                                                                           ;
+-------------------------------------------------------------------------------+-----------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+------------------------------------------------------------------------------+---------------------------------------------------------------------------------+-----------------------------------------------------------------------------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Generated ; 11.747  ; 85.13 MHz ; 0.000 ; 5.873   ; 50.00      ; 1         ; 3           ;       ;        ;           ;            ; false    ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] } ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Generated ; 35.242  ; 28.38 MHz ; 0.000 ; 17.621  ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] } ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ; Generated ; 11.747  ; 85.13 MHz ; 7.341 ; 13.214  ; 50.00      ; 1         ; 3           ; 225.0 ;        ;           ;            ; false    ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] } ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Generated ; 17.621  ; 56.75 MHz ; 0.000 ; 8.810   ; 50.00      ; 1         ; 2           ;       ;        ;           ;            ; false    ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] } ;
; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]  ; Generated ; 35.242  ; 28.38 MHz ; 0.000 ; 17.621  ; 50.00      ; 40        ; 227         ;       ;        ;           ;            ; false    ; FPGA_CLK                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]  ; { \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] }  ;
; FPGA_CLK                                                                      ; Base      ; 200.000 ; 5.0 MHz   ; 0.000 ; 100.000 ;            ;           ;             ;       ;        ;           ;            ;          ;                                                                              ;                                                                                 ; { FPGA_CLK }                                                                      ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; Generated ; 20.833  ; 48.0 MHz  ; 0.000 ; 10.416  ; 50.00      ; 5         ; 48          ;       ;        ;           ;            ; false    ; FPGA_CLK                                                                     ; usb_pll|altpll_component|auto_generated|pll1|inclk[0]                           ; { usb_pll|altpll_component|auto_generated|pll1|clk[0] }                           ;
+-------------------------------------------------------------------------------+-----------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+------------------------------------------------------------------------------+---------------------------------------------------------------------------------+-----------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Fmax Summary                                                                                  ;
+------------+-----------------+-------------------------------------------------------------------------------+------+
; Fmax       ; Restricted Fmax ; Clock Name                                                                    ; Note ;
+------------+-----------------+-------------------------------------------------------------------------------+------+
; 35.1 MHz   ; 35.1 MHz        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;      ;
; 106.37 MHz ; 106.37 MHz      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ;      ;
; 127.29 MHz ; 127.29 MHz      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;      ;
; 133.89 MHz ; 133.89 MHz      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;      ;
+------------+-----------------+-------------------------------------------------------------------------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


----------------------------------
; Timing Closure Recommendations ;
----------------------------------
HTML report is unavailable in plain text report export.


+--------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup Summary                                                                    ;
+-------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                         ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; -3.853 ; -139.896      ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; -0.486 ; -10.965       ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.731  ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 9.765  ; 0.000         ;
+-------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold Summary                                                                     ;
+-------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                         ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------+--------+---------------+
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; -1.725 ; -63.784       ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.370  ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.453  ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.454  ; 0.000         ;
+-------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery Summary                                                                 ;
+-------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                         ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 6.223  ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 7.730  ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 11.432 ; 0.000         ;
+-------------------------------------------------------------------------------+--------+---------------+


+-------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal Summary                                                                 ;
+-------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                         ; Slack ; End Point TNS ;
+-------------------------------------------------------------------------------+-------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 2.605 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 4.075 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 4.546 ; 0.000         ;
+-------------------------------------------------------------------------------+-------+---------------+


+--------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width Summary                                                      ;
+-------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                         ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.570  ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 8.513  ; 0.000         ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; 10.104 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.191 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]  ; 17.584 ; 0.000         ;
; FPGA_CLK                                                                      ; 99.858 ; 0.000         ;
+-------------------------------------------------------------------------------+--------+---------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                              ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                          ; To Node                                                                                                                                                                                            ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; -3.853 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[8]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[8]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.559     ; 1.266      ;
; -3.713 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[10]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[10]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.559     ; 1.126      ;
; -3.709 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[12]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[12]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.559     ; 1.122      ;
; -3.706 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[14]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[14]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.559     ; 1.119      ;
; -3.676 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[9]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.559     ; 1.089      ;
; -3.674 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[15]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[15]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.559     ; 1.087      ;
; -3.266 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.145     ; 1.093      ;
; -3.266 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.145     ; 1.093      ;
; -3.248 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[11]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[11]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.084     ; 1.136      ;
; -3.245 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[13]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.084     ; 1.133      ;
; -3.239 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[10]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[10]    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.084     ; 1.127      ;
; -3.204 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[7]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[7]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.084     ; 1.092      ;
; -3.188 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[0]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[0]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.092     ; 1.068      ;
; -3.168 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[2]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[2]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.092     ; 1.048      ;
; -3.159 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[1]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[1]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.092     ; 1.039      ;
; -3.156 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[3]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[3]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.092     ; 1.036      ;
; -3.081 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.145     ; 0.908      ;
; -3.081 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.145     ; 0.908      ;
; -3.080 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.145     ; 0.907      ;
; -3.080 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.145     ; 0.907      ;
; -3.080 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.145     ; 0.907      ;
; -3.074 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|bitStuffError                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[1]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.136     ; 0.910      ;
; -3.073 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[1] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.135     ; 0.910      ;
; -3.073 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXTimeOut                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[3]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.136     ; 0.909      ;
; -3.071 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CRCError                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[0]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.136     ; 0.907      ;
; -3.071 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[0] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.135     ; 0.908      ;
; -3.067 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|stallRxed                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[5]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.130     ; 0.909      ;
; -3.066 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|NAKRxed                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[4]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.130     ; 0.908      ;
; -3.066 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXOverflow                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[2]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.130     ; 0.908      ;
; -3.046 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[3]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[3]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.085     ; 0.933      ;
; -3.046 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInExtend[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInSTB[2]           ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.134     ; 0.884      ;
; -3.046 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|dataSequence                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[7]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.136     ; 0.882      ;
; -3.045 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.134     ; 0.883      ;
; -3.043 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.134     ; 0.881      ;
; -3.042 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.130     ; 0.884      ;
; -3.040 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|ACKRxed                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[6]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.130     ; 0.882      ;
; -3.020 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[8]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[8]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.084     ; 0.908      ;
; -3.020 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[9]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[9]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.085     ; 0.907      ;
; -3.020 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[5]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[5]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.084     ; 0.908      ;
; -3.020 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[2]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[2]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.084     ; 0.908      ;
; -3.019 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[6]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[6]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.084     ; 0.907      ;
; -3.019 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[0]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[0]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.084     ; 0.907      ;
; -3.019 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[1]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[1]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.084     ; 0.907      ;
; -3.018 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[4]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[4]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.084     ; 0.906      ;
; 2.500  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[7]                                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.163     ; 9.086      ;
; 2.500  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[9]                                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.163     ; 9.086      ;
; 2.500  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[10]                                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.163     ; 9.086      ;
; 2.500  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[8]                                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.163     ; 9.086      ;
; 2.715  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[5]                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 8.860      ;
; 2.765  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[0]                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 8.806      ;
; 2.765  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[1]                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 8.806      ;
; 2.765  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[2]                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 8.806      ;
; 2.765  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[3]                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 8.806      ;
; 2.765  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[4]                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 8.806      ;
; 2.765  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[5]                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 8.806      ;
; 2.765  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[6]                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 8.806      ;
; 2.765  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[7]                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 8.806      ;
; 2.767  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[3]                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 8.807      ;
; 2.767  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[6]                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 8.807      ;
; 2.785  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[4]                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 8.790      ;
; 2.877  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer2|count_reg[0]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.167     ; 8.705      ;
; 2.877  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer2|count_reg[1]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.167     ; 8.705      ;
; 2.877  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer2|count_reg[2]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.167     ; 8.705      ;
; 2.877  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer2|count_reg[3]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.167     ; 8.705      ;
; 2.877  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer2|count_reg[4]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.167     ; 8.705      ;
; 2.877  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer2|count_reg[5]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.167     ; 8.705      ;
; 2.877  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer2|count_reg[6]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.167     ; 8.705      ;
; 2.877  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer2|count_reg[7]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.167     ; 8.705      ;
; 2.932  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.163     ; 8.654      ;
; 2.932  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[11]                                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.163     ; 8.654      ;
; 2.932  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.163     ; 8.654      ;
; 2.932  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.163     ; 8.654      ;
; 2.932  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[13]                                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.163     ; 8.654      ;
; 2.932  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[4]                                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.163     ; 8.654      ;
; 2.932  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.163     ; 8.654      ;
; 2.932  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]                                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.163     ; 8.654      ;
; 2.932  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]                                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.163     ; 8.654      ;
; 2.932  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[12]                                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.163     ; 8.654      ;
; 2.932  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.163     ; 8.654      ;
; 2.932  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.163     ; 8.654      ;
; 2.945  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[5]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.185     ; 8.619      ;
; 2.945  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[4]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.185     ; 8.619      ;
; 2.945  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[2]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.185     ; 8.619      ;
; 2.945  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[3]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.185     ; 8.619      ;
; 2.945  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[1]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.185     ; 8.619      ;
; 2.945  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[0]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.185     ; 8.619      ;
; 2.949  ; ram_do_reg[7]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.183     ; 8.617      ;
; 3.010  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[3]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.185     ; 8.554      ;
; 3.010  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[6]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.185     ; 8.554      ;
; 3.010  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[7]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.185     ; 8.554      ;
; 3.010  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[4]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.185     ; 8.554      ;
; 3.010  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[0]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.185     ; 8.554      ;
; 3.010  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[1]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.185     ; 8.554      ;
; 3.010  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[5]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.185     ; 8.554      ;
; 3.010  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[2]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.185     ; 8.554      ;
; 3.019  ; ram_do_reg[7]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.179     ; 8.551      ;
; 3.022  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[7]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.169     ; 8.558      ;
; 3.022  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[6]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.169     ; 8.558      ;
; 3.022  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[1]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.169     ; 8.558      ;
; 3.022  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[0]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.169     ; 8.558      ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                               ; To Node                                                                                                                                                                                                          ; Launch Clock                                                                  ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -0.486 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.249      ; 1.635      ;
; -0.408 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.249      ; 1.557      ;
; -0.393 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.249      ; 1.542      ;
; -0.387 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate_reg1                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.239      ; 1.526      ;
; -0.351 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.241      ; 1.492      ;
; -0.347 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.253      ; 1.500      ;
; -0.317 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.249      ; 1.466      ;
; -0.306 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.241      ; 1.447      ;
; -0.304 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.266      ; 1.470      ;
; -0.302 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.240      ; 1.442      ;
; -0.301 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.253      ; 1.454      ;
; -0.300 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.249      ; 1.449      ;
; -0.299 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.242      ; 1.441      ;
; -0.299 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.254      ; 1.453      ;
; -0.298 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.249      ; 1.447      ;
; -0.298 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[0]                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.239      ; 1.437      ;
; -0.297 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.254      ; 1.451      ;
; -0.296 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg_reg1                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.240      ; 1.436      ;
; -0.293 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.241      ; 1.434      ;
; -0.293 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.254      ; 1.447      ;
; -0.292 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn_reg1                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.253      ; 1.445      ;
; -0.290 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.249      ; 1.439      ;
; -0.287 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.241      ; 1.428      ;
; -0.278 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.253      ; 1.431      ;
; -0.278 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.253      ; 1.431      ;
; -0.277 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.253      ; 1.430      ;
; -0.276 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.252      ; 1.428      ;
; -0.276 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.252      ; 1.428      ;
; -0.273 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.252      ; 1.425      ;
; -0.271 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.253      ; 1.424      ;
; -0.270 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.252      ; 1.422      ;
; -0.227 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.266      ; 1.393      ;
; -0.200 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.266      ; 1.366      ;
; -0.169 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.249      ; 1.318      ;
; -0.153 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.266      ; 1.319      ;
; -0.131 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.266      ; 1.297      ;
; -0.113 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.255      ; 1.268      ;
; -0.111 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.266      ; 1.277      ;
; -0.110 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.266      ; 1.276      ;
; -0.108 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.266      ; 1.274      ;
; 11.432 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.572     ; 8.830      ;
; 11.443 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.572     ; 8.819      ;
; 11.606 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.572     ; 8.656      ;
; 11.917 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[5]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 8.839      ;
; 11.928 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[5]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 8.828      ;
; 11.952 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 8.804      ;
; 11.963 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 8.793      ;
; 12.091 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[5]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 8.665      ;
; 12.122 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[4]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 8.634      ;
; 12.126 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 8.630      ;
; 12.133 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[4]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 8.623      ;
; 12.191 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 8.565      ;
; 12.202 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 8.554      ;
; 12.237 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[6]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 8.519      ;
; 12.248 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[6]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 8.508      ;
; 12.296 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[4]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 8.460      ;
; 12.299 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 8.457      ;
; 12.310 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 8.446      ;
; 12.365 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 8.391      ;
; 12.411 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[6]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 8.345      ;
; 12.473 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 8.283      ;
; 12.661 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.000            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.082     ; 8.091      ;
; 12.672 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.000            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.082     ; 8.080      ;
; 12.835 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.000            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.082     ; 7.917      ;
; 13.295 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.000 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 7.461      ;
; 13.348 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[7]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 7.408      ;
; 13.359 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[7]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 7.397      ;
; 13.430 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 7.326      ;
; 13.432 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 7.324      ;
; 13.445 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.000 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 7.311      ;
; 13.482 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.000 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 7.274      ;
; 13.522 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[7]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 7.234      ;
; 13.580 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 7.176      ;
; 13.582 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 7.174      ;
; 13.607 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.000 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 7.149      ;
; 13.617 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 7.139      ;
; 13.619 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 7.137      ;
; 13.637 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.000 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 7.119      ;
; 13.638 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFNearTime[15]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.089     ; 7.107      ;
; 13.649 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFNearTime[15]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.089     ; 7.096      ;
; 13.742 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 7.014      ;
; 13.744 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 7.012      ;
; 13.764 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.000 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 6.992      ;
; 13.772 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 6.984      ;
; 13.774 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 6.982      ;
; 13.791 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 6.965      ;
; 13.791 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.010 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 6.965      ;
; 13.812 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFNearTime[15]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.089     ; 6.933      ;
; 13.899 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 6.857      ;
; 13.901 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 6.855      ;
; 13.941 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 6.815      ;
; 13.941 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.010 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 6.815      ;
; 13.966 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 6.790      ;
; 13.976 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[7]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.000 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 6.780      ;
; 13.977 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 6.779      ;
; 13.978 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 6.778      ;
; 13.978 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.010 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 6.778      ;
; 14.084 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[0] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[4]              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.082     ; 6.668      ;
; 14.103 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 6.653      ;
; 14.103 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.010 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 6.653      ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                            ;
+-------+-------------------------+----------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node               ; To Node                                      ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------+----------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 0.731 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.164     ; 4.849      ;
; 0.914 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.164     ; 4.666      ;
; 1.011 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.165     ; 4.568      ;
; 1.044 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[0]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.179     ; 4.521      ;
; 1.044 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.179     ; 4.521      ;
; 1.044 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.179     ; 4.521      ;
; 1.044 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.179     ; 4.521      ;
; 1.067 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.166     ; 4.511      ;
; 1.067 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.166     ; 4.511      ;
; 1.163 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.179     ; 4.402      ;
; 1.178 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_ras_n    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.177     ; 4.389      ;
; 1.194 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.165     ; 4.385      ;
; 1.227 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[0]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.179     ; 4.338      ;
; 1.227 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.179     ; 4.338      ;
; 1.227 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.179     ; 4.338      ;
; 1.227 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.179     ; 4.338      ;
; 1.230 ; SDRAM_ADDR[16]          ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.152     ; 4.362      ;
; 1.250 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.166     ; 4.328      ;
; 1.250 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.166     ; 4.328      ;
; 1.346 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.179     ; 4.219      ;
; 1.361 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_ras_n    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.177     ; 4.206      ;
; 1.380 ; SDRAM_ADDR[18]          ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.154     ; 4.210      ;
; 1.442 ; SDRAM_ADDR[17]          ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.153     ; 4.149      ;
; 1.502 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.165     ; 4.077      ;
; 1.626 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[8]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.170     ; 4.078      ;
; 1.626 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[9]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.170     ; 4.078      ;
; 1.627 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[0]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.170     ; 4.077      ;
; 1.671 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[1]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.170     ; 4.033      ;
; 1.688 ; SDRAM_ADDR[22]          ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.179     ; 3.877      ;
; 1.705 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.165     ; 3.874      ;
; 1.722 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_ba[0]    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.177     ; 3.845      ;
; 1.774 ; SDRAM_ADDR[12]          ; sdram_ctrl:sdram_controller|r_sdram_addr[0]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.177     ; 3.793      ;
; 1.779 ; SDRAM_ADDR[7]           ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.143     ; 3.822      ;
; 1.855 ; SDRAM_ADDR[20]          ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.153     ; 3.736      ;
; 1.890 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[15]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.167     ; 3.817      ;
; 1.892 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[13]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.167     ; 3.815      ;
; 1.893 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[10]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.167     ; 3.814      ;
; 1.905 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_ba[1]    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.179     ; 3.660      ;
; 1.905 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_ba[0]    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.177     ; 3.662      ;
; 1.929 ; SDRAM_ADDR[5]           ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.141     ; 3.674      ;
; 1.966 ; SDRAM_ADDR[3]           ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.178     ; 3.600      ;
; 1.975 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.165     ; 3.604      ;
; 2.075 ; SDRAM_READ_ENABLE       ; ram_do_reg[7]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.170     ; 3.629      ;
; 2.075 ; SDRAM_READ_ENABLE       ; ram_do_reg[15]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.170     ; 3.629      ;
; 2.079 ; SDRAM_ADDR[19]          ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.154     ; 3.511      ;
; 2.080 ; SDRAM_READ_ENABLE       ; ram_do_reg[2]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.173     ; 3.621      ;
; 2.082 ; SDRAM_READ_ENABLE       ; ram_do_reg[3]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.172     ; 3.620      ;
; 2.082 ; SDRAM_READ_ENABLE       ; ram_do_reg[11]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.172     ; 3.620      ;
; 2.088 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_ba[1]    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.179     ; 3.477      ;
; 2.104 ; SDRAM_READ_ENABLE       ; ram_do_reg[6]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.170     ; 3.600      ;
; 2.158 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.165     ; 3.421      ;
; 2.229 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[5]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.167     ; 3.478      ;
; 2.231 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[2]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.167     ; 3.476      ;
; 2.276 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[7]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.167     ; 3.431      ;
; 2.296 ; SDRAM_ADDR[6]           ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.142     ; 3.306      ;
; 2.313 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[6]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.167     ; 3.394      ;
; 2.317 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[4]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.167     ; 3.390      ;
; 2.317 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[14]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.167     ; 3.390      ;
; 2.352 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[13]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.144     ; 3.378      ;
; 2.353 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[15]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.144     ; 3.377      ;
; 2.355 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[10]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.144     ; 3.375      ;
; 2.381 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[1]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.147     ; 3.346      ;
; 2.436 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[9]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.147     ; 3.291      ;
; 2.436 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[8]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.147     ; 3.291      ;
; 2.443 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[12]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.167     ; 3.264      ;
; 2.444 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[3]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.167     ; 3.263      ;
; 2.444 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[11]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.167     ; 3.263      ;
; 2.475 ; SDRAM_ADDR[21]          ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.165     ; 3.104      ;
; 2.486 ; SDRAM_ADDR[8]           ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.165     ; 3.093      ;
; 2.499 ; SDRAM_ADDR[15]          ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.178     ; 3.067      ;
; 2.509 ; SDRAM_ADDR[1]           ; sdram_ctrl:sdram_controller|r_sdram_addr[0]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.178     ; 3.057      ;
; 2.555 ; SDRAM_ADDR[14]          ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.178     ; 3.011      ;
; 2.586 ; SDRAM_ADDR[4]           ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.177     ; 2.981      ;
; 2.617 ; SDRAM_ADDR[13]          ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.178     ; 2.949      ;
; 2.619 ; SDRAM_ADDR[9]           ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.164     ; 2.961      ;
; 2.663 ; SDRAM_ADDR[2]           ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.177     ; 2.904      ;
; 2.667 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[7]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.144     ; 3.063      ;
; 2.672 ; SDRAM_READ_ENABLE       ; ram_do_reg[29]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.182     ; 3.020      ;
; 2.672 ; SDRAM_READ_ENABLE       ; ram_do_reg[28]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.182     ; 3.020      ;
; 2.672 ; SDRAM_READ_ENABLE       ; ram_do_reg[21]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.182     ; 3.020      ;
; 2.672 ; SDRAM_READ_ENABLE       ; ram_do_reg[20]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.182     ; 3.020      ;
; 2.672 ; SDRAM_READ_ENABLE       ; ram_do_reg[18]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.182     ; 3.020      ;
; 2.672 ; SDRAM_READ_ENABLE       ; ram_do_reg[25]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.182     ; 3.020      ;
; 2.672 ; SDRAM_READ_ENABLE       ; ram_do_reg[19]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.182     ; 3.020      ;
; 2.672 ; SDRAM_READ_ENABLE       ; ram_do_reg[26]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.182     ; 3.020      ;
; 2.672 ; SDRAM_READ_ENABLE       ; ram_do_reg[16]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.182     ; 3.020      ;
; 2.672 ; SDRAM_READ_ENABLE       ; ram_do_reg[23]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.182     ; 3.020      ;
; 2.689 ; SDRAM_ADDR[10]          ; sdram_ctrl:sdram_controller|r_sdram_ba[0]    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.176     ; 2.879      ;
; 2.696 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[5]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.144     ; 3.034      ;
; 2.698 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[2]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.144     ; 3.032      ;
; 2.720 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[0]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.147     ; 3.007      ;
; 2.734 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[6]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.144     ; 2.996      ;
; 2.739 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[4]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.144     ; 2.991      ;
; 2.740 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[14]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.144     ; 2.990      ;
; 2.747 ; SDRAM_READ_ENABLE       ; ram_do_reg[30]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.182     ; 2.945      ;
; 2.747 ; SDRAM_READ_ENABLE       ; ram_do_reg[22]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.182     ; 2.945      ;
; 2.747 ; SDRAM_READ_ENABLE       ; ram_do_reg[31]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.182     ; 2.945      ;
; 2.747 ; SDRAM_READ_ENABLE       ; ram_do_reg[27]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.182     ; 2.945      ;
; 2.747 ; SDRAM_READ_ENABLE       ; ram_do_reg[24]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.182     ; 2.945      ;
; 2.747 ; SDRAM_READ_ENABLE       ; ram_do_reg[17]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.182     ; 2.945      ;
+-------+-------------------------+----------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                                                                                                                                         ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                ; To Node                                                                 ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 9.765  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.100     ; 7.627      ;
; 9.864  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.100     ; 7.528      ;
; 10.060 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.100     ; 7.332      ;
; 10.254 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 7.139      ;
; 10.256 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.100     ; 7.136      ;
; 10.301 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 7.092      ;
; 10.311 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.100     ; 7.081      ;
; 10.358 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 7.035      ;
; 10.405 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.100     ; 6.987      ;
; 10.410 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.100     ; 6.982      ;
; 10.415 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 6.978      ;
; 10.416 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 6.977      ;
; 10.474 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.100     ; 6.918      ;
; 10.485 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.100     ; 6.907      ;
; 10.500 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 6.893      ;
; 10.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 6.890      ;
; 10.565 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.100     ; 6.827      ;
; 10.577 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.156     ; 6.759      ;
; 10.601 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.134     ; 6.757      ;
; 10.662 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 6.731      ;
; 10.697 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.156     ; 6.639      ;
; 10.737 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 6.656      ;
; 10.740 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 6.653      ;
; 10.759 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.156     ; 6.577      ;
; 10.766 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 6.627      ;
; 10.812 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 6.581      ;
; 10.813 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 6.580      ;
; 10.831 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.100     ; 6.561      ;
; 10.862 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 6.531      ;
; 10.864 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.134     ; 6.494      ;
; 10.898 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.156     ; 6.438      ;
; 10.915 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.134     ; 6.443      ;
; 10.925 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 6.468      ;
; 10.940 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.134     ; 6.418      ;
; 11.006 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.156     ; 6.330      ;
; 11.042 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 6.351      ;
; 11.070 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.156     ; 6.266      ;
; 11.084 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.135     ; 6.273      ;
; 11.086 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 6.307      ;
; 11.124 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.134     ; 6.234      ;
; 11.175 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 6.218      ;
; 11.187 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 6.206      ;
; 11.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.156     ; 6.142      ;
; 11.229 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.134     ; 6.129      ;
; 11.258 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 6.135      ;
; 11.290 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 6.103      ;
; 11.296 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 6.097      ;
; 11.305 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.154     ; 6.033      ;
; 11.372 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.100     ; 6.020      ;
; 11.390 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 6.003      ;
; 11.408 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 5.985      ;
; 11.421 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 5.972      ;
; 11.435 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 5.958      ;
; 11.442 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 5.951      ;
; 11.456 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 5.937      ;
; 11.507 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 5.886      ;
; 11.560 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.452     ; 5.610      ;
; 11.563 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 5.830      ;
; 11.591 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.135     ; 5.766      ;
; 11.602 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.466     ; 5.554      ;
; 11.604 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 5.789      ;
; 11.618 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 5.775      ;
; 11.660 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.449     ; 5.513      ;
; 11.677 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.156     ; 5.659      ;
; 11.733 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.156     ; 5.603      ;
; 11.749 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.452     ; 5.421      ;
; 11.751 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.135     ; 5.606      ;
; 11.784 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 5.609      ;
; 11.818 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.449     ; 5.355      ;
; 11.820 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.466     ; 5.336      ;
; 11.832 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.466     ; 5.324      ;
; 11.866 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.451     ; 5.305      ;
; 11.876 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.135     ; 5.481      ;
; 11.882 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.135     ; 5.475      ;
; 11.933 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 5.460      ;
; 11.984 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.466     ; 5.172      ;
; 11.986 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.452     ; 5.184      ;
; 12.030 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.452     ; 5.140      ;
; 12.031 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.449     ; 5.142      ;
; 12.067 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.135     ; 5.290      ;
; 12.177 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.466     ; 4.979      ;
; 12.191 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 5.202      ;
; 12.330 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.466     ; 4.826      ;
; 12.355 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 5.038      ;
; 12.365 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.466     ; 4.791      ;
; 12.459 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 4.936      ;
; 12.469 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.468     ; 4.685      ;
; 12.485 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 4.908      ;
; 12.528 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.156     ; 4.808      ;
; 12.552 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.098     ; 4.842      ;
; 12.634 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 4.759      ;
; 12.690 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 4.705      ;
; 12.779 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 4.616      ;
; 12.808 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 4.585      ;
; 12.918 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.156     ; 4.418      ;
; 12.944 ; sdram_reset_n_reg                                                                                                                                                        ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|hsync_in_reg  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 4.508      ;
; 12.986 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 4.409      ;
; 13.035 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.156     ; 4.301      ;
; 13.160 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.100     ; 4.232      ;
; 13.216 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 4.179      ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                        ; To Node                                                                                                                                                                                                          ; Launch Clock                                                                  ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -1.725 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.572      ; 1.167      ;
; -1.690 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.582      ; 1.212      ;
; -1.689 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.582      ; 1.213      ;
; -1.689 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.582      ; 1.213      ;
; -1.686 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.582      ; 1.216      ;
; -1.679 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.566      ; 1.207      ;
; -1.667 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.582      ; 1.235      ;
; -1.643 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.582      ; 1.259      ;
; -1.641 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.582      ; 1.261      ;
; -1.637 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.572      ; 1.255      ;
; -1.636 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.566      ; 1.250      ;
; -1.636 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.572      ; 1.256      ;
; -1.635 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.558      ; 1.243      ;
; -1.626 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.582      ; 1.276      ;
; -1.625 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.571      ; 1.266      ;
; -1.624 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.572      ; 1.268      ;
; -1.620 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.571      ; 1.271      ;
; -1.619 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.571      ; 1.272      ;
; -1.619 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.571      ; 1.272      ;
; -1.609 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.571      ; 1.282      ;
; -1.608 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.571      ; 1.283      ;
; -1.605 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.571      ; 1.286      ;
; -1.603 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg_reg1                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.558      ; 1.275      ;
; -1.603 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.566      ; 1.283      ;
; -1.602 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.571      ; 1.289      ;
; -1.600 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.559      ; 1.279      ;
; -1.589 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.558      ; 1.289      ;
; -1.588 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn_reg1                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.570      ; 1.302      ;
; -1.587 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.571      ; 1.304      ;
; -1.587 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.558      ; 1.291      ;
; -1.574 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.558      ; 1.304      ;
; -1.560 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.566      ; 1.326      ;
; -1.558 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[0]                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.557      ; 1.319      ;
; -1.534 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.566      ; 1.352      ;
; -1.490 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.570      ; 1.400      ;
; -1.478 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.559      ; 1.401      ;
; -1.432 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate_reg1                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.557      ; 1.445      ;
; -1.424 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.566      ; 1.462      ;
; -1.418 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.566      ; 1.468      ;
; -1.349 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.566      ; 1.537      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.011                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.011                         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.001                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.001                         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortReq                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortReq                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1110      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1110      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1111      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1111      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[0]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[0]               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferInIndex[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferInIndex[0]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferInIndex[1]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferInIndex[1]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[0]     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[0]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[1]     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[1]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxBits[1]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxBits[1]                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1]                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0]                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3]                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2]                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[4]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[4]                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6]                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[1]                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[1]                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.010 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.010 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|rstCRC                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|rstCRC                    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1110   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1110   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[7]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[7]                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[1]              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[1]              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1100  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1100  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketCPReady         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketCPReady         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000100                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000100                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010100                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010100                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010101                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010101                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011011                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011011                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011100                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011100                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001110                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001110                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|getPacketREn                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|getPacketREn                                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01101                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01101                                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00010                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00010                                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001101                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001101                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011010                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011010                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001011                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001011                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXTimeOut                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXTimeOut                                             ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID[2]                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID[2]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID[0]                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[0]          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[0]          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01010                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01010                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00110                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00110                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00111                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00111                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.100                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.100                         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.010                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.010                         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortWEn                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortWEn                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011111  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011111  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|processTxByteWEn        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|processTxByteWEn        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutCtrl[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutCtrl[0]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutCtrl[1]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutCtrl[1]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortCntl[0]                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortCntl[0]                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxBits[0]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxBits[0]                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1101      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1101      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[0]                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[0]                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[0]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[0]                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                                                                                                                                                                       ;
+-------+--------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                        ; To Node                                                                                                                                                                       ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 0.370 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_datain_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.586      ; 1.230      ;
; 0.453 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_hsync_reg                          ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_hsync_reg                                                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.746      ;
; 0.454 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|buffer_select_reg                      ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|buffer_select_reg                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.746      ;
; 0.466 ; half_scandouble_enable_reg                                                                       ; half_scandouble_enable_reg                                                                                                                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.758      ;
; 0.484 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[3] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_datain_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.600      ; 1.358      ;
; 0.484 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[0]    ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_hsync_reg                                                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.777      ;
; 0.500 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_datain_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.600      ; 1.374      ;
; 0.501 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[85]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[84]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.793      ;
; 0.501 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[44]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[43]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.793      ;
; 0.501 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[125]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[124]                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.794      ;
; 0.501 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[1]    ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[0]                                                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.794      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[98]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[97]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.794      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[97]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[96]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.794      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[90]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[89]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.794      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[89]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[88]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.794      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[83]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[82]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.794      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[41]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[40]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.794      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[40]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[39]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.794      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[10]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[9]                                                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.794      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[3]    ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[2]                                                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.795      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[2]    ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[1]                                                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.795      ;
; 0.503 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_datain_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.600      ; 1.377      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[121]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[120]                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.794      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[120]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[119]                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.794      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[119]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[118]                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.794      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[118]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[117]                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.794      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[111]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[110]                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.794      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[104]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[103]                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.795      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[101]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[100]                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.795      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[100]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[99]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.795      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[96]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[95]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.795      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[88]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[87]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.795      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[82]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[81]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.795      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[81]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[80]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.795      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[76]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[75]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.794      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[73]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[72]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.794      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[70]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[69]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.794      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[68]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[67]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.794      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[63]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[62]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.794      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[62]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[61]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.794      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[60]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[59]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.794      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[56]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[55]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.794      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[55]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[54]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.794      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[45]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[44]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.795      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[42]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[41]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.795      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[30]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[29]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.794      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[29]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[28]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.794      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[18]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[17]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.795      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[17]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[16]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.795      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[13]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[12]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.795      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[126]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[125]                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.796      ;
; 0.504 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[115]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[114]                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.795      ;
; 0.504 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[114]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[113]                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.795      ;
; 0.504 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[113]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[112]                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.795      ;
; 0.504 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[110]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[109]                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.795      ;
; 0.504 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[105]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[104]                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.796      ;
; 0.504 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[91]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[90]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.796      ;
; 0.504 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[74]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[73]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.795      ;
; 0.504 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[71]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[70]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.795      ;
; 0.504 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[66]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[65]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.795      ;
; 0.504 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[59]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[58]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.795      ;
; 0.504 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[58]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[57]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.795      ;
; 0.504 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[46]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[45]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.796      ;
; 0.504 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[39]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[38]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.796      ;
; 0.504 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[37]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[36]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.796      ;
; 0.504 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[34]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[33]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.795      ;
; 0.504 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[33]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[32]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.795      ;
; 0.504 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[28]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[27]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.795      ;
; 0.504 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[27]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[26]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.795      ;
; 0.504 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[24]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[23]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.795      ;
; 0.504 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[15]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[14]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.796      ;
; 0.504 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[14]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[13]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.796      ;
; 0.504 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[9]    ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[8]                                                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.796      ;
; 0.504 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[7]    ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[6]                                                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.796      ;
; 0.505 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[106]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[105]                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.797      ;
; 0.505 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[86]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[85]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.797      ;
; 0.505 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[54]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[53]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.796      ;
; 0.505 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[48]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[47]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.797      ;
; 0.505 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[47]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[46]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.797      ;
; 0.505 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[8]    ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[7]                                                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.797      ;
; 0.506 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[53]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[52]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.797      ;
; 0.509 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[10]                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[10]                                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.801      ;
; 0.515 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_datain_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.600      ; 1.389      ;
; 0.516 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[10]                 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[10]                                                                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.809      ;
; 0.520 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[3] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_datain_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.583      ; 1.377      ;
; 0.539 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_datain_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.600      ; 1.413      ;
; 0.545 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_datain_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.586      ; 1.405      ;
; 0.621 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_datain_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.583      ; 1.478      ;
; 0.631 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_datain_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.599      ; 1.504      ;
; 0.660 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_datain_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.583      ; 1.517      ;
; 0.672 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_datain_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.586      ; 1.532      ;
; 0.687 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_datain_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.582      ; 1.543      ;
; 0.687 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[51]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[50]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.978      ;
; 0.687 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[35]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[34]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.978      ;
; 0.688 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[23]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[22]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.979      ;
; 0.688 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[22]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[21]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.979      ;
; 0.691 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|buffer_select_reg                      ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.983      ;
; 0.692 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|buffer_select_reg                      ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.984      ;
; 0.694 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[108]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[107]                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.986      ;
; 0.695 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[77]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[76]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.987      ;
+-------+--------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                              ;
+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                  ; To Node                                                                                                                                                                                    ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_noise_filter:pokey_noise_filter3|out_reg                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_noise_filter:pokey_noise_filter3|out_reg                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[370]                                                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[370]                                                                                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; paddle_mode_reg                                                                                                                                                                            ; paddle_mode_reg                                                                                                                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[46]                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[46]                                                                                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[50]                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[50]                                                                                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[118]                                                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[118]                                                                                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[12]                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[12]                                                                                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[58]                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[58]                                                                                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[13]                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[13]                                                                                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[44]                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[44]                                                                                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[67]                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[67]                                                                                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[90]                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[90]                                                                                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[6]                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[6]                                                                                                                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[66]                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[66]                                                                                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[84]                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[84]                                                                                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[29]                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[29]                                                                                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[30]                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[30]                                                                                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[78]                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[78]                                                                                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[82]                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[82]                                                                                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[34]                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[34]                                                                                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[85]                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[85]                                                                                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[93]                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[93]                                                                                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[28]                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[28]                                                                                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[22]                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[22]                                                                                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[21]                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[21]                                                                                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[68]                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[68]                                                                                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[45]                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[45]                                                                                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[37]                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[37]                                                                                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[51]                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[51]                                                                                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[364]                                                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[364]                                                                                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[3]                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[3]                                                                                                                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[70]                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[70]                                                                                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[42]                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[42]                                                                                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[49]                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[49]                                                                                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[53]                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[53]                                                                                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[69]                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[69]                                                                                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[61]                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[61]                                                                                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[35]                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[35]                                                                                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[54]                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[54]                                                                                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[77]                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[77]                                                                                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[76]                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[76]                                                                                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[5]                                                                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[5]                                                                                                                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[60]                                                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[60]                                                                                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|state_reg[0]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|state_reg[0]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|state_reg[1]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|state_reg[1]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[276]                                                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[276]                                                                                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[119]                                                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[119]                                                                                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|count_reg[1]                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|count_reg[1]                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|shift_reg[6]                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|shift_reg[6]                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[120]                                                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[120]                                                                                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[372]                                                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[372]                                                                                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[373]                                                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[373]                                                                                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInt        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInt        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_count_reg[1]                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_count_reg[1]                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_count_reg[2]                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_count_reg[2]                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_count_reg[3]                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_count_reg[3]                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[1]                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[1]                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[2]                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[2]                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[3]                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[3]                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[4]                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[4]                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[5]                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[5]                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[6]                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[6]                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[7]                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[7]                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[0]                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[0]                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                                                                                                                         ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[5]                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[5]                                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[4]                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[4]                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[9]                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[9]                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|last_line_of_instruction_reg                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|last_line_of_instruction_reg                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[0]                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[0]                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Creg                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Creg                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Vreg                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Vreg                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[5]                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[5]                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cyclePreIndirect                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cyclePreIndirect                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cycleBranchTaken                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cycleBranchTaken                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[1]                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[1]                                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[0]                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[0]                                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|state[0]                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|state[0]                                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|state[2]                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|state[2]                                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|vector_a2                                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|vector_a2                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|use_status_as_ram_address                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|use_status_as_ram_address                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|skctl_reg[0]                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|skctl_reg[0]                                                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|skctl_reg[1]                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|skctl_reg[1]                                                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pot_reset_reg                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pot_reset_reg                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot_reset_reg                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot_reset_reg                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[7]                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[7]                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[0]                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[0]                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[1]                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[1]                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[2]                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[2]                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf1_reg[3]                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf1_reg[3]                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf1_reg[0]                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf1_reg[0]                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf1_reg[1]                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf1_reg[1]                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf1_reg[2]                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf1_reg[2]                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf1_reg[7]                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf1_reg[7]                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf1_reg[4]                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf1_reg[4]                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf1_reg[6]                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf1_reg[6]                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[0]                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[0]                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[1]                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[1]                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                            ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                 ; To Node                                                   ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 0.454 ; sdram_request_reg                                         ; sdram_request_reg                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; sdram_request_complete_reg                                ; sdram_request_complete_reg                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|sdram_rdy                     ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_refr_act                    ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_rd_act                      ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_wr_act                      ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.466 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.758      ;
; 0.467 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.758      ;
; 0.504 ; ram_bena_reg[0]                                           ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.795      ;
; 0.506 ; ram_bena_reg[1]                                           ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.797      ;
; 0.542 ; seq_reg[10]                                               ; seq_reg[11]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.833      ;
; 0.560 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.851      ;
; 0.566 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.857      ;
; 0.581 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.872      ;
; 0.652 ; sdram_ctrl:sdram_controller|r_rd_act                      ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.943      ;
; 0.675 ; seq_reg[9]                                                ; seq_reg[10]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.966      ;
; 0.705 ; sdram_ctrl:sdram_controller|r_wr_act                      ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.996      ;
; 0.728 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.019      ;
; 0.737 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.029      ;
; 0.738 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.030      ;
; 0.738 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.030      ;
; 0.738 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.030      ;
; 0.739 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.031      ;
; 0.739 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.031      ;
; 0.741 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.033      ;
; 0.741 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.033      ;
; 0.744 ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.035      ;
; 0.745 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.036      ;
; 0.749 ; seq_reg[1]                                                ; seq_reg[2]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.040      ;
; 0.755 ; sdram_ctrl:sdram_controller|r_refr_req                    ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.047      ;
; 0.757 ; sdram_ctrl:sdram_controller|r_refr_req                    ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.049      ;
; 0.758 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.050      ;
; 0.758 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.050      ;
; 0.785 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.076      ;
; 0.803 ; sdram_ctrl:sdram_controller|r_rd_act                      ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.094      ;
; 0.852 ; sdram_request_complete_reg                                ; sdram_request_reg                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.144      ;
; 0.895 ; sdram_ctrl:sdram_controller|r_refr_act                    ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.186      ;
; 0.961 ; seq_reg[11]                                               ; seq_reg[0]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.252      ;
; 0.966 ; seq_reg[2]                                                ; seq_reg[3]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.257      ;
; 0.968 ; seq_reg[3]                                                ; seq_reg[4]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.259      ;
; 1.023 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.314      ;
; 1.038 ; sdram_ctrl:sdram_controller|r_wr_act                      ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.329      ;
; 1.056 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.347      ;
; 1.057 ; sdram_ctrl:sdram_controller|r_wr_act                      ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.348      ;
; 1.061 ; sdram_ctrl:sdram_controller|r_wr_act                      ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.352      ;
; 1.072 ; seq_reg[4]                                                ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.362      ;
; 1.092 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.384      ;
; 1.092 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.384      ;
; 1.093 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.385      ;
; 1.093 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.385      ;
; 1.099 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.391      ;
; 1.100 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.392      ;
; 1.101 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.393      ;
; 1.102 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.394      ;
; 1.102 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.394      ;
; 1.108 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.400      ;
; 1.109 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.401      ;
; 1.110 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.402      ;
; 1.111 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.403      ;
; 1.111 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.403      ;
; 1.135 ; sdram_ctrl:sdram_controller|r_refr_act                    ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.426      ;
; 1.150 ; sdram_ctrl:sdram_controller|r_refr_req                    ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.442      ;
; 1.155 ; seq_reg[5]                                                ; seq_reg[6]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.446      ;
; 1.166 ; sdram_ctrl:sdram_controller|r_psel[0]                     ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.457      ;
; 1.185 ; seq_reg[4]                                                ; seq_reg[5]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.476      ;
; 1.187 ; seq_reg[6]                                                ; seq_reg[7]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.478      ;
; 1.201 ; seq_reg[8]                                                ; seq_reg[9]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.492      ;
; 1.213 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.504      ;
; 1.223 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.515      ;
; 1.224 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.516      ;
; 1.224 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.516      ;
; 1.232 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.524      ;
; 1.233 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.525      ;
; 1.233 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.525      ;
; 1.240 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.532      ;
; 1.241 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.533      ;
; 1.242 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.534      ;
; 1.242 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.534      ;
; 1.249 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.541      ;
; 1.250 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.542      ;
; 1.251 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.543      ;
; 1.251 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.543      ;
; 1.253 ; sdram_ctrl:sdram_controller|r_refr_req                    ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.545      ;
; 1.294 ; sdram_ctrl:sdram_controller|r_psel[0]                     ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.585      ;
; 1.297 ; sdram_ctrl:sdram_controller|r_psel[0]                     ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.588      ;
; 1.298 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.589      ;
; 1.311 ; seq_reg[0]                                                ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.601      ;
; 1.351 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.642      ;
; 1.356 ; seq_reg[11]                                               ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.646      ;
; 1.358 ; seq_reg[11]                                               ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.648      ;
; 1.361 ; sdram_ctrl:sdram_controller|r_rddata[15]                  ; ram_do_reg[15]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.260      ; 1.833      ;
; 1.363 ; sdram_ctrl:sdram_controller|r_rddata[15]                  ; ram_do_reg[7]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.260      ; 1.835      ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                               ;
+-------+---------------------------------------+--------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                                                                              ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+--------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[4]                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 5.349      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[29]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.192     ; 5.334      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[16]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.182     ; 5.344      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[17]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.182     ; 5.344      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[18]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.182     ; 5.344      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[19]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.182     ; 5.344      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[20]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.182     ; 5.344      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[21]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.182     ; 5.344      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[22]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.182     ; 5.344      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[23]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.182     ; 5.344      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[24]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.182     ; 5.344      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[25]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.182     ; 5.344      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[7]                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 5.350      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[28]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.192     ; 5.334      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[26]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.182     ; 5.344      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[27]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.182     ; 5.344      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[28]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.182     ; 5.344      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[29]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.182     ; 5.344      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[30]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.182     ; 5.344      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[30]                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.183     ; 5.343      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[30]                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.183     ; 5.343      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[3]                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 5.349      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[4]                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 5.349      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[4]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 5.349      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[2]                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 5.349      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[21]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.192     ; 5.334      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[31]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.182     ; 5.344      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[31]                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.180     ; 5.346      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[31]                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 5.349      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[31]                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.180     ; 5.346      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[31]                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 5.349      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[27]                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.183     ; 5.343      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[27]                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.183     ; 5.343      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[12]                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 5.349      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[6]                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 5.349      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[6]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 5.349      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[7]                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 5.349      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[7]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 5.349      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[5]                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 5.349      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[16]                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.180     ; 5.346      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[13]                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 5.349      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[4]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 5.349      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[1]                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 5.349      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[0]                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 5.349      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[0]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 5.349      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[24]                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.183     ; 5.343      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[25]                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.183     ; 5.343      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[26]                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.183     ; 5.343      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[28]                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.183     ; 5.343      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[29]                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.183     ; 5.343      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|target_reg[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.190     ; 5.336      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|target_reg[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.190     ; 5.336      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|target_reg[2]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.190     ; 5.336      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audctl_reg[6] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.190     ; 5.336      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[13]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 5.350      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[3]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 5.349      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[5]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 5.349      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[2]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 5.349      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[13]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.180     ; 5.346      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[4]                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.180     ; 5.346      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[5]                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.180     ; 5.346      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[8]                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.180     ; 5.346      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[9]                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.180     ; 5.346      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[28]                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.180     ; 5.346      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[28]                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.180     ; 5.346      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[28]                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.183     ; 5.343      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[20]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.192     ; 5.334      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[20]                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.180     ; 5.346      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[20]                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.180     ; 5.346      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[8]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.182     ; 5.344      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[10]                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.182     ; 5.344      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[14]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 5.350      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[11]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.180     ; 5.346      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[18]                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 5.349      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[18]                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 5.349      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[25]                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.183     ; 5.343      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[25]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.192     ; 5.334      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[29]                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.183     ; 5.343      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[24]                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.183     ; 5.343      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[24]                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.180     ; 5.346      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[24]                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.180     ; 5.346      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[9]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 5.349      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[9]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 5.349      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[19]                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.185     ; 5.341      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[19]                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.185     ; 5.341      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[6]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 5.349      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[6]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 5.349      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[6]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.180     ; 5.346      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[14]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.180     ; 5.346      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[12]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.180     ; 5.346      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[4]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 5.349      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[10]                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.180     ; 5.346      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[10]                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.180     ; 5.346      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 5.349      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[8]                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.180     ; 5.346      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[8]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 5.349      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[8]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 5.349      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[14]                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.180     ; 5.346      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[0]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 5.349      ;
; 6.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[15]                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.180     ; 5.346      ;
+-------+---------------------------------------+--------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                     ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                                   ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 7.730 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[0]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.397     ; 3.479      ;
; 7.730 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[1]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.397     ; 3.479      ;
; 7.730 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[2]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.397     ; 3.479      ;
; 7.732 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[3]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.398     ; 3.476      ;
; 7.732 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[7]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.398     ; 3.476      ;
; 7.737 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[5]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.400     ; 3.469      ;
; 7.738 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[6]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.396     ; 3.472      ;
; 7.738 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[4]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.402     ; 3.466      ;
; 7.742 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[0]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.270     ; 3.606      ;
; 7.742 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[1]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.270     ; 3.606      ;
; 7.742 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[2]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.270     ; 3.606      ;
; 7.744 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[3]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.271     ; 3.603      ;
; 7.744 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[7]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.271     ; 3.603      ;
; 7.749 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[5]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.273     ; 3.596      ;
; 7.750 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[4]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.275     ; 3.593      ;
; 7.750 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[6]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.269     ; 3.599      ;
; 7.755 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[0]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.215     ; 3.648      ;
; 7.755 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[1]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.215     ; 3.648      ;
; 7.755 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[2]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.215     ; 3.648      ;
; 7.755 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[3]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.215     ; 3.648      ;
; 7.755 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.213     ; 3.650      ;
; 7.755 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.215     ; 3.648      ;
; 7.755 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.215     ; 3.648      ;
; 7.757 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[13]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.386     ; 3.463      ;
; 7.757 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[12]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.388     ; 3.461      ;
; 7.757 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[14]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.386     ; 3.463      ;
; 7.757 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[15]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.386     ; 3.463      ;
; 7.757 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[11]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.388     ; 3.461      ;
; 7.757 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[10]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.388     ; 3.461      ;
; 7.758 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[8]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.384     ; 3.464      ;
; 7.760 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[9]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.388     ; 3.458      ;
; 7.769 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[10]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.261     ; 3.588      ;
; 7.769 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[11]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.261     ; 3.588      ;
; 7.769 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[12]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.261     ; 3.588      ;
; 7.769 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[13]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.259     ; 3.590      ;
; 7.769 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[14]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.259     ; 3.590      ;
; 7.769 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[15]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.259     ; 3.590      ;
; 7.770 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[8]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.257     ; 3.591      ;
; 7.772 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[9]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.261     ; 3.585      ;
; 7.780 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[4]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.200     ; 3.638      ;
; 7.780 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[6]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.202     ; 3.636      ;
; 7.780 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[7]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.202     ; 3.636      ;
; 7.780 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[8]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.201     ; 3.637      ;
; 7.780 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.201     ; 3.637      ;
; 7.781 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[5]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.201     ; 3.636      ;
; 7.830 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.206     ; 3.712      ;
; 7.830 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.206     ; 3.712      ;
; 7.830 ; sdram_reset_ctrl_n_reg ; ram_do_reg[15]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.206     ; 3.712      ;
; 7.867 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.208     ; 3.673      ;
; 7.867 ; sdram_reset_ctrl_n_reg ; ram_do_reg[11]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.208     ; 3.673      ;
; 7.874 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.206     ; 3.668      ;
; 7.874 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.206     ; 3.668      ;
; 7.879 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.218     ; 3.651      ;
; 7.879 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.218     ; 3.651      ;
; 7.879 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.218     ; 3.651      ;
; 7.879 ; sdram_reset_ctrl_n_reg ; ram_do_reg[20]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.218     ; 3.651      ;
; 7.879 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.218     ; 3.651      ;
; 7.879 ; sdram_reset_ctrl_n_reg ; ram_do_reg[25]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.218     ; 3.651      ;
; 7.879 ; sdram_reset_ctrl_n_reg ; ram_do_reg[19]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.218     ; 3.651      ;
; 7.879 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.218     ; 3.651      ;
; 7.879 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.218     ; 3.651      ;
; 7.879 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.218     ; 3.651      ;
; 7.880 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.218     ; 3.650      ;
; 7.880 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.218     ; 3.650      ;
; 7.880 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.218     ; 3.650      ;
; 7.880 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.218     ; 3.650      ;
; 7.880 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.218     ; 3.650      ;
; 7.880 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.218     ; 3.650      ;
; 8.038 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.213     ; 3.367      ;
; 8.038 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.213     ; 3.367      ;
; 8.038 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.213     ; 3.367      ;
; 8.038 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.213     ; 3.367      ;
; 8.350 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.195      ;
; 8.350 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.195      ;
; 8.350 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.195      ;
; 8.350 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.195      ;
; 8.350 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.195      ;
; 8.350 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.195      ;
; 8.350 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.195      ;
; 8.350 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.195      ;
; 8.350 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.195      ;
; 8.350 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.195      ;
; 8.350 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.195      ;
; 8.350 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.195      ;
; 8.350 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.195      ;
; 8.350 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.195      ;
; 8.350 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.195      ;
; 8.350 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.204     ; 3.194      ;
; 8.350 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.195      ;
; 8.350 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.195      ;
; 8.350 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.195      ;
; 8.350 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.195      ;
; 8.350 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.195      ;
; 8.350 ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.195      ;
; 8.350 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.195      ;
; 8.350 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.195      ;
; 8.350 ; sdram_reset_ctrl_n_reg ; ram_di_reg[15]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.195      ;
; 8.350 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.195      ;
; 8.350 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.204     ; 3.194      ;
; 8.350 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.204     ; 3.194      ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                       ;
+--------+-------------------+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node         ; To Node                                                                                         ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 11.432 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vsync_reg                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.190     ; 5.870      ;
; 11.432 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.189     ; 5.871      ;
; 11.432 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.189     ; 5.871      ;
; 11.432 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.189     ; 5.871      ;
; 11.433 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|hsync_reg                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.190     ; 5.869      ;
; 11.433 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.189     ; 5.870      ;
; 11.433 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.190     ; 5.869      ;
; 11.433 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.190     ; 5.869      ;
; 11.433 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.189     ; 5.870      ;
; 11.433 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.189     ; 5.870      ;
; 11.434 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.246     ; 5.812      ;
; 11.434 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.246     ; 5.812      ;
; 11.470 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.224     ; 5.798      ;
; 11.470 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.225     ; 5.797      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[123] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[122] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[121] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[120] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[119] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[118] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[117] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[116] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[115] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[114] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[113] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[112] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[111] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[110] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[109] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[108] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[107] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[106] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[105] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[104] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[103] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[102] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[101] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[100] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[99]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[98]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[97]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[96]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[95]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[94]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[93]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[92]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[91]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[90]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[89]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[88]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[87]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[86]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[85]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[84]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[83]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[82]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[81]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[80]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[79]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[78]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[77]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[76]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.193     ; 5.479      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[75]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.193     ; 5.479      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[74]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.193     ; 5.479      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[73]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.193     ; 5.479      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[72]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.193     ; 5.479      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[71]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.193     ; 5.479      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[70]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.193     ; 5.479      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[69]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.193     ; 5.479      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[68]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.193     ; 5.479      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[67]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.193     ; 5.479      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[50]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[49]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[48]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[47]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[46]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[45]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[44]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[43]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[42]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[41]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[40]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[39]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[38]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[37]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[36]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[35]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[34]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[33]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[32]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[31]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[30]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[29]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[28]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[27]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[26]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[25]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[24]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[23]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 5.478      ;
; 11.950 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[21]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.195     ; 5.477      ;
+--------+-------------------+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                      ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                                   ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 2.605 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 3.015      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 3.015      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 3.015      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 3.015      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 3.015      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; seq_reg[5]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 3.015      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 3.015      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 3.015      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 3.015      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 3.015      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 3.015      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 3.015      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 3.014      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 3.014      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; ram_do_reg[5]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 3.014      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 3.014      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; ram_do_reg[13]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 3.014      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 3.014      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; ram_do_reg[9]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 3.014      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; ram_do_reg[14]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 3.014      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; ram_do_reg[12]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 3.014      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 3.014      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; ram_do_reg[8]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 3.014      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 3.015      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 3.015      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; ram_di_reg[6]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 3.015      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 3.015      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; ram_di_reg[11]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 3.015      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; ram_di_reg[12]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 3.015      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; ram_di_reg[14]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 3.015      ;
; 2.606 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 3.015      ;
; 2.606 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 3.016      ;
; 2.606 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 3.016      ;
; 2.606 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 3.016      ;
; 2.606 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 3.016      ;
; 2.606 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 3.016      ;
; 2.606 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 3.016      ;
; 2.606 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 3.016      ;
; 2.606 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 3.016      ;
; 2.606 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 3.016      ;
; 2.606 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 3.016      ;
; 2.606 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 3.015      ;
; 2.606 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 3.015      ;
; 2.606 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 3.015      ;
; 2.606 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 3.015      ;
; 2.606 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 3.015      ;
; 2.606 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 3.015      ;
; 2.606 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 3.015      ;
; 2.606 ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 3.015      ;
; 2.606 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 3.015      ;
; 2.606 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 3.015      ;
; 2.606 ; sdram_reset_ctrl_n_reg ; ram_di_reg[15]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 3.015      ;
; 2.606 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 3.015      ;
; 2.606 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 3.015      ;
; 2.607 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 3.016      ;
; 2.607 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 3.016      ;
; 2.607 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 3.016      ;
; 2.607 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 3.016      ;
; 2.607 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 3.016      ;
; 2.607 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 3.016      ;
; 2.607 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 3.016      ;
; 2.607 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 3.016      ;
; 2.607 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 3.016      ;
; 2.607 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 3.016      ;
; 2.607 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 3.016      ;
; 2.607 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[0]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 3.016      ;
; 2.607 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 3.016      ;
; 2.607 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[1]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 3.016      ;
; 2.607 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 3.016      ;
; 2.609 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.172      ; 3.012      ;
; 2.609 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.015      ;
; 2.609 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.015      ;
; 2.609 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.015      ;
; 2.609 ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.015      ;
; 2.870 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.173      ; 3.188      ;
; 2.870 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.173      ; 3.188      ;
; 2.871 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.172      ; 3.188      ;
; 2.871 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.172      ; 3.188      ;
; 3.050 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.163      ; 3.444      ;
; 3.050 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.163      ; 3.444      ;
; 3.050 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 3.443      ;
; 3.050 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 3.443      ;
; 3.050 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.163      ; 3.444      ;
; 3.050 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 3.443      ;
; 3.050 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 3.443      ;
; 3.050 ; sdram_reset_ctrl_n_reg ; ram_do_reg[20]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.163      ; 3.444      ;
; 3.050 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.163      ; 3.444      ;
; 3.050 ; sdram_reset_ctrl_n_reg ; ram_do_reg[25]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.163      ; 3.444      ;
; 3.050 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 3.443      ;
; 3.050 ; sdram_reset_ctrl_n_reg ; ram_do_reg[19]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.163      ; 3.444      ;
; 3.050 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 3.443      ;
; 3.050 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.163      ; 3.444      ;
; 3.050 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.163      ; 3.444      ;
; 3.050 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.163      ; 3.444      ;
; 3.054 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 3.461      ;
; 3.054 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 3.461      ;
; 3.063 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.173      ; 3.467      ;
; 3.063 ; sdram_reset_ctrl_n_reg ; ram_do_reg[11]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.173      ; 3.467      ;
; 3.096 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.502      ;
; 3.096 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 3.503      ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                        ;
+-------+---------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                                                                                                                                      ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 4.075 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[5]                                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.648      ; 4.956      ;
; 4.528 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|state_reg[3]                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.965      ;
; 4.528 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|state_reg[0]                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.965      ;
; 4.528 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|command_reg                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.965      ;
; 4.528 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|state_reg[1]                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.965      ;
; 4.528 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|skctl_reg[4]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.965      ;
; 4.528 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf3_reg[6]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.965      ;
; 4.528 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer3|delay_line:underflow0_delay|shift_reg[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.965      ;
; 4.528 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|skctl_reg[5]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.965      ;
; 4.528 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|clock_reg                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.965      ;
; 4.528 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|clock_sync_reg                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.965      ;
; 4.528 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audctl_reg[7]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.965      ;
; 4.528 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[12]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.965      ;
; 4.528 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[11]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.201      ; 4.962      ;
; 4.528 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[10]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.201      ; 4.962      ;
; 4.528 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[9]                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.965      ;
; 4.528 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[8]                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.965      ;
; 4.528 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[7]                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.965      ;
; 4.528 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[6]                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.965      ;
; 4.528 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[5]                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.965      ;
; 4.528 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[4]                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.965      ;
; 4.528 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[3]                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.965      ;
; 4.528 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[2]                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.965      ;
; 4.528 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[1]                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.965      ;
; 4.528 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[0]                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.965      ;
; 4.528 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[15]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.965      ;
; 4.528 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[14]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.965      ;
; 4.528 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[13]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.965      ;
; 4.528 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|state_reg[2]                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.965      ;
; 4.528 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|skctl_reg[6]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.965      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.200      ; 4.962      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[8]                                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.200      ; 4.962      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[6]                                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.197      ; 4.959      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[30]                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.198      ; 4.960      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[4]                                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.197      ; 4.959      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[27]                                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.198      ; 4.960      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[27]                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.198      ; 4.960      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|sio_in_reg                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.203      ; 4.965      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|delay_line:stimer_delay|shift_reg[2]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.966      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|delay_line:stimer_delay|shift_reg[1]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.966      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|delay_line:stimer_delay|shift_reg[0]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.966      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf2_reg[5]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.966      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf2_reg[0]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.966      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf2_reg[1]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.966      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf2_reg[2]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.966      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf2_reg[3]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.966      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf2_reg[4]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.966      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf2_reg[7]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.966      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf2_reg[6]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.966      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf3_reg[2]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.966      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf3_reg[3]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.966      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf3_reg[7]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.966      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf3_reg[4]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.966      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|serin_bitcount_reg[1]                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.966      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|serin_bitcount_reg[2]                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.966      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|serin_bitcount_reg[3]                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.203      ; 4.965      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|serin_bitcount_reg[0]                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.966      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|irqst_reg[5]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.203      ; 4.965      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|skctl_reg[2]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.966      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|serial_ip_overrun_reg                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.203      ; 4.965      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|skctl_reg[3]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.966      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[0]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.966      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[0]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.966      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[2]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.966      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[1]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.966      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[1]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.966      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[2]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.966      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[3]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.966      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[3]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.966      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[4]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.966      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[4]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.966      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[6]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.966      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[5]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.966      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[5]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.966      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[6]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.966      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[7]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.966      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[7]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.966      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.966      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.966      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf1_reg[4]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.966      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|skctl_reg[7]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.966      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|delay_line:serout_clock_delay|shift_reg[1]                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.966      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|delay_line:serout_clock_delay|shift_reg[0]                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.966      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|serout_clock_reg                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.966      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|serout_clock_last_reg                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.966      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|serout_holding_full_reg                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.201      ; 4.963      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|serout_active_reg                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.966      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|serial_out_reg                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.966      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|twotone_reg                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.966      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|sio_out_reg                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 4.966      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[3]                                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.197      ; 4.959      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[29]                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.198      ; 4.960      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[5]                                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.197      ; 4.959      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[2]                                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.197      ; 4.959      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[1]                                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.197      ; 4.959      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[0]                                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.197      ; 4.959      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[9]                                                                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.201      ; 4.963      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[10]                                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.201      ; 4.963      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[26]                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.198      ; 4.960      ;
; 4.529 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[1]                                                                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.196      ; 4.958      ;
+-------+---------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                       ;
+-------+-------------------+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node         ; To Node                                                                                         ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 4.546 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[127] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.214      ; 4.992      ;
; 4.546 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[126] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.214      ; 4.992      ;
; 4.546 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[125] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.214      ; 4.992      ;
; 4.546 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[124] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.214      ; 4.992      ;
; 4.546 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[4]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.214      ; 4.992      ;
; 4.546 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[3]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.214      ; 4.992      ;
; 4.546 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[2]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.214      ; 4.992      ;
; 4.546 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[1]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.214      ; 4.992      ;
; 4.546 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[0]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.214      ; 4.992      ;
; 4.546 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_hsync_reg                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.214      ; 4.992      ;
; 4.547 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.212      ; 4.991      ;
; 4.547 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[2]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.212      ; 4.991      ;
; 4.547 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[3]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.212      ; 4.991      ;
; 4.547 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[4]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.212      ; 4.991      ;
; 4.547 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[5]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.212      ; 4.991      ;
; 4.547 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[6]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.212      ; 4.991      ;
; 4.547 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[7]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.212      ; 4.991      ;
; 4.547 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[8]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.212      ; 4.991      ;
; 4.547 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[9]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.212      ; 4.991      ;
; 4.547 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[10]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.212      ; 4.991      ;
; 4.547 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.212      ; 4.991      ;
; 4.547 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|buffer_select_reg                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.212      ; 4.991      ;
; 4.547 ; sdram_reset_n_reg ; half_scandouble_enable_reg                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.212      ; 4.991      ;
; 4.547 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.990      ;
; 4.547 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[1]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.990      ;
; 4.547 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[2]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.990      ;
; 4.547 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[3]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.990      ;
; 4.547 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[4]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.990      ;
; 4.547 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[5]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.990      ;
; 4.547 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[6]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.990      ;
; 4.547 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[7]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.990      ;
; 4.547 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[8]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.990      ;
; 4.547 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[9]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.990      ;
; 4.547 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[10]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.990      ;
; 4.547 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.210      ; 4.989      ;
; 4.547 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.212      ; 4.991      ;
; 4.547 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.212      ; 4.991      ;
; 4.547 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.212      ; 4.991      ;
; 4.547 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.212      ; 4.991      ;
; 4.547 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.212      ; 4.991      ;
; 4.547 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.212      ; 4.991      ;
; 4.547 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.212      ; 4.991      ;
; 4.587 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[107] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 5.007      ;
; 4.587 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[106] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 5.007      ;
; 4.587 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[105] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 5.007      ;
; 4.587 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[104] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 5.007      ;
; 4.587 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[103] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 5.007      ;
; 4.587 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[102] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 5.007      ;
; 4.587 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[101] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 5.007      ;
; 4.587 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[100] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 5.007      ;
; 4.587 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[99]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 5.007      ;
; 4.587 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[98]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 5.007      ;
; 4.587 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[97]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 5.007      ;
; 4.587 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[96]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 5.007      ;
; 4.587 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[95]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 5.007      ;
; 4.587 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[94]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 5.007      ;
; 4.587 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[93]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 5.007      ;
; 4.587 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[92]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 5.007      ;
; 4.587 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[91]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 5.007      ;
; 4.587 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[90]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 5.007      ;
; 4.587 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[89]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 5.007      ;
; 4.587 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[88]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 5.007      ;
; 4.587 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[87]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 5.007      ;
; 4.587 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[86]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 5.007      ;
; 4.587 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[85]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 5.007      ;
; 4.587 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[84]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 5.007      ;
; 4.587 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[83]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 5.007      ;
; 4.587 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[82]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 5.007      ;
; 4.587 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[81]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 5.007      ;
; 4.587 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[80]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 5.007      ;
; 4.587 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[79]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 5.007      ;
; 4.587 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[78]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 5.007      ;
; 4.587 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[77]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 5.007      ;
; 4.587 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[50]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 5.007      ;
; 4.587 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[49]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 5.007      ;
; 4.587 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[48]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 5.007      ;
; 4.587 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[47]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 5.007      ;
; 4.587 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[46]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 5.007      ;
; 4.587 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[45]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 5.007      ;
; 4.587 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[44]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 5.007      ;
; 4.587 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[43]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 5.007      ;
; 4.587 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[42]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 5.007      ;
; 4.587 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[41]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 5.007      ;
; 4.587 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[40]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 5.007      ;
; 4.587 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[39]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 5.007      ;
; 4.587 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[38]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 5.007      ;
; 4.587 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[37]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 5.007      ;
; 4.587 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[36]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 5.007      ;
; 4.587 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[35]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 5.007      ;
; 4.588 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[123] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 5.007      ;
; 4.588 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[122] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 5.007      ;
; 4.588 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[121] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 5.007      ;
; 4.588 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[120] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 5.007      ;
; 4.588 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[119] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 5.007      ;
; 4.588 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[118] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 5.007      ;
; 4.588 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[117] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 5.007      ;
; 4.588 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[116] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 5.007      ;
; 4.588 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[115] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 5.007      ;
; 4.588 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[114] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 5.007      ;
; 4.588 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[113] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 5.007      ;
+-------+-------------------+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                        ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                         ; Clock Edge ; Target                                                    ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[0]                                           ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[1]                                           ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[15]                                            ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[6]                                             ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[7]                                             ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_act                      ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_act                      ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[0]                                             ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[11]                                            ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[12]                                            ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[14]                                            ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[1]                                             ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[3]                                             ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[4]                                             ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[6]                                             ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[7]                                             ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[8]                                             ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[9]                                             ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[11]                                            ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[2]                                             ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[3]                                             ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_complete_reg                                ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_reg                                         ;
; 5.572 ; 5.792        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[0]                                             ;
; 5.572 ; 5.792        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[10]                                            ;
; 5.572 ; 5.792        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[12]                                            ;
; 5.572 ; 5.792        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[13]                                            ;
; 5.572 ; 5.792        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[14]                                            ;
; 5.572 ; 5.792        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[1]                                             ;
; 5.572 ; 5.792        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[4]                                             ;
; 5.572 ; 5.792        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[5]                                             ;
; 5.572 ; 5.792        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[8]                                             ;
; 5.572 ; 5.792        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[9]                                             ;
; 5.572 ; 5.792        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel[0]                     ;
; 5.572 ; 5.792        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[0]                                                ;
; 5.572 ; 5.792        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[10]                                               ;
; 5.572 ; 5.792        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[11]                                               ;
; 5.572 ; 5.792        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[1]                                                ;
; 5.572 ; 5.792        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[2]                                                ;
; 5.572 ; 5.792        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[3]                                                ;
; 5.572 ; 5.792        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[4]                                                ;
; 5.572 ; 5.792        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[5]                                                ;
; 5.572 ; 5.792        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[6]                                                ;
; 5.572 ; 5.792        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[7]                                                ;
; 5.572 ; 5.792        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[8]                                                ;
; 5.572 ; 5.792        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[9]                                                ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[10]                                            ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[13]                                            ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[15]                                            ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[2]                                             ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[5]                                             ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_reg                      ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_act                    ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_req                    ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_reg                      ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|sdram_rdy                     ;
; 5.574 ; 5.794        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[16]                                            ;
; 5.574 ; 5.794        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[17]                                            ;
; 5.574 ; 5.794        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[18]                                            ;
; 5.574 ; 5.794        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[19]                                            ;
; 5.574 ; 5.794        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[20]                                            ;
; 5.574 ; 5.794        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[21]                                            ;
; 5.574 ; 5.794        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[22]                                            ;
; 5.574 ; 5.794        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[23]                                            ;
; 5.574 ; 5.794        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[24]                                            ;
; 5.574 ; 5.794        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[25]                                            ;
; 5.574 ; 5.794        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[26]                                            ;
; 5.574 ; 5.794        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[27]                                            ;
; 5.574 ; 5.794        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[28]                                            ;
; 5.574 ; 5.794        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[29]                                            ;
; 5.574 ; 5.794        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[30]                                            ;
; 5.574 ; 5.794        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[31]                                            ;
; 5.574 ; 5.794        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ;
; 5.574 ; 5.794        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ;
; 5.574 ; 5.794        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ;
; 5.574 ; 5.794        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ;
; 5.662 ; 5.820        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[0]                   ;
; 5.662 ; 5.820        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[1]                   ;
; 5.662 ; 5.820        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[2]                   ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                              ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                         ; Clock Edge ; Target                                                                                          ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------------------------+
; 8.513 ; 8.733        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[0]   ;
; 8.513 ; 8.733        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[124] ;
; 8.513 ; 8.733        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[125] ;
; 8.513 ; 8.733        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[126] ;
; 8.513 ; 8.733        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[127] ;
; 8.513 ; 8.733        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[1]   ;
; 8.513 ; 8.733        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[2]   ;
; 8.513 ; 8.733        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[3]   ;
; 8.513 ; 8.733        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[4]   ;
; 8.513 ; 8.733        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[0]                 ;
; 8.513 ; 8.733        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[10]                ;
; 8.513 ; 8.733        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[1]                 ;
; 8.513 ; 8.733        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[2]                 ;
; 8.513 ; 8.733        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[3]                 ;
; 8.513 ; 8.733        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[4]                 ;
; 8.513 ; 8.733        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[5]                 ;
; 8.513 ; 8.733        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[6]                 ;
; 8.513 ; 8.733        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[7]                 ;
; 8.513 ; 8.733        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[8]                 ;
; 8.513 ; 8.733        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[9]                 ;
; 8.513 ; 8.733        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_hsync_reg                         ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; half_scandouble_enable_reg                                                                      ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|buffer_select_reg                     ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                         ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                         ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                         ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]                         ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                         ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                         ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                         ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                         ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[100] ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[101] ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[102] ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[103] ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[104] ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[105] ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[106] ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[107] ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[108] ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[109] ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[10]  ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[110] ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[111] ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[112] ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[113] ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[114] ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[115] ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[116] ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[117] ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[118] ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[119] ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[11]  ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[120] ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[121] ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[122] ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[123] ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[12]  ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[13]  ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[14]  ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[15]  ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[16]  ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[17]  ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[18]  ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[19]  ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[20]  ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[21]  ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[22]  ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[23]  ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[24]  ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[25]  ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[26]  ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[27]  ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[28]  ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[29]  ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[30]  ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[31]  ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[32]  ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[33]  ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[34]  ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[35]  ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[36]  ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[37]  ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[38]  ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[39]  ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[40]  ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[41]  ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[42]  ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[43]  ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[44]  ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[45]  ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[46]  ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[47]  ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[48]  ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[49]  ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[50]  ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[51]  ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[52]  ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[53]  ;
; 8.514 ; 8.734        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[54]  ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                        ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                               ; Clock Edge ; Target                                                                                                                                                                                                                   ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 10.104 ; 10.324       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]                                           ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[0]                    ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[10]                   ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[11]                   ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[12]                   ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[15]                   ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[1]                    ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]                    ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[3]                    ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[4]                    ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[5]                    ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[8]                    ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[9]                    ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[0]                          ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[10]                         ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[13]                         ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[14]                         ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[15]                         ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[1]                          ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[2]                          ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[7]                          ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[7]                                 ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[0]~_Duplicate_1   ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[1]~_Duplicate_1   ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxCtrlOut                   ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer1[0]                  ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer1[1]                  ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer1[2]                  ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer1[3]                  ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer3[0]                  ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer3[1]                  ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer3[2]                  ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer3[3]                  ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutIndex[0]           ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutIndex[1]           ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutStMachCurrState.10 ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|decBufferCnt                ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|fullSpeedRate_reg           ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|fullSpeedTick               ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[0]                        ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[1]                        ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[2]                        ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[3]                        ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[4]                        ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|lowSpeedTick                ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqExtend[0]                            ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqExtend[1]                            ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqExtend[2]                            ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq                                        ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1                                   ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|ACKRxed                                                       ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01010                                        ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01011                                        ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|NAKRxed                                                       ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[2]                                                     ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[3]                                                     ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[4]                                                     ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[5]                                                     ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[6]                                                     ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[7]                                                     ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXOverflow                                                    ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[0]                                                      ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[1]                                                      ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[2]                                                      ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[3]                                                      ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|stallRxed                                                     ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000001                           ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000011                           ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001001                           ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010111                           ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|clearTXReq                                          ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|delCnt[0]                                           ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|delCnt[1]                                           ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|delCnt[2]                                           ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|delCnt[3]                                           ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00010                                      ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00011                                      ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00101                                      ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01000                                      ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01001                                      ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01011                                      ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01101                                      ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01110                                      ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01111                                      ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10000                                      ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10010                                      ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10011                                      ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10101                                      ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10110                                      ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl[0]                                             ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl[1]                                             ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl[2]                                             ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRC16En                         ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRC5En                          ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRC5_8Bit                       ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[7]                      ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000001          ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000010          ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000011          ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000100          ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                  ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                         ; Clock Edge ; Target                                                                                                                                                                                             ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 17.191 ; 17.592       ; 0.401          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[0]                                          ;
; 17.191 ; 17.592       ; 0.401          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[1]                                          ;
; 17.191 ; 17.592       ; 0.401          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[2]                                          ;
; 17.191 ; 17.592       ; 0.401          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[3]                                          ;
; 17.191 ; 17.592       ; 0.401          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[4]                                          ;
; 17.191 ; 17.592       ; 0.401          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[10]                                               ;
; 17.191 ; 17.592       ; 0.401          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[11]                                               ;
; 17.191 ; 17.592       ; 0.401          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[12]                                               ;
; 17.191 ; 17.592       ; 0.401          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[13]                                               ;
; 17.191 ; 17.592       ; 0.401          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[14]                                               ;
; 17.191 ; 17.592       ; 0.401          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[15]                                               ;
; 17.191 ; 17.592       ; 0.401          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[16]                                               ;
; 17.191 ; 17.592       ; 0.401          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[17]                                               ;
; 17.191 ; 17.592       ; 0.401          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[18]                                               ;
; 17.191 ; 17.592       ; 0.401          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[19]                                               ;
; 17.191 ; 17.592       ; 0.401          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[20]                                               ;
; 17.191 ; 17.592       ; 0.401          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[5]                                                ;
; 17.191 ; 17.592       ; 0.401          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[6]                                                ;
; 17.191 ; 17.592       ; 0.401          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[7]                                                ;
; 17.191 ; 17.592       ; 0.401          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[8]                                                ;
; 17.191 ; 17.592       ; 0.401          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[9]                                                ;
; 17.228 ; 17.629       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[0]                                          ;
; 17.228 ; 17.629       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[1]                                          ;
; 17.228 ; 17.629       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[2]                                          ;
; 17.228 ; 17.629       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[3]                                          ;
; 17.228 ; 17.629       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[4]                                          ;
; 17.228 ; 17.629       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[10]                                               ;
; 17.228 ; 17.629       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[11]                                               ;
; 17.228 ; 17.629       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[12]                                               ;
; 17.228 ; 17.629       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[13]                                               ;
; 17.228 ; 17.629       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[14]                                               ;
; 17.228 ; 17.629       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[15]                                               ;
; 17.228 ; 17.629       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[16]                                               ;
; 17.228 ; 17.629       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[17]                                               ;
; 17.228 ; 17.629       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[18]                                               ;
; 17.228 ; 17.629       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[19]                                               ;
; 17.228 ; 17.629       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[20]                                               ;
; 17.228 ; 17.629       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[5]                                                ;
; 17.228 ; 17.629       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[6]                                                ;
; 17.228 ; 17.629       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[7]                                                ;
; 17.228 ; 17.629       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[8]                                                ;
; 17.228 ; 17.629       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[9]                                                ;
; 17.292 ; 17.512       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                  ;
; 17.292 ; 17.512       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                  ;
; 17.292 ; 17.512       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                  ;
; 17.292 ; 17.512       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                  ;
; 17.292 ; 17.512       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                  ;
; 17.292 ; 17.512       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                  ;
; 17.292 ; 17.512       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                  ;
; 17.293 ; 17.513       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqSTB[2]         ;
; 17.294 ; 17.514       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[5]       ;
; 17.294 ; 17.514       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[6]       ;
; 17.294 ; 17.514       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[2]  ;
; 17.294 ; 17.514       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[4]  ;
; 17.294 ; 17.514       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[5]  ;
; 17.294 ; 17.514       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[6]  ;
; 17.296 ; 17.516       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInSTB[2]         ;
; 17.296 ; 17.516       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInSTB[2]         ;
; 17.299 ; 17.519       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[0]             ;
; 17.299 ; 17.519       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[1]             ;
; 17.299 ; 17.519       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[2]             ;
; 17.299 ; 17.519       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[3]             ;
; 17.299 ; 17.519       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[0]        ;
; 17.299 ; 17.519       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[1]        ;
; 17.299 ; 17.519       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[2]        ;
; 17.299 ; 17.519       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[3]        ;
; 17.299 ; 17.519       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[0]       ;
; 17.299 ; 17.519       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[2]       ;
; 17.299 ; 17.519       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[3]       ;
; 17.299 ; 17.519       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[3]  ;
; 17.299 ; 17.519       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB[0]      ;
; 17.299 ; 17.519       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB[1]      ;
; 17.299 ; 17.519       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[0] ;
; 17.299 ; 17.519       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[1] ;
; 17.300 ; 17.520       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[7]       ;
; 17.300 ; 17.520       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[0]  ;
; 17.300 ; 17.520       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[1]  ;
; 17.300 ; 17.520       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[7]  ;
; 17.300 ; 17.520       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInSTB[2]           ;
; 17.300 ; 17.520       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[15]           ;
; 17.300 ; 17.520       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[7]          ;
; 17.300 ; 17.520       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[5]                                                                                                                                                  ;
; 17.310 ; 17.530       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[9]          ;
; 17.310 ; 17.530       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[3]     ;
; 17.310 ; 17.530       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[9]     ;
; 17.311 ; 17.531       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[11]           ;
; 17.311 ; 17.531       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[13]           ;
; 17.311 ; 17.531       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[11]      ;
; 17.311 ; 17.531       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[13]      ;
; 17.311 ; 17.531       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[0]          ;
; 17.311 ; 17.531       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[10]         ;
; 17.311 ; 17.531       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[2]          ;
; 17.311 ; 17.531       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[5]          ;
; 17.311 ; 17.531       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[8]          ;
; 17.311 ; 17.531       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[0]     ;
; 17.311 ; 17.531       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[10]    ;
; 17.311 ; 17.531       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[1]     ;
; 17.311 ; 17.531       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[2]     ;
; 17.311 ; 17.531       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[4]     ;
; 17.311 ; 17.531       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[5]     ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                  ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                        ; Clock Edge ; Target                                                                                             ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------+
; 17.584 ; 17.584       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.584 ; 17.584       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.584 ; 17.584       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.584 ; 17.584       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]                      ;
; 17.584 ; 17.584       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 17.589 ; 17.589       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.589 ; 17.589       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.596 ; 17.596       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.645 ; 17.645       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.652 ; 17.652       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.652 ; 17.652       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.657 ; 17.657       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.657 ; 17.657       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.657 ; 17.657       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.657 ; 17.657       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]                      ;
; 17.657 ; 17.657       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'FPGA_CLK'                                                                                                                       ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------+
; Slack   ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                                                 ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------+
; 99.858  ; 99.858       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                    ;
; 99.858  ; 99.858       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|observablevcoout                          ;
; 99.862  ; 99.862       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 99.862  ; 99.862       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 99.888  ; 99.888       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                       ;
; 99.925  ; 99.925       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|inclk[0]                                  ;
; 99.929  ; 99.929       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 100.000 ; 100.000      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                       ;
; 100.000 ; 100.000      ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                       ;
; 100.070 ; 100.070      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 100.073 ; 100.073      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|inclk[0]                                  ;
; 100.112 ; 100.112      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                       ;
; 100.137 ; 100.137      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 100.137 ; 100.137      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 100.140 ; 100.140      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                    ;
; 100.140 ; 100.140      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|observablevcoout                          ;
; 196.000 ; 200.000      ; 4.000          ; Port Rate        ; FPGA_CLK ; Rise       ; FPGA_CLK                                                                               ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                             ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 3.046 ; 3.153 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.025 ; 3.132 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.025 ; 3.132 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.025 ; 3.132 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.036 ; 3.143 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.040 ; 3.147 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.038 ; 3.145 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.034 ; 3.141 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.046 ; 3.153 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.032 ; 3.139 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.036 ; 3.143 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.036 ; 3.143 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.036 ; 3.143 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.026 ; 3.133 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 3.024 ; 3.131 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 3.014 ; 3.121 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 3.024 ; 3.131 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; 8.007 ; 8.404 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; 4.300 ; 4.502 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; 4.421 ; 4.705 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; 5.608 ; 5.757 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; 5.665 ; 5.827 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; 8.007 ; 8.404 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; 7.242 ; 7.710 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; 4.272 ; 4.508 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; 4.037 ; 4.257 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; 5.797 ; 5.884 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; 5.341 ; 5.500 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; 7.242 ; 7.710 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; 6.709 ; 7.028 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; 6.466 ; 6.712 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; 3.650 ; 3.852 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 0.864 ; 0.974 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ;
; USB2_P        ; FPGA_CLK   ; 0.864 ; 0.974 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; -2.018 ; -2.125 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; -2.030 ; -2.137 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; -2.030 ; -2.137 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; -2.030 ; -2.137 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; -2.040 ; -2.147 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; -2.045 ; -2.152 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; -2.042 ; -2.149 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; -2.039 ; -2.146 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; -2.050 ; -2.157 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; -2.036 ; -2.143 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; -2.040 ; -2.147 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; -2.040 ; -2.147 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; -2.040 ; -2.147 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; -2.030 ; -2.137 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; -2.028 ; -2.135 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; -2.018 ; -2.125 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; -2.028 ; -2.135 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; -3.197 ; -3.377 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; -3.197 ; -3.377 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; -3.312 ; -3.573 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; -4.324 ; -4.406 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; -4.379 ; -4.471 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; -4.366 ; -4.387 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; -2.962 ; -3.166 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; -3.183 ; -3.405 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; -2.962 ; -3.166 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; -4.570 ; -4.650 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; -4.215 ; -4.359 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; -3.501 ; -3.712 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; -5.519 ; -5.816 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; -5.293 ; -5.516 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; -2.589 ; -2.776 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; -0.151 ; -0.261 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ;
; USB2_P        ; FPGA_CLK   ; -0.151 ; -0.261 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                     ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 4.389 ; 3.932 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 3.289 ; 3.000 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 3.279 ; 2.990 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 3.279 ; 2.990 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 3.279 ; 2.990 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 3.284 ; 2.995 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 3.293 ; 3.004 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 3.302 ; 3.013 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 4.389 ; 3.932 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 3.303 ; 3.014 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 3.313 ; 3.024 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 3.289 ; 3.000 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 4.376 ; 3.919 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 3.290 ; 3.001 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 4.376 ; 3.919 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 4.388 ; 3.931 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 3.300 ; 3.011 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 4.450 ; 3.995 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 3.574 ; 3.263 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 3.574 ; 3.263 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 3.574 ; 3.263 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 4.430 ; 3.975 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 4.425 ; 3.970 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 2.356 ; 2.151 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 3.477 ; 3.180 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 3.486 ; 3.189 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 3.608 ; 3.297 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 4.450 ; 3.995 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 3.604 ; 3.293 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 3.604 ; 3.293 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 3.594 ; 3.283 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 4.442 ; 3.987 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 3.586 ; 3.275 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 3.596 ; 3.285 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 3.218 ; 3.465 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 3.109 ; 3.273 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 3.218 ; 3.465 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 3.300 ; 3.011 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 3.311 ; 3.022 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 6.862 ; 7.127 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 3.995 ; 3.910 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 3.611 ; 3.437 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 5.888 ; 6.101 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 2.983 ; 3.178 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 8.792 ;       ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 8.552 ; Fall       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]        ; FPGA_CLK   ; 5.179 ; 5.520 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]       ; FPGA_CLK   ; 2.605 ; 2.568 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]       ; FPGA_CLK   ; 5.179 ; 5.520 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]       ; FPGA_CLK   ; 2.375 ; 2.318 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]       ; FPGA_CLK   ; 5.157 ; 5.498 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]        ; FPGA_CLK   ; 5.068 ; 5.354 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]       ; FPGA_CLK   ; 5.068 ; 5.354 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]       ; FPGA_CLK   ; 2.307 ; 2.183 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]       ; FPGA_CLK   ; 2.317 ; 2.193 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]       ; FPGA_CLK   ; 2.307 ; 2.183 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_HS          ; FPGA_CLK   ; 5.057 ; 5.343 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_R[*]        ; FPGA_CLK   ; 2.297 ; 2.173 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[0]       ; FPGA_CLK   ; 2.286 ; 2.162 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[1]       ; FPGA_CLK   ; 2.296 ; 2.172 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[2]       ; FPGA_CLK   ; 2.297 ; 2.173 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[3]       ; FPGA_CLK   ; 2.287 ; 2.163 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_VS          ; FPGA_CLK   ; 2.296 ; 2.172 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; USB2_N          ; FPGA_CLK   ; 4.032 ; 3.908 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ;
; USB2_P          ; FPGA_CLK   ; 4.032 ; 3.908 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                             ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 2.417 ; 2.133 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 2.427 ; 2.143 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 2.417 ; 2.133 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 2.417 ; 2.133 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 2.417 ; 2.133 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 2.422 ; 2.138 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 2.431 ; 2.147 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 2.440 ; 2.156 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 3.573 ; 3.117 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 2.441 ; 2.157 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 2.451 ; 2.167 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 2.427 ; 2.143 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 2.429 ; 2.145 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 2.429 ; 2.145 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 3.560 ; 3.104 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 3.572 ; 3.116 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 2.439 ; 2.155 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 1.542 ; 1.338 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 2.712 ; 2.407 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 2.712 ; 2.407 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 2.712 ; 2.407 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 3.616 ; 3.162 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 3.612 ; 3.158 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 1.542 ; 1.338 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 2.615 ; 2.324 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 2.623 ; 2.332 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 2.745 ; 2.440 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 3.636 ; 3.182 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 2.741 ; 2.436 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 2.741 ; 2.436 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 2.731 ; 2.426 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 3.628 ; 3.174 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 2.723 ; 2.418 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 2.733 ; 2.428 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 2.255 ; 2.419 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 2.255 ; 2.419 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 2.359 ; 2.603 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 2.439 ; 2.155 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 2.449 ; 2.165 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 5.985 ; 6.253 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 3.130 ; 3.048 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 2.748 ; 2.576 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 5.044 ; 5.261 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 2.142 ; 2.333 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 8.022 ;       ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 7.786 ; Fall       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]        ; FPGA_CLK   ; 1.561 ; 1.505 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]       ; FPGA_CLK   ; 1.790 ; 1.754 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]       ; FPGA_CLK   ; 4.364 ; 4.706 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]       ; FPGA_CLK   ; 1.561 ; 1.505 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]       ; FPGA_CLK   ; 4.343 ; 4.685 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]        ; FPGA_CLK   ; 1.490 ; 1.367 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]       ; FPGA_CLK   ; 4.251 ; 4.538 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]       ; FPGA_CLK   ; 1.490 ; 1.367 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]       ; FPGA_CLK   ; 1.500 ; 1.377 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]       ; FPGA_CLK   ; 1.490 ; 1.367 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_HS          ; FPGA_CLK   ; 4.240 ; 4.527 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_R[*]        ; FPGA_CLK   ; 1.469 ; 1.346 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[0]       ; FPGA_CLK   ; 1.469 ; 1.346 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[1]       ; FPGA_CLK   ; 1.479 ; 1.356 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[2]       ; FPGA_CLK   ; 1.480 ; 1.357 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[3]       ; FPGA_CLK   ; 1.470 ; 1.347 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_VS          ; FPGA_CLK   ; 1.479 ; 1.356 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; USB2_N          ; FPGA_CLK   ; 3.501 ; 3.378 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ;
; USB2_P          ; FPGA_CLK   ; 3.501 ; 3.378 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.800 ; 2.800 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.606 ; 3.606 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.606 ; 3.606 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.606 ; 3.606 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.697 ; 3.697 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 4.098 ; 4.098 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 4.082 ; 4.082 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.666 ; 3.666 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.698 ; 3.698 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.954 ; 3.954 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.596 ; 3.596 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.214 ; 3.214 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.214 ; 3.214 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.204 ; 3.204 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.810 ; 2.810 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.800 ; 2.800 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.810 ; 2.810 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.400 ; 3.016 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 5.450 ; 5.066 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ;
; USB2_P        ; FPGA_CLK   ; 5.450 ; 5.066 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                             ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.465 ; 1.494 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.238 ; 2.267 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.238 ; 2.267 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.238 ; 2.267 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.326 ; 2.355 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.711 ; 2.740 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.696 ; 2.725 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.297 ; 2.326 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.327 ; 2.356 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.574 ; 2.603 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.230 ; 2.259 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.863 ; 1.892 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.863 ; 1.892 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.853 ; 1.882 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 1.475 ; 1.504 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.465 ; 1.494 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.475 ; 1.504 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.448 ; 2.080 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 4.772 ; 4.404 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ;
; USB2_P        ; FPGA_CLK   ; 4.772 ; 4.404 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                            ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.520     ; 2.760     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.270     ; 3.510     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.270     ; 3.510     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.270     ; 3.510     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.399     ; 3.639     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.774     ; 4.014     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.774     ; 4.014     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.374     ; 3.614     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.416     ; 3.656     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.574     ; 3.814     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.257     ; 3.497     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.889     ; 3.129     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.889     ; 3.129     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.879     ; 3.119     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.530     ; 2.770     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.520     ; 2.760     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.530     ; 2.770     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.938     ; 3.322     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 4.952     ; 5.336     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ;
; USB2_P        ; FPGA_CLK   ; 4.952     ; 5.336     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                                    ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.426     ; 1.426     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.147     ; 2.147     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.147     ; 2.147     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.147     ; 2.147     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.271     ; 2.271     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.631     ; 2.631     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.631     ; 2.631     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.247     ; 2.247     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.288     ; 2.288     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.439     ; 2.439     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.135     ; 2.135     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.782     ; 1.782     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.782     ; 1.782     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.772     ; 1.772     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 1.436     ; 1.436     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.426     ; 1.426     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.436     ; 1.436     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.006     ; 2.374     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 4.295     ; 4.663     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ;
; USB2_P        ; FPGA_CLK   ; 4.295     ; 4.663     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+


----------------------------------------------
; Slow 1200mV 85C Model Metastability Report ;
----------------------------------------------
No synchronizer chains to report.


+---------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Fmax Summary                                                                                   ;
+------------+-----------------+-------------------------------------------------------------------------------+------+
; Fmax       ; Restricted Fmax ; Clock Name                                                                    ; Note ;
+------------+-----------------+-------------------------------------------------------------------------------+------+
; 36.97 MHz  ; 36.97 MHz       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;      ;
; 113.7 MHz  ; 113.7 MHz       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ;      ;
; 132.64 MHz ; 132.64 MHz      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;      ;
; 143.14 MHz ; 143.14 MHz      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;      ;
+------------+-----------------+-------------------------------------------------------------------------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+--------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup Summary                                                                     ;
+-------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                         ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; -3.449 ; -123.744      ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; -0.554 ; -12.827       ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1.007  ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 10.082 ; 0.000         ;
+-------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold Summary                                                                      ;
+-------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                         ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------+--------+---------------+
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; -1.488 ; -55.680       ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.372  ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.402  ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.403  ; 0.000         ;
+-------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery Summary                                                                  ;
+-------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                         ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 6.696  ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.124  ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 11.795 ; 0.000         ;
+-------------------------------------------------------------------------------+--------+---------------+


+-------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal Summary                                                                  ;
+-------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                         ; Slack ; End Point TNS ;
+-------------------------------------------------------------------------------+-------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 2.337 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 3.704 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 4.061 ; 0.000         ;
+-------------------------------------------------------------------------------+-------+---------------+


+--------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width Summary                                                       ;
+-------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                         ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.571  ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 8.510  ; 0.000         ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; 10.068 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.223 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]  ; 17.587 ; 0.000         ;
; FPGA_CLK                                                                      ; 99.831 ; 0.000         ;
+-------------------------------------------------------------------------------+--------+---------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                          ; To Node                                                                                                                                                                                            ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; -3.449 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[8]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[8]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.249     ; 1.173      ;
; -3.342 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[10]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[10]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.249     ; 1.066      ;
; -3.338 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[12]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[12]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.249     ; 1.062      ;
; -3.336 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[14]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[14]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.249     ; 1.060      ;
; -3.303 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[9]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.249     ; 1.027      ;
; -3.301 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[15]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[15]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.249     ; 1.025      ;
; -2.901 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[11]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[11]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.801     ; 1.073      ;
; -2.901 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[13]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.801     ; 1.073      ;
; -2.896 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[10]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[10]    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.802     ; 1.067      ;
; -2.886 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.869     ; 0.990      ;
; -2.885 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.869     ; 0.989      ;
; -2.855 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[0]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[0]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.812     ; 1.016      ;
; -2.831 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[2]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[2]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.812     ; 0.992      ;
; -2.823 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[1]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[1]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.812     ; 0.984      ;
; -2.821 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[3]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[3]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.812     ; 0.982      ;
; -2.817 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[7]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[7]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.802     ; 0.988      ;
; -2.714 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.869     ; 0.818      ;
; -2.714 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.869     ; 0.818      ;
; -2.714 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.869     ; 0.818      ;
; -2.714 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.869     ; 0.818      ;
; -2.713 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.869     ; 0.817      ;
; -2.701 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|bitStuffError                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[1]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.854     ; 0.820      ;
; -2.700 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[1] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.853     ; 0.820      ;
; -2.700 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXTimeOut                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[3]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.854     ; 0.819      ;
; -2.698 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CRCError                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[0]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.854     ; 0.817      ;
; -2.698 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[0] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.853     ; 0.818      ;
; -2.697 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|stallRxed                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[5]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.851     ; 0.819      ;
; -2.697 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXOverflow                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[2]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.851     ; 0.819      ;
; -2.696 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|NAKRxed                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[4]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.851     ; 0.818      ;
; -2.680 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.856     ; 0.797      ;
; -2.678 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInExtend[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInSTB[2]           ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.853     ; 0.798      ;
; -2.678 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.856     ; 0.795      ;
; -2.677 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|dataSequence                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[7]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.854     ; 0.796      ;
; -2.676 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.851     ; 0.798      ;
; -2.674 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|ACKRxed                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[6]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.851     ; 0.796      ;
; -2.670 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[3]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[3]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.802     ; 0.841      ;
; -2.647 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[8]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[8]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.802     ; 0.818      ;
; -2.647 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[5]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[5]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.802     ; 0.818      ;
; -2.647 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[2]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[2]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.802     ; 0.818      ;
; -2.646 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[6]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[6]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.802     ; 0.817      ;
; -2.646 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[0]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[0]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.802     ; 0.817      ;
; -2.646 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[1]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[1]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.802     ; 0.817      ;
; -2.646 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[9]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[9]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.802     ; 0.817      ;
; -2.645 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[4]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[4]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.802     ; 0.816      ;
; 2.919  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[7]                                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.141     ; 8.690      ;
; 2.919  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[9]                                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.141     ; 8.690      ;
; 2.919  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[10]                                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.141     ; 8.690      ;
; 2.919  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[8]                                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.141     ; 8.690      ;
; 3.137  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[5]                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.153     ; 8.460      ;
; 3.192  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[3]                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.152     ; 8.406      ;
; 3.192  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[6]                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.152     ; 8.406      ;
; 3.199  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[0]                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 8.394      ;
; 3.199  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[1]                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 8.394      ;
; 3.199  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[2]                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 8.394      ;
; 3.199  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[3]                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 8.394      ;
; 3.199  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[4]                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 8.394      ;
; 3.199  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[5]                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 8.394      ;
; 3.199  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[6]                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 8.394      ;
; 3.199  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[7]                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 8.394      ;
; 3.206  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[4]                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.153     ; 8.391      ;
; 3.311  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer2|count_reg[0]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.145     ; 8.294      ;
; 3.311  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer2|count_reg[1]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.145     ; 8.294      ;
; 3.311  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer2|count_reg[2]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.145     ; 8.294      ;
; 3.311  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer2|count_reg[3]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.145     ; 8.294      ;
; 3.311  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer2|count_reg[4]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.145     ; 8.294      ;
; 3.311  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer2|count_reg[5]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.145     ; 8.294      ;
; 3.311  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer2|count_reg[6]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.145     ; 8.294      ;
; 3.311  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer2|count_reg[7]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.145     ; 8.294      ;
; 3.355  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.141     ; 8.254      ;
; 3.355  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[5]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 8.233      ;
; 3.355  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[4]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 8.233      ;
; 3.355  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[2]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 8.233      ;
; 3.355  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[3]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 8.233      ;
; 3.355  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[1]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 8.233      ;
; 3.355  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[0]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 8.233      ;
; 3.355  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[11]                                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.141     ; 8.254      ;
; 3.355  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.141     ; 8.254      ;
; 3.355  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.141     ; 8.254      ;
; 3.355  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[13]                                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.141     ; 8.254      ;
; 3.355  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[4]                                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.141     ; 8.254      ;
; 3.355  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.141     ; 8.254      ;
; 3.355  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]                                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.141     ; 8.254      ;
; 3.355  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]                                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.141     ; 8.254      ;
; 3.355  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[12]                                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.141     ; 8.254      ;
; 3.355  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.141     ; 8.254      ;
; 3.355  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.141     ; 8.254      ;
; 3.399  ; ram_do_reg[7]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.159     ; 8.192      ;
; 3.430  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[3]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 8.158      ;
; 3.430  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[6]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 8.158      ;
; 3.430  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[7]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 8.158      ;
; 3.430  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[4]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 8.158      ;
; 3.430  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[0]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 8.158      ;
; 3.430  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[1]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 8.158      ;
; 3.430  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[5]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 8.158      ;
; 3.430  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[2]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 8.158      ;
; 3.431  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[7]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 8.172      ;
; 3.431  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[6]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 8.172      ;
; 3.431  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[1]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 8.172      ;
; 3.431  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[0]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 8.172      ;
; 3.431  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[2]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 8.172      ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                        ; To Node                                                                                                                                                                                                          ; Launch Clock                                                                  ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -0.554 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.097      ; 1.552      ;
; -0.472 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.097      ; 1.470      ;
; -0.458 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.097      ; 1.456      ;
; -0.450 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate_reg1                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.090      ; 1.441      ;
; -0.442 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.092      ; 1.435      ;
; -0.419 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.100      ; 1.420      ;
; -0.385 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.097      ; 1.383      ;
; -0.379 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[0]                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.090      ; 1.370      ;
; -0.372 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.097      ; 1.370      ;
; -0.348 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.097      ; 1.346      ;
; -0.331 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg_reg1                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.090      ; 1.322      ;
; -0.328 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.091      ; 1.320      ;
; -0.327 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.092      ; 1.320      ;
; -0.324 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.101      ; 1.326      ;
; -0.323 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.097      ; 1.321      ;
; -0.321 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.101      ; 1.323      ;
; -0.321 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.091      ; 1.313      ;
; -0.320 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.101      ; 1.322      ;
; -0.319 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.115      ; 1.335      ;
; -0.319 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.101      ; 1.321      ;
; -0.319 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.101      ; 1.321      ;
; -0.318 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn_reg1                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.100      ; 1.319      ;
; -0.318 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.101      ; 1.320      ;
; -0.317 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.101      ; 1.319      ;
; -0.316 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.101      ; 1.318      ;
; -0.314 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.115      ; 1.330      ;
; -0.314 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.091      ; 1.306      ;
; -0.311 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.091      ; 1.303      ;
; -0.300 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.101      ; 1.302      ;
; -0.300 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.101      ; 1.302      ;
; -0.299 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.101      ; 1.301      ;
; -0.299 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.101      ; 1.301      ;
; -0.289 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.115      ; 1.305      ;
; -0.257 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.098      ; 1.256      ;
; -0.242 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.115      ; 1.258      ;
; -0.172 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.115      ; 1.188      ;
; -0.161 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.115      ; 1.177      ;
; -0.159 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.115      ; 1.175      ;
; -0.158 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.115      ; 1.174      ;
; -0.152 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.102      ; 1.155      ;
; 12.038 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.535     ; 8.262      ;
; 12.045 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.535     ; 8.255      ;
; 12.201 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.535     ; 8.099      ;
; 12.509 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[5]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.068     ; 8.258      ;
; 12.516 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[5]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.068     ; 8.251      ;
; 12.526 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.068     ; 8.241      ;
; 12.533 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.068     ; 8.234      ;
; 12.672 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[5]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.068     ; 8.095      ;
; 12.687 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[4]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.068     ; 8.080      ;
; 12.689 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.068     ; 8.078      ;
; 12.694 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[4]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.068     ; 8.073      ;
; 12.729 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.068     ; 8.038      ;
; 12.736 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.068     ; 8.031      ;
; 12.784 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[6]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.068     ; 7.983      ;
; 12.791 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[6]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.068     ; 7.976      ;
; 12.833 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.068     ; 7.934      ;
; 12.840 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.068     ; 7.927      ;
; 12.850 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[4]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.068     ; 7.917      ;
; 12.892 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.068     ; 7.875      ;
; 12.947 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[6]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.068     ; 7.820      ;
; 12.996 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.068     ; 7.771      ;
; 13.153 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.000     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.071     ; 7.611      ;
; 13.160 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.000     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.071     ; 7.604      ;
; 13.316 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.000     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.071     ; 7.448      ;
; 13.771 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.000 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.068     ; 6.996      ;
; 13.878 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[7]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.068     ; 6.889      ;
; 13.885 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[7]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.068     ; 6.882      ;
; 13.910 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.000 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.068     ; 6.857      ;
; 13.936 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.068     ; 6.831      ;
; 13.938 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.068     ; 6.829      ;
; 13.977 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.000 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.068     ; 6.790      ;
; 14.041 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[7]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.068     ; 6.726      ;
; 14.063 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.000 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.068     ; 6.704      ;
; 14.075 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.068     ; 6.692      ;
; 14.077 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.068     ; 6.690      ;
; 14.092 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.000 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.068     ; 6.675      ;
; 14.142 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.068     ; 6.625      ;
; 14.144 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.068     ; 6.623      ;
; 14.180 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFNearTime[15]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 6.577      ;
; 14.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFNearTime[15]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 6.570      ;
; 14.211 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.000 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.068     ; 6.556      ;
; 14.228 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.068     ; 6.539      ;
; 14.230 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.068     ; 6.537      ;
; 14.257 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.068     ; 6.510      ;
; 14.259 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.068     ; 6.508      ;
; 14.261 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.068     ; 6.506      ;
; 14.261 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.010 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.068     ; 6.506      ;
; 14.343 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFNearTime[15]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 6.414      ;
; 14.376 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.068     ; 6.391      ;
; 14.378 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.068     ; 6.389      ;
; 14.395 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.068     ; 6.372      ;
; 14.400 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.068     ; 6.367      ;
; 14.400 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.010 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.068     ; 6.367      ;
; 14.402 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.068     ; 6.365      ;
; 14.410 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[7] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.000 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.068     ; 6.357      ;
; 14.467 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.068     ; 6.300      ;
; 14.467 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.010 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.068     ; 6.300      ;
; 14.553 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.068     ; 6.214      ;
; 14.553 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.010 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.068     ; 6.214      ;
; 14.558 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.068     ; 6.209      ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                             ;
+-------+-------------------------+----------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node               ; To Node                                      ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------+----------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 1.007 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.127     ; 4.615      ;
; 1.159 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.127     ; 4.463      ;
; 1.293 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.129     ; 4.327      ;
; 1.323 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[0]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.141     ; 4.285      ;
; 1.323 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.141     ; 4.285      ;
; 1.323 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.141     ; 4.285      ;
; 1.323 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.141     ; 4.285      ;
; 1.342 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.129     ; 4.278      ;
; 1.342 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.129     ; 4.278      ;
; 1.445 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.129     ; 4.175      ;
; 1.453 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.141     ; 4.155      ;
; 1.468 ; SDRAM_ADDR[16]          ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.114     ; 4.167      ;
; 1.475 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[0]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.141     ; 4.133      ;
; 1.475 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.141     ; 4.133      ;
; 1.475 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.141     ; 4.133      ;
; 1.475 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.141     ; 4.133      ;
; 1.494 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.129     ; 4.126      ;
; 1.494 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.129     ; 4.126      ;
; 1.500 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_ras_n    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.139     ; 4.110      ;
; 1.605 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.141     ; 4.003      ;
; 1.652 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_ras_n    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.139     ; 3.958      ;
; 1.690 ; SDRAM_ADDR[17]          ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.116     ; 3.943      ;
; 1.725 ; SDRAM_ADDR[18]          ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.116     ; 3.908      ;
; 1.794 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.128     ; 3.827      ;
; 1.844 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[8]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.132     ; 3.899      ;
; 1.844 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[9]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.132     ; 3.899      ;
; 1.845 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[0]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.132     ; 3.898      ;
; 1.877 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[1]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.132     ; 3.866      ;
; 1.924 ; SDRAM_ADDR[22]          ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.141     ; 3.684      ;
; 1.978 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.128     ; 3.643      ;
; 1.993 ; SDRAM_ADDR[12]          ; sdram_ctrl:sdram_controller|r_sdram_addr[0]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.139     ; 3.617      ;
; 2.022 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_ba[0]    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.139     ; 3.588      ;
; 2.058 ; SDRAM_ADDR[20]          ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.115     ; 3.576      ;
; 2.090 ; SDRAM_ADDR[7]           ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.110     ; 3.549      ;
; 2.107 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[15]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.128     ; 3.640      ;
; 2.109 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[10]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.128     ; 3.638      ;
; 2.109 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[13]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.128     ; 3.638      ;
; 2.148 ; SDRAM_ADDR[5]           ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.108     ; 3.493      ;
; 2.164 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_ba[1]    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.141     ; 3.444      ;
; 2.171 ; SDRAM_ADDR[3]           ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.140     ; 3.438      ;
; 2.174 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_ba[0]    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.139     ; 3.436      ;
; 2.247 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.128     ; 3.374      ;
; 2.268 ; SDRAM_ADDR[19]          ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.116     ; 3.365      ;
; 2.272 ; SDRAM_READ_ENABLE       ; ram_do_reg[7]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.132     ; 3.471      ;
; 2.272 ; SDRAM_READ_ENABLE       ; ram_do_reg[15]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.132     ; 3.471      ;
; 2.281 ; SDRAM_READ_ENABLE       ; ram_do_reg[2]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.134     ; 3.460      ;
; 2.282 ; SDRAM_READ_ENABLE       ; ram_do_reg[3]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.134     ; 3.459      ;
; 2.282 ; SDRAM_READ_ENABLE       ; ram_do_reg[11]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.134     ; 3.459      ;
; 2.300 ; SDRAM_READ_ENABLE       ; ram_do_reg[6]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.133     ; 3.442      ;
; 2.316 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_ba[1]    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.141     ; 3.292      ;
; 2.399 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.128     ; 3.222      ;
; 2.417 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[5]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.128     ; 3.330      ;
; 2.418 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[2]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.128     ; 3.329      ;
; 2.471 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[7]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.129     ; 3.275      ;
; 2.500 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[6]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.129     ; 3.246      ;
; 2.504 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[4]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.129     ; 3.242      ;
; 2.504 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[14]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.129     ; 3.242      ;
; 2.528 ; SDRAM_ADDR[6]           ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.110     ; 3.111      ;
; 2.626 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[3]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.129     ; 3.120      ;
; 2.626 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[12]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.129     ; 3.120      ;
; 2.628 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[11]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.129     ; 3.118      ;
; 2.650 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[13]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.109     ; 3.116      ;
; 2.651 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[15]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.109     ; 3.115      ;
; 2.653 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[10]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.109     ; 3.113      ;
; 2.656 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[8]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.113     ; 3.106      ;
; 2.657 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[9]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.113     ; 3.105      ;
; 2.674 ; SDRAM_ADDR[8]           ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.128     ; 2.947      ;
; 2.685 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[1]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.113     ; 3.077      ;
; 2.699 ; SDRAM_ADDR[1]           ; sdram_ctrl:sdram_controller|r_sdram_addr[0]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.140     ; 2.910      ;
; 2.709 ; SDRAM_ADDR[21]          ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.128     ; 2.912      ;
; 2.727 ; SDRAM_ADDR[15]          ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.139     ; 2.883      ;
; 2.745 ; SDRAM_ADDR[14]          ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.139     ; 2.865      ;
; 2.756 ; SDRAM_ADDR[4]           ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.139     ; 2.854      ;
; 2.797 ; SDRAM_ADDR[9]           ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.127     ; 2.825      ;
; 2.801 ; SDRAM_ADDR[13]          ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.139     ; 2.809      ;
; 2.848 ; SDRAM_READ_ENABLE       ; ram_do_reg[29]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.139     ; 2.888      ;
; 2.848 ; SDRAM_READ_ENABLE       ; ram_do_reg[28]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.139     ; 2.888      ;
; 2.848 ; SDRAM_READ_ENABLE       ; ram_do_reg[21]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.139     ; 2.888      ;
; 2.848 ; SDRAM_READ_ENABLE       ; ram_do_reg[20]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.139     ; 2.888      ;
; 2.848 ; SDRAM_READ_ENABLE       ; ram_do_reg[18]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.139     ; 2.888      ;
; 2.848 ; SDRAM_READ_ENABLE       ; ram_do_reg[25]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.139     ; 2.888      ;
; 2.848 ; SDRAM_READ_ENABLE       ; ram_do_reg[19]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.139     ; 2.888      ;
; 2.848 ; SDRAM_READ_ENABLE       ; ram_do_reg[26]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.139     ; 2.888      ;
; 2.848 ; SDRAM_READ_ENABLE       ; ram_do_reg[16]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.139     ; 2.888      ;
; 2.848 ; SDRAM_READ_ENABLE       ; ram_do_reg[23]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.139     ; 2.888      ;
; 2.874 ; SDRAM_ADDR[10]          ; sdram_ctrl:sdram_controller|r_sdram_ba[0]    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.138     ; 2.737      ;
; 2.883 ; SDRAM_ADDR[2]           ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.139     ; 2.727      ;
; 2.919 ; SDRAM_READ_ENABLE       ; ram_do_reg[30]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.140     ; 2.816      ;
; 2.919 ; SDRAM_READ_ENABLE       ; ram_do_reg[22]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.140     ; 2.816      ;
; 2.919 ; SDRAM_READ_ENABLE       ; ram_do_reg[31]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.140     ; 2.816      ;
; 2.919 ; SDRAM_READ_ENABLE       ; ram_do_reg[27]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.140     ; 2.816      ;
; 2.919 ; SDRAM_READ_ENABLE       ; ram_do_reg[24]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.140     ; 2.816      ;
; 2.919 ; SDRAM_READ_ENABLE       ; ram_do_reg[17]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.140     ; 2.816      ;
; 2.927 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[7]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.110     ; 2.838      ;
; 2.977 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[5]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.109     ; 2.789      ;
; 2.978 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[2]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.109     ; 2.788      ;
; 2.993 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[6]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.110     ; 2.772      ;
; 2.997 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[4]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.110     ; 2.768      ;
; 2.998 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[14]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.110     ; 2.767      ;
; 3.001 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[0]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.113     ; 2.761      ;
+-------+-------------------------+----------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                                                                                                                                          ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                ; To Node                                                                 ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 10.082 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.091     ; 7.324      ;
; 10.183 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.091     ; 7.223      ;
; 10.376 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.091     ; 7.030      ;
; 10.552 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.091     ; 6.854      ;
; 10.615 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.091     ; 6.791      ;
; 10.640 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.090     ; 6.767      ;
; 10.700 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.091     ; 6.706      ;
; 10.708 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.090     ; 6.699      ;
; 10.720 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.090     ; 6.687      ;
; 10.769 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.090     ; 6.638      ;
; 10.774 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.091     ; 6.632      ;
; 10.799 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.091     ; 6.607      ;
; 10.818 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.090     ; 6.589      ;
; 10.855 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.090     ; 6.552      ;
; 10.855 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.091     ; 6.551      ;
; 10.872 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.090     ; 6.535      ;
; 10.904 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.091     ; 6.502      ;
; 10.975 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.143     ; 6.379      ;
; 10.991 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.122     ; 6.384      ;
; 10.995 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.143     ; 6.359      ;
; 11.018 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.090     ; 6.389      ;
; 11.028 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.090     ; 6.379      ;
; 11.087 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.090     ; 6.320      ;
; 11.134 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.091     ; 6.272      ;
; 11.137 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.143     ; 6.217      ;
; 11.139 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.090     ; 6.268      ;
; 11.145 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.090     ; 6.262      ;
; 11.163 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.090     ; 6.244      ;
; 11.189 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.122     ; 6.186      ;
; 11.193 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.143     ; 6.161      ;
; 11.205 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.090     ; 6.202      ;
; 11.242 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.122     ; 6.133      ;
; 11.289 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.143     ; 6.065      ;
; 11.317 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.122     ; 6.058      ;
; 11.336 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.090     ; 6.071      ;
; 11.357 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.090     ; 6.050      ;
; 11.386 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.090     ; 6.021      ;
; 11.400 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.122     ; 5.975      ;
; 11.434 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.143     ; 5.920      ;
; 11.473 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.143     ; 5.881      ;
; 11.495 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.122     ; 5.880      ;
; 11.523 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.122     ; 5.852      ;
; 11.532 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.090     ; 5.875      ;
; 11.569 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.090     ; 5.838      ;
; 11.586 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.090     ; 5.821      ;
; 11.626 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.090     ; 5.781      ;
; 11.641 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.090     ; 5.766      ;
; 11.645 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.090     ; 5.762      ;
; 11.655 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.091     ; 5.751      ;
; 11.655 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.090     ; 5.752      ;
; 11.680 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.090     ; 5.727      ;
; 11.710 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.141     ; 5.646      ;
; 11.738 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.090     ; 5.669      ;
; 11.754 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.090     ; 5.653      ;
; 11.823 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.090     ; 5.584      ;
; 11.830 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.090     ; 5.577      ;
; 11.880 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.090     ; 5.527      ;
; 11.896 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.090     ; 5.511      ;
; 11.905 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.122     ; 5.470      ;
; 11.920 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.143     ; 5.434      ;
; 11.940 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.090     ; 5.467      ;
; 11.986 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.143     ; 5.368      ;
; 12.008 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.396     ; 5.219      ;
; 12.041 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.122     ; 5.334      ;
; 12.048 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.090     ; 5.359      ;
; 12.057 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.411     ; 5.155      ;
; 12.139 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.394     ; 5.090      ;
; 12.160 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.122     ; 5.215      ;
; 12.197 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.122     ; 5.178      ;
; 12.208 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.396     ; 5.019      ;
; 12.261 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.090     ; 5.146      ;
; 12.264 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.394     ; 4.965      ;
; 12.265 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.411     ; 4.947      ;
; 12.270 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.411     ; 4.942      ;
; 12.302 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.122     ; 5.073      ;
; 12.338 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.396     ; 4.889      ;
; 12.410 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.396     ; 4.817      ;
; 12.414 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.411     ; 4.798      ;
; 12.468 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.396     ; 4.759      ;
; 12.479 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.090     ; 4.928      ;
; 12.483 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.394     ; 4.746      ;
; 12.544 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.090     ; 4.863      ;
; 12.600 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.411     ; 4.612      ;
; 12.634 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.088     ; 4.775      ;
; 12.719 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.090     ; 4.688      ;
; 12.740 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.411     ; 4.472      ;
; 12.769 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.089     ; 4.639      ;
; 12.779 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.411     ; 4.433      ;
; 12.816 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.143     ; 4.538      ;
; 12.903 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.413     ; 4.307      ;
; 12.906 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.088     ; 4.503      ;
; 12.913 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.090     ; 4.494      ;
; 12.998 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.088     ; 4.411      ;
; 13.067 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.090     ; 4.340      ;
; 13.125 ; sdram_reset_n_reg                                                                                                                                                        ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|hsync_in_reg  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.151     ; 4.347      ;
; 13.140 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.088     ; 4.269      ;
; 13.141 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.143     ; 4.213      ;
; 13.267 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.143     ; 4.087      ;
; 13.360 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.091     ; 4.046      ;
; 13.385 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.088     ; 4.024      ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                          ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                       ; To Node                                                                                                                                                                                                         ; Launch Clock                                                                  ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -1.488 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.271      ; 1.086      ;
; -1.483 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]                                                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.260      ; 1.080      ;
; -1.477 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.255      ; 1.081      ;
; -1.451 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.272      ; 1.124      ;
; -1.449 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.272      ; 1.126      ;
; -1.448 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.271      ; 1.126      ;
; -1.448 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.272      ; 1.127      ;
; -1.447 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.271      ; 1.127      ;
; -1.430 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.272      ; 1.145      ;
; -1.429 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.260      ; 1.134      ;
; -1.424 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.259      ; 1.138      ;
; -1.422 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.259      ; 1.140      ;
; -1.421 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.271      ; 1.153      ;
; -1.421 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.255      ; 1.137      ;
; -1.420 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.259      ; 1.142      ;
; -1.420 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.260      ; 1.143      ;
; -1.417 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.260      ; 1.146      ;
; -1.415 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.248      ; 1.136      ;
; -1.413 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.260      ; 1.150      ;
; -1.410 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg_reg1                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.249      ; 1.142      ;
; -1.408 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.255      ; 1.150      ;
; -1.405 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.250      ; 1.148      ;
; -1.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.260      ; 1.160      ;
; -1.399 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.260      ; 1.164      ;
; -1.398 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.260      ; 1.165      ;
; -1.396 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.260      ; 1.167      ;
; -1.385 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.249      ; 1.167      ;
; -1.382 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn_reg1               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.259      ; 1.180      ;
; -1.381 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.249      ; 1.171      ;
; -1.376 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.260      ; 1.187      ;
; -1.374 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[0]                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.247      ; 1.176      ;
; -1.371 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.255      ; 1.187      ;
; -1.370 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.249      ; 1.182      ;
; -1.353 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.255      ; 1.205      ;
; -1.306 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.259      ; 1.256      ;
; -1.303 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.249      ; 1.249      ;
; -1.256 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate_reg1                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.247      ; 1.294      ;
; -1.247 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.255      ; 1.311      ;
; -1.243 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.255      ; 1.315      ;
; -1.191 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.255      ; 1.367      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|SIETxGnt           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|SIETxGnt           ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.10    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.10    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.11    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.11    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.00    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.00    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.01    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.01    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1]              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1]              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[3]              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[3]              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[2]              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[2]              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxBitRdy            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxBitRdy            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferInIndex[0]     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferInIndex[0]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferInIndex[1]     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferInIndex[1]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[0]    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[0]    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[1]    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[1]    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActive         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActive         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1100     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1100     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[0]          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[0]          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[1]          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[1]          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[2]          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[2]          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[3]          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[3]          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxByteWEn           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxByteWEn           ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[1]                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[1]                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1101  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1101  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1101 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0000 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0000 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketCPReady        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketCPReady        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000100                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000100                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010101                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010101                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011100                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011100                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|getPacketREn                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|getPacketREn                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01101                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01101                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00010                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00100                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00100                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00111                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00111                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001101                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001101                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011010                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011010                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001011                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001011                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|bitStuffError                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|bitStuffError                                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXTimeOut                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXTimeOut                                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CRCError                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CRCError                                             ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[0]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[0]                                             ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[2]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[2]                                             ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[3]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[3]                                             ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[4]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[4]                                             ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[5]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[5]                                             ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[6]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[6]                                             ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.110                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.110                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFTimerClr                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFTimerClr                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.011                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.011                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.100                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.100                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.101                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.101                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFSent                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFSent                                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0100 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00001                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00001                             ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|sendPacketRdy                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|sendPacketRdy                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1001 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1001 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortReq                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortReq                                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.110                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.110                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.111                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.111                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                                                                                                                                                                        ;
+-------+--------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                        ; To Node                                                                                                                                                                       ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 0.372 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_datain_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.513      ; 1.135      ;
; 0.402 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|buffer_select_reg                      ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|buffer_select_reg                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_hsync_reg                          ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_hsync_reg                                                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.669      ;
; 0.417 ; half_scandouble_enable_reg                                                                       ; half_scandouble_enable_reg                                                                                                                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.684      ;
; 0.448 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[0]    ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_hsync_reg                                                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.715      ;
; 0.469 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[85]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[84]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.735      ;
; 0.469 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[10]                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[10]                                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.736      ;
; 0.470 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[68]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[67]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.736      ;
; 0.470 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[63]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[62]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.736      ;
; 0.470 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[125]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[124]                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.737      ;
; 0.470 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[2]    ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[1]                                                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.737      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[121]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[120]                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[120]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[119]                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[119]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[118]                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[118]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[117]                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[115]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[114]                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[114]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[113]                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[113]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[112]                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[111]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[110]                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[90]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[89]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[89]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[88]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[88]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[87]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[82]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[81]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[76]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[75]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[73]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[72]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[70]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[69]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[66]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[65]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[62]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[61]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[58]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[57]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[55]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[54]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[44]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[43]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.736      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[28]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[27]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[17]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[16]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[13]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[12]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[3]    ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[2]                                                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.738      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[1]    ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[0]                                                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[110]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[109]                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[104]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[103]                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[101]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[100]                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[100]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[99]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[98]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[97]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[97]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[96]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[96]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[95]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[83]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[82]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[81]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[80]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[74]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[73]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[71]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[70]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[59]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[58]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[56]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[55]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[45]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[44]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.737      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[40]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[39]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.737      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[34]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[33]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[33]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[32]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[29]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[28]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[27]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[26]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[24]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[23]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[18]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[17]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[10]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[9]                                                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[9]    ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[8]                                                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[7]    ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[6]                                                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[126]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[125]                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.739      ;
; 0.473 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[106]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[105]                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.739      ;
; 0.473 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[105]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[104]                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.739      ;
; 0.473 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[91]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[90]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.739      ;
; 0.473 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[86]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[85]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.739      ;
; 0.473 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[60]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[59]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.739      ;
; 0.473 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[54]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[53]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.739      ;
; 0.473 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[53]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[52]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.739      ;
; 0.473 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[46]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[45]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.738      ;
; 0.473 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[42]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[41]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.738      ;
; 0.473 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[41]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[40]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.738      ;
; 0.473 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[39]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[38]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.738      ;
; 0.473 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[37]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[36]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.738      ;
; 0.473 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[30]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[29]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.739      ;
; 0.473 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[15]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[14]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.739      ;
; 0.473 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[14]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[13]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.739      ;
; 0.473 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[8]    ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[7]                                                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.739      ;
; 0.474 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[3] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_datain_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.528      ; 1.252      ;
; 0.474 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[47]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[46]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.739      ;
; 0.475 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[48]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[47]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.740      ;
; 0.476 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[10]                 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[10]                                                                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.743      ;
; 0.481 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_datain_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.527      ; 1.258      ;
; 0.483 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_datain_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.528      ; 1.261      ;
; 0.503 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_datain_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.528      ; 1.281      ;
; 0.503 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[3] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_datain_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.511      ; 1.264      ;
; 0.510 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_datain_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.512      ; 1.272      ;
; 0.514 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_datain_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.527      ; 1.291      ;
; 0.587 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_datain_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.510      ; 1.347      ;
; 0.605 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_datain_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.527      ; 1.382      ;
; 0.610 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[51]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[50]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.875      ;
; 0.610 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[23]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[22]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.876      ;
; 0.610 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[22]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[21]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.876      ;
; 0.611 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[35]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[34]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.876      ;
; 0.619 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_datain_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.510      ; 1.379      ;
; 0.621 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[108]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[107]                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.887      ;
; 0.621 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[77]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[76]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.887      ;
; 0.623 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[6]    ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[5]                                                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.889      ;
; 0.624 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[93]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[92]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.891      ;
; 0.630 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_datain_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.513      ; 1.393      ;
; 0.644 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_datain_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.510      ; 1.404      ;
+-------+--------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                           ; To Node                                                                                                                                                             ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_count_reg[1]                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_count_reg[1]                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_count_reg[2]                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_count_reg[2]                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_count_reg[3]                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_count_reg[3]                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[1]                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[1]                                                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[2]                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[2]                                                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[3]                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[3]                                                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[4]                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[4]                                                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[5]                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[5]                                                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[6]                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[6]                                                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[7]                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[7]                                                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[0]                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[0]                                                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[4]                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[4]                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[1]                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[1]                                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[0]                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[0]                                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|skctl_reg[1]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|skctl_reg[1]                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[2]                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[2]                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:pokey_keyboard_scanner1|shift_pressed_reg   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:pokey_keyboard_scanner1|shift_pressed_reg   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[0]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[0]                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[1]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[1]                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[2]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[2]                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[3]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[3]                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[5]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[5]                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[6]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[6]                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:pokey_keyboard_scanner1|control_pressed_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:pokey_keyboard_scanner1|control_pressed_reg ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:pokey_keyboard_scanner1|break_pressed_reg   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_keyboard_scanner:pokey_keyboard_scanner1|break_pressed_reg   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|irqst_reg[7]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|irqst_reg[7]                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[0]                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[0]                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[0]                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[0]                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|cpu_fetch_real_reg                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|cpu_fetch_real_reg                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_refresh_count|value_reg[1]                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_refresh_count|value_reg[1]                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_refresh_count|value_reg[2]                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_refresh_count|value_reg[2]                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_refresh_count|value_reg[3]                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_refresh_count|value_reg[3]                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_pending_reg                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_pending_reg                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_noise_filter:pokey_noise_filter3|out_reg                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_noise_filter:pokey_noise_filter3|out_reg                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_noise_filter:pokey_noise_filter2|out_reg                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_noise_filter:pokey_noise_filter2|out_reg                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_ready_reg                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_ready_reg                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|porta_control_reg[3]                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|porta_control_reg[3]                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|porta_control_reg[4]                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|porta_control_reg[4]                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|irqa_reg[1]                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|irqa_reg[1]                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|CA2_output_reg                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|CA2_output_reg                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[0]                                                                                    ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[0]                                                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[1]                                                                                    ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[1]                                                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[3]                                                                                    ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[3]                                                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[2]                                                                                    ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[2]                                                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|pending_extended_reg                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|pending_extended_reg                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|pending_keyup_reg                                                                                  ; ps2_to_atari800:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|pending_keyup_reg                                                                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[1]                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[1]                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[2]                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[2]                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[3]                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[3]                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[370]                                                                                                                     ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[370]                                                                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[126]                                                                                                                     ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[126]                                                                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[46]                                                                                                                      ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[46]                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[50]                                                                                                                      ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[50]                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[118]                                                                                                                     ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[118]                                                                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[12]                                                                                                                      ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[12]                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[88]                                                                                                                      ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[88]                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[102]                                                                                                                     ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[102]                                                                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[62]                                                                                                                      ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[62]                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[52]                                                                                                                      ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[52]                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[58]                                                                                                                      ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[58]                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[13]                                                                                                                      ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[13]                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[44]                                                                                                                      ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[44]                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[84]                                                                                                                      ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[84]                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[29]                                                                                                                      ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[29]                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[30]                                                                                                                      ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[30]                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[27]                                                                                                                      ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[27]                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[82]                                                                                                                      ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[82]                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[34]                                                                                                                      ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[34]                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[74]                                                                                                                      ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[74]                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[273]                                                                                                                     ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[273]                                                                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[26]                                                                                                                      ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[26]                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[28]                                                                                                                      ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[28]                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[22]                                                                                                                      ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[22]                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[91]                                                                                                                      ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[91]                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[21]                                                                                                                      ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[21]                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[43]                                                                                                                      ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[43]                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[45]                                                                                                                      ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[45]                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[37]                                                                                                                      ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[37]                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[41]                                                                                                                      ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[41]                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[3]                                                                                                                       ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[3]                                                                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[59]                                                                                                                      ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[59]                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[65]                                                                                                                      ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[65]                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[75]                                                                                                                      ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[75]                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[53]                                                                                                                      ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[53]                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[36]                                                                                                                      ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[36]                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[61]                                                                                                                      ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[61]                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[35]                                                                                                                      ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[35]                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[4]                                                                                                                       ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[4]                                                                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[54]                                                                                                                      ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[54]                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[33]                                                                                                                      ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[33]                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[38]                                                                                                                      ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[38]                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[5]                                                                                                                       ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[5]                                                                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[60]                                                                                                                      ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[60]                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|state_reg[0]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|state_reg[0]                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|state_reg[1]                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|state_reg[1]                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[20]                                                                                                                      ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[20]                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[119]                                                                                                                     ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[119]                                                                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                             ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                 ; To Node                                                   ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 0.403 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; sdram_ctrl:sdram_controller|sdram_rdy                     ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; sdram_ctrl:sdram_controller|r_refr_act                    ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; sdram_request_reg                                         ; sdram_request_reg                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; sdram_ctrl:sdram_controller|r_wr_act                      ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; sdram_request_complete_reg                                ; sdram_request_complete_reg                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.404 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; sdram_ctrl:sdram_controller|r_rd_act                      ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.418 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.684      ;
; 0.419 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.684      ;
; 0.472 ; ram_bena_reg[0]                                           ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.737      ;
; 0.474 ; ram_bena_reg[1]                                           ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.739      ;
; 0.503 ; seq_reg[10]                                               ; seq_reg[11]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.768      ;
; 0.514 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.779      ;
; 0.520 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.785      ;
; 0.541 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.806      ;
; 0.609 ; sdram_ctrl:sdram_controller|r_rd_act                      ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.874      ;
; 0.626 ; seq_reg[9]                                                ; seq_reg[10]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.891      ;
; 0.647 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.913      ;
; 0.653 ; sdram_ctrl:sdram_controller|r_wr_act                      ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.919      ;
; 0.687 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.952      ;
; 0.687 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.952      ;
; 0.688 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.953      ;
; 0.689 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.954      ;
; 0.690 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.955      ;
; 0.690 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.955      ;
; 0.692 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.957      ;
; 0.692 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.957      ;
; 0.693 ; seq_reg[1]                                                ; seq_reg[2]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.958      ;
; 0.693 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.958      ;
; 0.693 ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.958      ;
; 0.704 ; sdram_ctrl:sdram_controller|r_refr_req                    ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.970      ;
; 0.706 ; sdram_ctrl:sdram_controller|r_refr_req                    ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.972      ;
; 0.711 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.976      ;
; 0.712 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.977      ;
; 0.735 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.000      ;
; 0.748 ; sdram_ctrl:sdram_controller|r_rd_act                      ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.013      ;
; 0.806 ; sdram_request_complete_reg                                ; sdram_request_reg                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.072      ;
; 0.831 ; sdram_ctrl:sdram_controller|r_refr_act                    ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.097      ;
; 0.896 ; seq_reg[11]                                               ; seq_reg[0]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.161      ;
; 0.905 ; seq_reg[2]                                                ; seq_reg[3]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.170      ;
; 0.905 ; seq_reg[3]                                                ; seq_reg[4]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.170      ;
; 0.925 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.191      ;
; 0.946 ; sdram_ctrl:sdram_controller|r_wr_act                      ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.211      ;
; 0.949 ; sdram_ctrl:sdram_controller|r_wr_act                      ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.214      ;
; 0.952 ; seq_reg[4]                                                ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 1.215      ;
; 0.962 ; sdram_ctrl:sdram_controller|r_wr_act                      ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.228      ;
; 0.982 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.248      ;
; 1.007 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.272      ;
; 1.008 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.273      ;
; 1.009 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.274      ;
; 1.010 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.275      ;
; 1.010 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.275      ;
; 1.010 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.275      ;
; 1.013 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.278      ;
; 1.014 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.279      ;
; 1.014 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.279      ;
; 1.022 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.287      ;
; 1.023 ; sdram_ctrl:sdram_controller|r_refr_req                    ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.289      ;
; 1.023 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.288      ;
; 1.026 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.291      ;
; 1.026 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.291      ;
; 1.027 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.292      ;
; 1.038 ; sdram_ctrl:sdram_controller|r_psel[0]                     ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.305      ;
; 1.041 ; sdram_ctrl:sdram_controller|r_refr_act                    ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.307      ;
; 1.047 ; seq_reg[5]                                                ; seq_reg[6]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.312      ;
; 1.068 ; seq_reg[6]                                                ; seq_reg[7]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.333      ;
; 1.073 ; seq_reg[4]                                                ; seq_reg[5]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.338      ;
; 1.085 ; seq_reg[8]                                                ; seq_reg[9]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.350      ;
; 1.088 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.354      ;
; 1.102 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.367      ;
; 1.108 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.373      ;
; 1.108 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.373      ;
; 1.122 ; sdram_ctrl:sdram_controller|r_refr_req                    ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.387      ;
; 1.130 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.395      ;
; 1.131 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.396      ;
; 1.132 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.397      ;
; 1.132 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.397      ;
; 1.132 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.397      ;
; 1.136 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.401      ;
; 1.136 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.401      ;
; 1.145 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.410      ;
; 1.148 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.413      ;
; 1.148 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.413      ;
; 1.149 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.414      ;
; 1.152 ; sdram_ctrl:sdram_controller|r_psel[0]                     ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.419      ;
; 1.156 ; sdram_ctrl:sdram_controller|r_psel[0]                     ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.423      ;
; 1.163 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 1.426      ;
; 1.165 ; seq_reg[0]                                                ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.431      ;
; 1.192 ; sdram_ctrl:sdram_controller|r_rddata[15]                  ; ram_do_reg[15]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.239      ; 1.626      ;
; 1.194 ; sdram_ctrl:sdram_controller|r_rddata[15]                  ; ram_do_reg[7]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.239      ; 1.628      ;
; 1.204 ; seq_reg[11]                                               ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.470      ;
; 1.207 ; seq_reg[11]                                               ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.473      ;
; 1.208 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.474      ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                       ;
+-------+---------------------------------------+---------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                                                                                     ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+---------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[2]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 4.898      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[4]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 4.896      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[3]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 4.898      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[21]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.166     ; 4.888      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.167     ; 4.887      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[29]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 4.878      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[29]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.171     ; 4.883      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[16]                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 4.892      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[17]                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 4.892      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[18]                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 4.892      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[19]                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 4.892      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[20]                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 4.892      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[21]                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 4.892      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[22]                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 4.892      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[23]                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 4.892      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[24]                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 4.892      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[25]                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 4.892      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[25]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.166     ; 4.888      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[18]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.166     ; 4.888      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[7]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 4.898      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[28]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.171     ; 4.883      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[30]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 4.896      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[26]                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 4.892      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[27]                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 4.892      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[28]                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 4.892      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[29]                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 4.892      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[30]                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 4.892      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[30]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 4.892      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[30]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 4.892      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[30]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.172     ; 4.882      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[3]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 4.897      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[3]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.154     ; 4.900      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[4]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 4.897      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[4]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 4.897      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[1]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.154     ; 4.900      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[2]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 4.897      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[2]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.154     ; 4.900      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[22]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.172     ; 4.882      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[21]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.171     ; 4.883      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[21]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.161     ; 4.893      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[21]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.161     ; 4.893      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[21]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 4.894      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[21]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.170     ; 4.884      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[21]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 4.896      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[21]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 4.896      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[31]                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 4.892      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[31]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.161     ; 4.893      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[31]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.161     ; 4.893      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[31]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 4.896      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[31]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.155     ; 4.899      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[31]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 4.896      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[31]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.155     ; 4.899      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[22]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.161     ; 4.893      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[22]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.161     ; 4.893      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[22]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 4.889      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[22]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.170     ; 4.884      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[22]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 4.889      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[27]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 4.896      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[27]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 4.892      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[27]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 4.892      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[12]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.155     ; 4.899      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[6]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 4.897      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[7]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 4.897      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[7]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.155     ; 4.899      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[5]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 4.897      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[5]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.154     ; 4.900      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[16]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 4.896      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[13]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.166     ; 4.888      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[13]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 4.896      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[13]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.155     ; 4.899      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[13]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.172     ; 4.882      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[13]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 4.896      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[19]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.170     ; 4.884      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[18]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.170     ; 4.884      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[20]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.172     ; 4.882      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[20]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.170     ; 4.884      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[17]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.166     ; 4.888      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[17]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.170     ; 4.884      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[4]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.155     ; 4.899      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[4]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.154     ; 4.900      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[1]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 4.897      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[0]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 4.897      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[24]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 4.892      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[25]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 4.892      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[26]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 4.878      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[26]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 4.892      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[28]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 4.892      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[29]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 4.892      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf3_reg[0]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.166     ; 4.888      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf3_reg[1]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.166     ; 4.888      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf3_reg[5]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.166     ; 4.888      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|serin_clock_reg      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.166     ; 4.888      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|serin_clock_last_reg ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.166     ; 4.888      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pot_counter_reg[0]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 4.879      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pot_counter_reg[1]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 4.879      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pot_counter_reg[2]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 4.879      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pot_counter_reg[3]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 4.879      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pot_counter_reg[4]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 4.879      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pot_counter_reg[5]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 4.879      ;
; 6.696 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pot_counter_reg[6]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 4.879      ;
+-------+---------------------------------------+---------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                         ;
+-------+------------------------+----------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                      ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+----------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 8.124 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[3]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.362     ; 3.126      ;
; 8.128 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.359     ; 3.125      ;
; 8.128 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[0]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.358     ; 3.126      ;
; 8.128 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.358     ; 3.126      ;
; 8.128 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[1]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.358     ; 3.126      ;
; 8.128 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[2]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.358     ; 3.126      ;
; 8.129 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.363     ; 3.120      ;
; 8.130 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.365     ; 3.117      ;
; 8.134 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[0]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.191     ; 3.298      ;
; 8.134 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.191     ; 3.298      ;
; 8.134 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.191     ; 3.298      ;
; 8.134 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.191     ; 3.298      ;
; 8.134 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[0]    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 3.300      ;
; 8.134 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[1]    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.191     ; 3.298      ;
; 8.134 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.191     ; 3.298      ;
; 8.146 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[13]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.351     ; 3.115      ;
; 8.146 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[12]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.352     ; 3.114      ;
; 8.146 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[14]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.351     ; 3.115      ;
; 8.146 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[15]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.351     ; 3.115      ;
; 8.146 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[11]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.352     ; 3.114      ;
; 8.146 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[10]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.352     ; 3.114      ;
; 8.146 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[3]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.242     ; 3.235      ;
; 8.150 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[9]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.352     ; 3.110      ;
; 8.150 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[8]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.346     ; 3.116      ;
; 8.150 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[0]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.238     ; 3.235      ;
; 8.150 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.238     ; 3.235      ;
; 8.150 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.238     ; 3.235      ;
; 8.150 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[6]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.239     ; 3.234      ;
; 8.150 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.238     ; 3.235      ;
; 8.151 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.243     ; 3.229      ;
; 8.152 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.245     ; 3.226      ;
; 8.159 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.177     ; 3.287      ;
; 8.159 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.179     ; 3.285      ;
; 8.159 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.179     ; 3.285      ;
; 8.159 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.179     ; 3.285      ;
; 8.159 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 3.286      ;
; 8.159 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 3.286      ;
; 8.168 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.232     ; 3.223      ;
; 8.168 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[11] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.232     ; 3.223      ;
; 8.168 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[12] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.232     ; 3.223      ;
; 8.168 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[13] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.231     ; 3.224      ;
; 8.168 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[14] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.231     ; 3.224      ;
; 8.168 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[15] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.231     ; 3.224      ;
; 8.172 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.226     ; 3.225      ;
; 8.172 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[9]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.232     ; 3.219      ;
; 8.189 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.183     ; 3.377      ;
; 8.189 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 3.378      ;
; 8.189 ; sdram_reset_ctrl_n_reg ; ram_do_reg[15]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 3.378      ;
; 8.228 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.184     ; 3.337      ;
; 8.228 ; sdram_reset_ctrl_n_reg ; ram_do_reg[11]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.184     ; 3.337      ;
; 8.232 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 3.335      ;
; 8.232 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 3.335      ;
; 8.244 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.190     ; 3.315      ;
; 8.244 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.190     ; 3.315      ;
; 8.244 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.190     ; 3.315      ;
; 8.244 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.190     ; 3.315      ;
; 8.244 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.190     ; 3.315      ;
; 8.244 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.190     ; 3.315      ;
; 8.245 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 3.315      ;
; 8.245 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 3.315      ;
; 8.245 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 3.315      ;
; 8.245 ; sdram_reset_ctrl_n_reg ; ram_do_reg[20]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 3.315      ;
; 8.245 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 3.315      ;
; 8.245 ; sdram_reset_ctrl_n_reg ; ram_do_reg[25]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 3.315      ;
; 8.245 ; sdram_reset_ctrl_n_reg ; ram_do_reg[19]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 3.315      ;
; 8.245 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 3.315      ;
; 8.245 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 3.315      ;
; 8.245 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 3.315      ;
; 8.366 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 3.068      ;
; 8.366 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 3.068      ;
; 8.366 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 3.068      ;
; 8.366 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 3.068      ;
; 8.682 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 2.889      ;
; 8.682 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 2.889      ;
; 8.682 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 2.889      ;
; 8.682 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 2.889      ;
; 8.682 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 2.889      ;
; 8.682 ; sdram_reset_ctrl_n_reg ; seq_reg[5]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 2.889      ;
; 8.682 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 2.889      ;
; 8.682 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 2.889      ;
; 8.682 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 2.889      ;
; 8.682 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 2.889      ;
; 8.682 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 2.889      ;
; 8.682 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 2.889      ;
; 8.682 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 2.889      ;
; 8.682 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 2.889      ;
; 8.682 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.179     ; 2.888      ;
; 8.682 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.179     ; 2.888      ;
; 8.682 ; sdram_reset_ctrl_n_reg ; ram_do_reg[5]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.179     ; 2.888      ;
; 8.682 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.179     ; 2.888      ;
; 8.682 ; sdram_reset_ctrl_n_reg ; ram_do_reg[13]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.179     ; 2.888      ;
; 8.682 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 2.889      ;
; 8.682 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 2.889      ;
; 8.682 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 2.889      ;
; 8.682 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 2.889      ;
; 8.682 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.180     ; 2.887      ;
; 8.682 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.180     ; 2.887      ;
; 8.682 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.180     ; 2.887      ;
; 8.682 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.180     ; 2.887      ;
; 8.682 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.179     ; 2.888      ;
+-------+------------------------+----------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                        ;
+--------+-------------------+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node         ; To Node                                                                                         ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 11.795 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vsync_reg                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.532      ;
; 11.795 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.169     ; 5.533      ;
; 11.795 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.169     ; 5.533      ;
; 11.795 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.169     ; 5.533      ;
; 11.795 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.169     ; 5.533      ;
; 11.795 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.169     ; 5.533      ;
; 11.795 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.169     ; 5.533      ;
; 11.796 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|hsync_reg                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.531      ;
; 11.796 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.531      ;
; 11.796 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.531      ;
; 11.816 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.222     ; 5.459      ;
; 11.816 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.222     ; 5.459      ;
; 11.848 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.201     ; 5.448      ;
; 11.850 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.201     ; 5.446      ;
; 12.295 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[107] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.171     ; 5.157      ;
; 12.295 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[106] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.171     ; 5.157      ;
; 12.295 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[105] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.171     ; 5.157      ;
; 12.295 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[104] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.171     ; 5.157      ;
; 12.295 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[103] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.171     ; 5.157      ;
; 12.295 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[102] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.171     ; 5.157      ;
; 12.295 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[101] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.171     ; 5.157      ;
; 12.295 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[100] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.171     ; 5.157      ;
; 12.295 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[99]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.171     ; 5.157      ;
; 12.295 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[98]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.171     ; 5.157      ;
; 12.295 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[97]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.171     ; 5.157      ;
; 12.295 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[96]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.171     ; 5.157      ;
; 12.295 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[95]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.171     ; 5.157      ;
; 12.295 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[94]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.171     ; 5.157      ;
; 12.295 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[93]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.171     ; 5.157      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[123] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.171     ; 5.156      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[122] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.171     ; 5.156      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[121] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.171     ; 5.156      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[120] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.171     ; 5.156      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[119] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.171     ; 5.156      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[118] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.171     ; 5.156      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[117] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.171     ; 5.156      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[116] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.171     ; 5.156      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[115] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.171     ; 5.156      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[114] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.171     ; 5.156      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[113] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.171     ; 5.156      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[112] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.171     ; 5.156      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[111] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.171     ; 5.156      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[110] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.171     ; 5.156      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[109] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.171     ; 5.156      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[108] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.171     ; 5.156      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[92]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.157      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[91]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.157      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[90]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.157      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[89]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.157      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[88]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.157      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[87]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.157      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[86]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.157      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[85]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.157      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[84]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.157      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[83]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.157      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[82]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.157      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[81]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.157      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[80]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.157      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[79]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.157      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[78]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.157      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[77]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.157      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[76]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.157      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[75]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.157      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[74]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.157      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[73]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.157      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[72]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.157      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[71]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.157      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[70]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.157      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[69]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.157      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[68]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.157      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[67]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.157      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[66]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.157      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[65]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.157      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[64]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.157      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[63]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.157      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[62]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.157      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[61]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.157      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[60]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.157      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[59]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.157      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[58]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.157      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[57]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.157      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[56]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.157      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[55]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.157      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[54]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.157      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[53]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.157      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[52]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.157      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[51]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.157      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[50]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.157      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[49]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.157      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[48]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.157      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[47]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.157      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[46]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.157      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[45]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.157      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[44]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.157      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[43]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.157      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[42]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.157      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[41]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.157      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[40]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.157      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[39]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.157      ;
; 12.296 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[38]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.170     ; 5.157      ;
+--------+-------------------+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                       ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                                   ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 2.337 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 2.709      ;
; 2.337 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 2.709      ;
; 2.337 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 2.709      ;
; 2.337 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 2.709      ;
; 2.337 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 2.709      ;
; 2.337 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 2.709      ;
; 2.337 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 2.709      ;
; 2.337 ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 2.709      ;
; 2.337 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 2.709      ;
; 2.337 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 2.709      ;
; 2.337 ; sdram_reset_ctrl_n_reg ; ram_di_reg[15]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 2.709      ;
; 2.338 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 2.709      ;
; 2.338 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 2.709      ;
; 2.338 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 2.709      ;
; 2.338 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 2.709      ;
; 2.338 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 2.709      ;
; 2.338 ; sdram_reset_ctrl_n_reg ; seq_reg[5]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 2.709      ;
; 2.338 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 2.709      ;
; 2.338 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 2.709      ;
; 2.338 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 2.709      ;
; 2.338 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 2.709      ;
; 2.338 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 2.709      ;
; 2.338 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 2.709      ;
; 2.338 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 2.710      ;
; 2.338 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 2.710      ;
; 2.338 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 2.710      ;
; 2.338 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 2.710      ;
; 2.338 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 2.710      ;
; 2.338 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 2.710      ;
; 2.338 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 2.710      ;
; 2.338 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 2.710      ;
; 2.338 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 2.710      ;
; 2.338 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 2.710      ;
; 2.338 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 2.710      ;
; 2.338 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 2.710      ;
; 2.338 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 2.710      ;
; 2.338 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.708      ;
; 2.338 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.708      ;
; 2.338 ; sdram_reset_ctrl_n_reg ; ram_do_reg[5]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.708      ;
; 2.338 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.708      ;
; 2.338 ; sdram_reset_ctrl_n_reg ; ram_do_reg[13]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.708      ;
; 2.338 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 2.709      ;
; 2.338 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.708      ;
; 2.338 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.708      ;
; 2.338 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.708      ;
; 2.338 ; sdram_reset_ctrl_n_reg ; ram_do_reg[9]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.708      ;
; 2.338 ; sdram_reset_ctrl_n_reg ; ram_do_reg[14]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.708      ;
; 2.338 ; sdram_reset_ctrl_n_reg ; ram_do_reg[12]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.708      ;
; 2.338 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.708      ;
; 2.338 ; sdram_reset_ctrl_n_reg ; ram_do_reg[8]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.708      ;
; 2.338 ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 2.709      ;
; 2.338 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 2.709      ;
; 2.338 ; sdram_reset_ctrl_n_reg ; ram_di_reg[6]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 2.709      ;
; 2.338 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 2.709      ;
; 2.338 ; sdram_reset_ctrl_n_reg ; ram_di_reg[11]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 2.709      ;
; 2.338 ; sdram_reset_ctrl_n_reg ; ram_di_reg[12]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 2.709      ;
; 2.338 ; sdram_reset_ctrl_n_reg ; ram_di_reg[14]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 2.709      ;
; 2.338 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.708      ;
; 2.338 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 2.710      ;
; 2.338 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 2.709      ;
; 2.338 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 2.709      ;
; 2.339 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 2.708      ;
; 2.339 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 2.708      ;
; 2.339 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 2.708      ;
; 2.339 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 2.708      ;
; 2.339 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.151      ; 2.704      ;
; 2.339 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[0]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 2.708      ;
; 2.339 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 2.708      ;
; 2.339 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[1]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 2.708      ;
; 2.339 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 2.708      ;
; 2.340 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.707      ;
; 2.340 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.707      ;
; 2.340 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.707      ;
; 2.340 ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.707      ;
; 2.573 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.152      ; 2.856      ;
; 2.573 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.152      ; 2.856      ;
; 2.574 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.152      ; 2.857      ;
; 2.574 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.152      ; 2.857      ;
; 2.720 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 3.080      ;
; 2.720 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 3.080      ;
; 2.720 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 3.080      ;
; 2.720 ; sdram_reset_ctrl_n_reg ; ram_do_reg[20]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 3.080      ;
; 2.720 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 3.080      ;
; 2.720 ; sdram_reset_ctrl_n_reg ; ram_do_reg[25]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 3.080      ;
; 2.720 ; sdram_reset_ctrl_n_reg ; ram_do_reg[19]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 3.080      ;
; 2.720 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 3.080      ;
; 2.720 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 3.080      ;
; 2.720 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 3.080      ;
; 2.721 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.145      ; 3.080      ;
; 2.721 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.145      ; 3.080      ;
; 2.721 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.145      ; 3.080      ;
; 2.721 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.145      ; 3.080      ;
; 2.721 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.145      ; 3.080      ;
; 2.721 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.145      ; 3.080      ;
; 2.727 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.154      ; 3.095      ;
; 2.727 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.154      ; 3.095      ;
; 2.734 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.152      ; 3.100      ;
; 2.734 ; sdram_reset_ctrl_n_reg ; ram_do_reg[11]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.152      ; 3.100      ;
; 2.763 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 3.130      ;
; 2.764 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 3.131      ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                         ;
+-------+---------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                                                                                                                                      ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 3.704 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[5]                                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.592      ; 4.512      ;
; 4.124 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|delay_line:stimer_delay|shift_reg[2]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.181      ; 4.521      ;
; 4.124 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|delay_line:stimer_delay|shift_reg[1]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.181      ; 4.521      ;
; 4.124 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|delay_line:stimer_delay|shift_reg[0]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.181      ; 4.521      ;
; 4.124 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf2_reg[5]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.181      ; 4.521      ;
; 4.124 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf2_reg[0]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.181      ; 4.521      ;
; 4.124 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf2_reg[1]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.181      ; 4.521      ;
; 4.124 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf2_reg[2]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.181      ; 4.521      ;
; 4.124 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf2_reg[3]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.181      ; 4.521      ;
; 4.124 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf2_reg[4]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.181      ; 4.521      ;
; 4.124 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf2_reg[7]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.181      ; 4.521      ;
; 4.124 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf2_reg[6]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.181      ; 4.521      ;
; 4.124 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf3_reg[2]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.181      ; 4.521      ;
; 4.124 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf3_reg[3]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.181      ; 4.521      ;
; 4.124 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf3_reg[7]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.181      ; 4.521      ;
; 4.124 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf3_reg[4]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.181      ; 4.521      ;
; 4.124 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|serin_bitcount_reg[1]                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.181      ; 4.521      ;
; 4.124 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|serin_bitcount_reg[2]                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.181      ; 4.521      ;
; 4.124 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|serin_bitcount_reg[0]                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.181      ; 4.521      ;
; 4.124 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|skctl_reg[2]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.181      ; 4.521      ;
; 4.124 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|skctl_reg[3]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.181      ; 4.521      ;
; 4.124 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[0]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.181      ; 4.521      ;
; 4.124 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[0]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.182      ; 4.522      ;
; 4.124 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[2]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.181      ; 4.521      ;
; 4.124 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[1]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.181      ; 4.521      ;
; 4.124 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[1]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.182      ; 4.522      ;
; 4.124 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[2]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.182      ; 4.522      ;
; 4.124 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[3]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.181      ; 4.521      ;
; 4.124 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[3]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.182      ; 4.522      ;
; 4.124 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[4]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.181      ; 4.521      ;
; 4.124 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[4]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.182      ; 4.522      ;
; 4.124 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[6]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.181      ; 4.521      ;
; 4.124 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[5]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.181      ; 4.521      ;
; 4.124 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[5]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.182      ; 4.522      ;
; 4.124 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[6]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.182      ; 4.522      ;
; 4.124 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[7]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.181      ; 4.521      ;
; 4.124 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[7]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.182      ; 4.522      ;
; 4.124 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.182      ; 4.522      ;
; 4.124 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.182      ; 4.522      ;
; 4.124 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf1_reg[4]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.181      ; 4.521      ;
; 4.124 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|skctl_reg[7]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.181      ; 4.521      ;
; 4.124 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|delay_line:serout_clock_delay|shift_reg[1]                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.181      ; 4.521      ;
; 4.124 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|delay_line:serout_clock_delay|shift_reg[0]                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.181      ; 4.521      ;
; 4.124 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|serout_clock_reg                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.181      ; 4.521      ;
; 4.124 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|serout_clock_last_reg                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.181      ; 4.521      ;
; 4.124 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|serout_holding_full_reg                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.178      ; 4.518      ;
; 4.124 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|serout_active_reg                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.181      ; 4.521      ;
; 4.124 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|serial_out_reg                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.181      ; 4.521      ;
; 4.124 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|twotone_reg                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.181      ; 4.521      ;
; 4.124 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|sio_out_reg                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.181      ; 4.521      ;
; 4.124 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|irqst_reg[3]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.178      ; 4.518      ;
; 4.125 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.176      ; 4.517      ;
; 4.125 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[8]                                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.176      ; 4.517      ;
; 4.125 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[9]                                                                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.177      ; 4.518      ;
; 4.125 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[10]                                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.177      ; 4.518      ;
; 4.125 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.176      ; 4.517      ;
; 4.126 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[0]                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.172      ; 4.514      ;
; 4.126 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[1]                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.172      ; 4.514      ;
; 4.126 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[2]                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.172      ; 4.514      ;
; 4.126 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[3]                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.172      ; 4.514      ;
; 4.126 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[4]                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.172      ; 4.514      ;
; 4.126 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[5]                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.172      ; 4.514      ;
; 4.126 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[6]                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.172      ; 4.514      ;
; 4.126 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[7]                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.172      ; 4.514      ;
; 4.126 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[8]                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.172      ; 4.514      ;
; 4.126 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[9]                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.172      ; 4.514      ;
; 4.126 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[10]                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.172      ; 4.514      ;
; 4.126 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[11]                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.172      ; 4.514      ;
; 4.126 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[12]                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.172      ; 4.514      ;
; 4.126 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[13]                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.172      ; 4.514      ;
; 4.126 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[14]                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.172      ; 4.514      ;
; 4.126 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[15]                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.172      ; 4.514      ;
; 4.126 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[6]                                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.172      ; 4.514      ;
; 4.126 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[30]                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.173      ; 4.515      ;
; 4.126 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[30]                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.174      ; 4.516      ;
; 4.126 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[30]                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.173      ; 4.515      ;
; 4.126 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[4]                                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.172      ; 4.514      ;
; 4.126 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[27]                                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.174      ; 4.516      ;
; 4.126 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[27]                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.174      ; 4.516      ;
; 4.126 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[27]                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.173      ; 4.515      ;
; 4.126 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[27]                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.173      ; 4.515      ;
; 4.126 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[13]                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.171      ; 4.513      ;
; 4.126 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[13]                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.171      ; 4.513      ;
; 4.126 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|state_reg[3]                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.179      ; 4.521      ;
; 4.126 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|state_reg[0]                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.179      ; 4.521      ;
; 4.126 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|command_reg                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.179      ; 4.521      ;
; 4.126 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|state_reg[1]                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.179      ; 4.521      ;
; 4.126 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|sio_in_reg                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.178      ; 4.520      ;
; 4.126 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[0]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.180      ; 4.522      ;
; 4.126 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[1]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.180      ; 4.522      ;
; 4.126 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[2]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.180      ; 4.522      ;
; 4.126 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[3]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.180      ; 4.522      ;
; 4.126 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[4]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.180      ; 4.522      ;
; 4.126 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[5]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.180      ; 4.522      ;
; 4.126 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf3_reg[6]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.179      ; 4.521      ;
; 4.126 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[6]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.180      ; 4.522      ;
; 4.126 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[7]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.180      ; 4.522      ;
; 4.126 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer3|delay_line:underflow0_delay|shift_reg[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.180      ; 4.522      ;
; 4.126 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|serin_bitcount_reg[3]                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.178      ; 4.520      ;
; 4.126 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|irqst_reg[5]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.178      ; 4.520      ;
+-------+---------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                        ;
+-------+-------------------+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node         ; To Node                                                                                         ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 4.061 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.186      ; 4.462      ;
; 4.061 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[2]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.186      ; 4.462      ;
; 4.061 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[3]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.186      ; 4.462      ;
; 4.061 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[4]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.186      ; 4.462      ;
; 4.061 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[5]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.186      ; 4.462      ;
; 4.061 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[6]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.186      ; 4.462      ;
; 4.061 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[7]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.186      ; 4.462      ;
; 4.061 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[8]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.186      ; 4.462      ;
; 4.061 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[9]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.186      ; 4.462      ;
; 4.061 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[10]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.186      ; 4.462      ;
; 4.061 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.186      ; 4.462      ;
; 4.061 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|buffer_select_reg                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.186      ; 4.462      ;
; 4.061 ; sdram_reset_n_reg ; half_scandouble_enable_reg                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.186      ; 4.462      ;
; 4.061 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.185      ; 4.461      ;
; 4.061 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[1]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.185      ; 4.461      ;
; 4.061 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[2]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.185      ; 4.461      ;
; 4.061 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[3]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.185      ; 4.461      ;
; 4.061 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[4]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.185      ; 4.461      ;
; 4.061 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[5]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.185      ; 4.461      ;
; 4.061 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[6]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.185      ; 4.461      ;
; 4.061 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[7]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.185      ; 4.461      ;
; 4.061 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[8]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.185      ; 4.461      ;
; 4.061 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[9]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.185      ; 4.461      ;
; 4.061 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[10]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.185      ; 4.461      ;
; 4.061 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[127] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 4.464      ;
; 4.061 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[126] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 4.464      ;
; 4.061 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[125] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 4.464      ;
; 4.061 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[124] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 4.464      ;
; 4.061 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[4]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 4.464      ;
; 4.061 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[3]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 4.464      ;
; 4.061 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[2]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 4.464      ;
; 4.061 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[1]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 4.464      ;
; 4.061 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[0]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 4.464      ;
; 4.061 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_hsync_reg                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 4.464      ;
; 4.061 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.184      ; 4.460      ;
; 4.061 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.186      ; 4.462      ;
; 4.061 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.186      ; 4.462      ;
; 4.061 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.186      ; 4.462      ;
; 4.061 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.186      ; 4.462      ;
; 4.061 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.186      ; 4.462      ;
; 4.061 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.186      ; 4.462      ;
; 4.061 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.186      ; 4.462      ;
; 4.097 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[123] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.165      ; 4.477      ;
; 4.097 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[122] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.165      ; 4.477      ;
; 4.097 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[121] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.165      ; 4.477      ;
; 4.097 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[120] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.165      ; 4.477      ;
; 4.097 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[119] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.165      ; 4.477      ;
; 4.097 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[118] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.165      ; 4.477      ;
; 4.097 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[117] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.165      ; 4.477      ;
; 4.097 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[116] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.165      ; 4.477      ;
; 4.097 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[115] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.165      ; 4.477      ;
; 4.097 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[114] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.165      ; 4.477      ;
; 4.097 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[113] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.165      ; 4.477      ;
; 4.097 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[112] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.165      ; 4.477      ;
; 4.097 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[111] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.165      ; 4.477      ;
; 4.097 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[110] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.165      ; 4.477      ;
; 4.097 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[109] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.165      ; 4.477      ;
; 4.097 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[108] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.165      ; 4.477      ;
; 4.097 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[92]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.166      ; 4.478      ;
; 4.097 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[91]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.166      ; 4.478      ;
; 4.097 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[90]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.166      ; 4.478      ;
; 4.097 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[89]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.166      ; 4.478      ;
; 4.097 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[88]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.166      ; 4.478      ;
; 4.097 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[87]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.166      ; 4.478      ;
; 4.097 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[86]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.166      ; 4.478      ;
; 4.097 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[85]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.166      ; 4.478      ;
; 4.097 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[84]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.166      ; 4.478      ;
; 4.097 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[83]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.166      ; 4.478      ;
; 4.097 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[82]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.166      ; 4.478      ;
; 4.097 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[81]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.166      ; 4.478      ;
; 4.097 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[80]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.166      ; 4.478      ;
; 4.097 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[79]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.166      ; 4.478      ;
; 4.097 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[78]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.166      ; 4.478      ;
; 4.097 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[77]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.166      ; 4.478      ;
; 4.097 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[76]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.166      ; 4.478      ;
; 4.097 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[75]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.166      ; 4.478      ;
; 4.097 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[74]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.166      ; 4.478      ;
; 4.097 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[73]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.166      ; 4.478      ;
; 4.097 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[72]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.166      ; 4.478      ;
; 4.097 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[71]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.166      ; 4.478      ;
; 4.097 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[70]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.166      ; 4.478      ;
; 4.097 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[69]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.166      ; 4.478      ;
; 4.097 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[68]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.166      ; 4.478      ;
; 4.097 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[67]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.166      ; 4.478      ;
; 4.097 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[66]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.166      ; 4.478      ;
; 4.097 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[65]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.166      ; 4.478      ;
; 4.097 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[64]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.166      ; 4.478      ;
; 4.097 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[63]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.166      ; 4.478      ;
; 4.097 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[62]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.166      ; 4.478      ;
; 4.097 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[61]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.166      ; 4.478      ;
; 4.097 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[60]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.166      ; 4.478      ;
; 4.097 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[59]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.166      ; 4.478      ;
; 4.097 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[58]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.166      ; 4.478      ;
; 4.097 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[57]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.166      ; 4.478      ;
; 4.097 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[56]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.166      ; 4.478      ;
; 4.097 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[55]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.166      ; 4.478      ;
; 4.097 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[54]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.166      ; 4.478      ;
; 4.097 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[53]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.166      ; 4.478      ;
; 4.097 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[52]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.166      ; 4.478      ;
; 4.097 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[51]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.166      ; 4.478      ;
+-------+-------------------+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                         ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                         ; Clock Edge ; Target                                                    ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[16]                                            ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[18]                                            ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[19]                                            ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[20]                                            ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[21]                                            ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[23]                                            ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[25]                                            ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[26]                                            ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[28]                                            ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[29]                                            ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[11]                                            ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[12]                                            ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[14]                                            ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[3]                                             ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[4]                                             ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[6]                                             ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[7]                                             ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[11]                                            ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[17]                                            ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[22]                                            ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[24]                                            ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[27]                                            ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[2]                                             ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[30]                                            ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[31]                                            ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[3]                                             ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[6]                                             ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_reg                      ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_act                    ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_act                      ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_reg                      ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|sdram_rdy                     ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_complete_reg                                ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_reg                                         ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[0]                                           ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[1]                                           ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[0]                                             ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[10]                                            ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[13]                                            ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[15]                                            ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[1]                                             ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[2]                                             ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[5]                                             ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[8]                                             ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[9]                                             ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[0]                                             ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[10]                                            ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[12]                                            ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[13]                                            ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[14]                                            ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[15]                                            ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[1]                                             ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[4]                                             ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[5]                                             ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[7]                                             ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[8]                                             ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[9]                                             ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel[0]                     ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_act                      ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_req                    ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[0]                                                ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[10]                                               ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[11]                                               ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[1]                                                ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[2]                                                ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[3]                                                ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[4]                                                ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[5]                                                ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[6]                                                ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[7]                                                ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[8]                                                ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[9]                                                ;
; 5.677 ; 5.832        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[3]                   ;
; 5.678 ; 5.833        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[5]                   ;
; 5.679 ; 5.834        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[0]                   ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                               ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                         ; Clock Edge ; Target                                                                                          ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------------------------+
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[108] ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[109] ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[10]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[110] ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[111] ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[112] ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[113] ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[114] ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[115] ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[116] ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[117] ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[118] ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[119] ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[11]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[120] ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[121] ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[122] ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[123] ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[12]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[13]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[14]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[15]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[16]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[17]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[18]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[19]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[20]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[21]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[22]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[23]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[24]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[25]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[26]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[27]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[28]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[29]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[30]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[31]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[32]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[33]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[34]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[51]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[52]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[53]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[54]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[55]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[56]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[57]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[58]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[59]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[5]   ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[60]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[61]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[62]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[63]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[64]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[65]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[66]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[67]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[68]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[69]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[6]   ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[70]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[71]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[72]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[73]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[74]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[75]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[76]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[77]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[78]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[79]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[7]   ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[80]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[81]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[82]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[83]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[84]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[85]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[86]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[87]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[88]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[89]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[8]   ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[90]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[91]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[92]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[9]   ;
; 8.511 ; 8.727        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[0]   ;
; 8.511 ; 8.727        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[100] ;
; 8.511 ; 8.727        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[101] ;
; 8.511 ; 8.727        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[102] ;
; 8.511 ; 8.727        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[103] ;
; 8.511 ; 8.727        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[104] ;
; 8.511 ; 8.727        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[105] ;
; 8.511 ; 8.727        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[106] ;
; 8.511 ; 8.727        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[107] ;
; 8.511 ; 8.727        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[124] ;
; 8.511 ; 8.727        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[125] ;
; 8.511 ; 8.727        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[126] ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                         ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                               ; Clock Edge ; Target                                                                                                                                                                                                                   ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 10.068 ; 10.284       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]                                           ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[0]                                                      ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[2]                                                      ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[3]                                                      ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[4]                                                      ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[5]                                                      ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[6]                                                      ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000001          ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001110          ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010000          ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010001          ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101001          ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101110          ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101111          ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110010          ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110011          ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110100          ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110101          ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110110          ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireWEn                      ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[0]                    ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[10]                   ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[11]                   ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[12]                   ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[15]                   ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[1]                    ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]                    ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[3]                    ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[4]                    ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[5]                    ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[8]                    ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[9]                    ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC16En                           ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5En                            ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5_8Bit                         ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[0]                        ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[1]                        ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[2]                        ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[3]                        ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[4]                        ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[5]                        ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[6]                        ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[7]                        ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1011           ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[0]                               ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[1]                               ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[2]                               ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[3]                               ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[4]                               ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[5]                               ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[6]                               ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[0]                          ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[10]                         ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[13]                         ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[14]                         ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[15]                         ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[1]                          ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[2]                          ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[7]                          ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[7]                                 ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[0]~_Duplicate_1   ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[1]~_Duplicate_1   ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxCtrlOut                   ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer1[0]                  ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer1[1]                  ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer1[2]                  ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer1[3]                  ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer3[0]                  ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer3[1]                  ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer3[2]                  ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer3[3]                  ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutIndex[0]           ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutIndex[1]           ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutStMachCurrState.10 ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|decBufferCnt                ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|fullSpeedRate_reg           ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|fullSpeedTick               ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[0]                        ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[1]                        ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[2]                        ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[3]                        ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[4]                        ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|lowSpeedTick                ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[1]                                                                         ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[2]                                                                         ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.001                             ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.010                             ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.011                             ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.100                             ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|SOFCntlGnt                                        ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|directCntlGnt                                     ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|muxCntl.00                                        ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|muxCntl.10                                        ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|sendPacketGnt                                     ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[10]                                          ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[11]                                          ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[12]                                          ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]                                          ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[14]                                          ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[15]                                          ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                   ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                         ; Clock Edge ; Target                                                                                                                                                                                             ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 17.223 ; 17.605       ; 0.382          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[0]                                          ;
; 17.223 ; 17.605       ; 0.382          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[1]                                          ;
; 17.223 ; 17.605       ; 0.382          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[2]                                          ;
; 17.223 ; 17.605       ; 0.382          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[3]                                          ;
; 17.223 ; 17.605       ; 0.382          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[4]                                          ;
; 17.223 ; 17.605       ; 0.382          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[10]                                               ;
; 17.223 ; 17.605       ; 0.382          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[11]                                               ;
; 17.223 ; 17.605       ; 0.382          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[12]                                               ;
; 17.223 ; 17.605       ; 0.382          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[13]                                               ;
; 17.223 ; 17.605       ; 0.382          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[14]                                               ;
; 17.223 ; 17.605       ; 0.382          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[15]                                               ;
; 17.223 ; 17.605       ; 0.382          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[16]                                               ;
; 17.223 ; 17.605       ; 0.382          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[17]                                               ;
; 17.223 ; 17.605       ; 0.382          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[18]                                               ;
; 17.223 ; 17.605       ; 0.382          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[19]                                               ;
; 17.223 ; 17.605       ; 0.382          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[20]                                               ;
; 17.223 ; 17.605       ; 0.382          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[5]                                                ;
; 17.223 ; 17.605       ; 0.382          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[6]                                                ;
; 17.223 ; 17.605       ; 0.382          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[7]                                                ;
; 17.223 ; 17.605       ; 0.382          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[8]                                                ;
; 17.223 ; 17.605       ; 0.382          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[9]                                                ;
; 17.241 ; 17.623       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[0]                                          ;
; 17.241 ; 17.623       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[1]                                          ;
; 17.241 ; 17.623       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[2]                                          ;
; 17.241 ; 17.623       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[3]                                          ;
; 17.241 ; 17.623       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[4]                                          ;
; 17.241 ; 17.623       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[10]                                               ;
; 17.241 ; 17.623       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[11]                                               ;
; 17.241 ; 17.623       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[12]                                               ;
; 17.241 ; 17.623       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[13]                                               ;
; 17.241 ; 17.623       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[14]                                               ;
; 17.241 ; 17.623       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[15]                                               ;
; 17.241 ; 17.623       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[16]                                               ;
; 17.241 ; 17.623       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[17]                                               ;
; 17.241 ; 17.623       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[18]                                               ;
; 17.241 ; 17.623       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[19]                                               ;
; 17.241 ; 17.623       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[20]                                               ;
; 17.241 ; 17.623       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[5]                                                ;
; 17.241 ; 17.623       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[6]                                                ;
; 17.241 ; 17.623       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[7]                                                ;
; 17.241 ; 17.623       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[8]                                                ;
; 17.241 ; 17.623       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[9]                                                ;
; 17.271 ; 17.487       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[0]             ;
; 17.271 ; 17.487       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[1]             ;
; 17.271 ; 17.487       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[2]             ;
; 17.271 ; 17.487       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[3]             ;
; 17.271 ; 17.487       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[0]        ;
; 17.271 ; 17.487       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[1]        ;
; 17.271 ; 17.487       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[2]        ;
; 17.271 ; 17.487       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[3]        ;
; 17.271 ; 17.487       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[0]       ;
; 17.271 ; 17.487       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[2]       ;
; 17.271 ; 17.487       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[5]       ;
; 17.271 ; 17.487       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[6]       ;
; 17.271 ; 17.487       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[2]  ;
; 17.271 ; 17.487       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[4]  ;
; 17.271 ; 17.487       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[5]  ;
; 17.271 ; 17.487       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[6]  ;
; 17.271 ; 17.487       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqSTB[2]         ;
; 17.273 ; 17.489       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInSTB[2]           ;
; 17.273 ; 17.489       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB[0]      ;
; 17.273 ; 17.489       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB[1]      ;
; 17.273 ; 17.489       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[0] ;
; 17.273 ; 17.489       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[1] ;
; 17.275 ; 17.491       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[3]       ;
; 17.275 ; 17.491       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[7]       ;
; 17.275 ; 17.491       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[0]  ;
; 17.275 ; 17.491       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[1]  ;
; 17.275 ; 17.491       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[3]  ;
; 17.275 ; 17.491       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[7]  ;
; 17.275 ; 17.491       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[11]           ;
; 17.275 ; 17.491       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[13]           ;
; 17.275 ; 17.491       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[15]           ;
; 17.275 ; 17.491       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[11]      ;
; 17.275 ; 17.491       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[13]      ;
; 17.275 ; 17.491       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[0]          ;
; 17.275 ; 17.491       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[10]         ;
; 17.275 ; 17.491       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[2]          ;
; 17.275 ; 17.491       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[5]          ;
; 17.275 ; 17.491       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[7]          ;
; 17.275 ; 17.491       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[8]          ;
; 17.275 ; 17.491       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[9]          ;
; 17.275 ; 17.491       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[0]     ;
; 17.275 ; 17.491       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[10]    ;
; 17.275 ; 17.491       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[1]     ;
; 17.275 ; 17.491       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[2]     ;
; 17.275 ; 17.491       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[3]     ;
; 17.275 ; 17.491       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[4]     ;
; 17.275 ; 17.491       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[5]     ;
; 17.275 ; 17.491       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[6]     ;
; 17.275 ; 17.491       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[7]     ;
; 17.275 ; 17.491       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[8]     ;
; 17.275 ; 17.491       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[9]     ;
; 17.275 ; 17.491       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[5]                                                                                                                                                  ;
; 17.280 ; 17.496       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                  ;
; 17.280 ; 17.496       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                  ;
; 17.280 ; 17.496       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                  ;
; 17.280 ; 17.496       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                  ;
; 17.280 ; 17.496       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                  ;
; 17.280 ; 17.496       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                  ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                   ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                        ; Clock Edge ; Target                                                                                             ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------+
; 17.587 ; 17.587       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.587 ; 17.587       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.587 ; 17.587       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.587 ; 17.587       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]                      ;
; 17.587 ; 17.587       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 17.589 ; 17.589       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.589 ; 17.589       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.598 ; 17.598       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.643 ; 17.643       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.652 ; 17.652       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.652 ; 17.652       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.654 ; 17.654       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.654 ; 17.654       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.654 ; 17.654       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.654 ; 17.654       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]                      ;
; 17.654 ; 17.654       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'                                                                                                                        ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------+
; Slack   ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                                                 ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------+
; 99.831  ; 99.831       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                    ;
; 99.831  ; 99.831       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|observablevcoout                          ;
; 99.837  ; 99.837       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 99.837  ; 99.837       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 99.888  ; 99.888       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                       ;
; 99.914  ; 99.914       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|inclk[0]                                  ;
; 99.920  ; 99.920       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 100.000 ; 100.000      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                       ;
; 100.000 ; 100.000      ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                       ;
; 100.079 ; 100.079      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 100.084 ; 100.084      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|inclk[0]                                  ;
; 100.112 ; 100.112      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                       ;
; 100.162 ; 100.162      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 100.162 ; 100.162      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 100.167 ; 100.167      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                    ;
; 100.167 ; 100.167      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|observablevcoout                          ;
; 196.000 ; 200.000      ; 4.000          ; Port Rate        ; FPGA_CLK ; Rise       ; FPGA_CLK                                                                               ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                             ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.654 ; 2.761 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.634 ; 2.741 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.634 ; 2.741 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.634 ; 2.741 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.648 ; 2.755 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.651 ; 2.758 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.649 ; 2.756 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.645 ; 2.752 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.654 ; 2.761 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.642 ; 2.749 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.648 ; 2.755 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.648 ; 2.755 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.648 ; 2.755 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.638 ; 2.745 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.637 ; 2.744 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.627 ; 2.734 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.637 ; 2.744 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; 7.229 ; 7.733 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; 3.759 ; 4.064 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; 3.884 ; 4.258 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; 5.036 ; 5.181 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; 5.083 ; 5.244 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; 7.229 ; 7.733 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; 6.474 ; 7.126 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; 3.725 ; 4.067 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; 3.526 ; 3.823 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; 5.197 ; 5.312 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; 4.791 ; 4.956 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; 6.474 ; 7.126 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; 5.915 ; 6.065 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; 5.696 ; 5.795 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; 3.191 ; 3.432 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 0.728 ; 0.838 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ;
; USB2_P        ; FPGA_CLK   ; 0.728 ; 0.838 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; -1.742 ; -1.850 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; -1.749 ; -1.857 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; -1.749 ; -1.857 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; -1.749 ; -1.857 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; -1.763 ; -1.871 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; -1.767 ; -1.875 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; -1.765 ; -1.873 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; -1.761 ; -1.869 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; -1.769 ; -1.877 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; -1.757 ; -1.865 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; -1.763 ; -1.871 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; -1.763 ; -1.871 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; -1.763 ; -1.871 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; -1.753 ; -1.861 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; -1.752 ; -1.860 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; -1.742 ; -1.850 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; -1.752 ; -1.860 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; -2.774 ; -3.064 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; -2.774 ; -3.064 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; -2.895 ; -3.252 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; -3.883 ; -3.967 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; -3.931 ; -4.029 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; -3.935 ; -3.946 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; -2.574 ; -2.854 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; -2.760 ; -3.085 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; -2.574 ; -2.854 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; -4.096 ; -4.210 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; -3.787 ; -3.942 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; -3.058 ; -3.369 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; -4.860 ; -4.999 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; -4.655 ; -4.742 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; -2.250 ; -2.477 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; -0.093 ; -0.204 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ;
; USB2_P        ; FPGA_CLK   ; -0.093 ; -0.204 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                     ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 4.590 ; 4.140 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 3.323 ; 3.087 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 3.313 ; 3.077 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 3.313 ; 3.077 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 3.313 ; 3.077 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 3.317 ; 3.081 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 3.326 ; 3.090 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 3.335 ; 3.099 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 4.590 ; 4.140 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 3.336 ; 3.100 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 3.346 ; 3.110 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 3.323 ; 3.087 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 4.578 ; 4.128 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 3.325 ; 3.089 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 4.578 ; 4.128 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 4.590 ; 4.140 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 3.335 ; 3.099 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 4.657 ; 4.209 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 3.607 ; 3.350 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 3.607 ; 3.350 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 3.607 ; 3.350 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 4.637 ; 4.189 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 4.633 ; 4.185 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 2.563 ; 2.365 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 3.507 ; 3.264 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 3.519 ; 3.276 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 3.639 ; 3.382 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 4.657 ; 4.209 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 3.633 ; 3.376 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 3.633 ; 3.376 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 3.623 ; 3.366 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 4.648 ; 4.200 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 3.614 ; 3.357 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 3.624 ; 3.367 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 3.312 ; 3.626 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 3.207 ; 3.432 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 3.312 ; 3.626 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 3.335 ; 3.099 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 3.345 ; 3.109 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 7.005 ; 7.188 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 4.148 ; 3.987 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 3.778 ; 3.512 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 6.084 ; 6.217 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 3.098 ; 3.364 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 9.081 ;       ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 8.810 ; Fall       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]        ; FPGA_CLK   ; 5.382 ; 5.730 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]       ; FPGA_CLK   ; 2.808 ; 2.778 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]       ; FPGA_CLK   ; 5.382 ; 5.730 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]       ; FPGA_CLK   ; 2.578 ; 2.528 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]       ; FPGA_CLK   ; 5.360 ; 5.708 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]        ; FPGA_CLK   ; 5.266 ; 5.559 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]       ; FPGA_CLK   ; 5.266 ; 5.559 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]       ; FPGA_CLK   ; 2.506 ; 2.389 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]       ; FPGA_CLK   ; 2.516 ; 2.399 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]       ; FPGA_CLK   ; 2.506 ; 2.389 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_HS          ; FPGA_CLK   ; 5.255 ; 5.548 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_R[*]        ; FPGA_CLK   ; 2.496 ; 2.379 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[0]       ; FPGA_CLK   ; 2.484 ; 2.367 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[1]       ; FPGA_CLK   ; 2.494 ; 2.377 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[2]       ; FPGA_CLK   ; 2.496 ; 2.379 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[3]       ; FPGA_CLK   ; 2.486 ; 2.369 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_VS          ; FPGA_CLK   ; 2.495 ; 2.378 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; USB2_N          ; FPGA_CLK   ; 4.020 ; 3.903 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ;
; USB2_P          ; FPGA_CLK   ; 4.020 ; 3.903 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                             ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 2.555 ; 2.323 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 2.565 ; 2.333 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 2.555 ; 2.323 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 2.555 ; 2.323 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 2.555 ; 2.323 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 2.559 ; 2.327 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 2.567 ; 2.335 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 2.577 ; 2.345 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 3.871 ; 3.422 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 2.578 ; 2.346 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 2.588 ; 2.356 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 2.565 ; 2.333 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 2.567 ; 2.335 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 2.567 ; 2.335 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 3.859 ; 3.410 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 3.871 ; 3.422 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 2.577 ; 2.345 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 1.847 ; 1.650 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 2.848 ; 2.595 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 2.848 ; 2.595 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 2.848 ; 2.595 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 3.920 ; 3.473 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 3.917 ; 3.470 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 1.847 ; 1.650 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 2.749 ; 2.510 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 2.760 ; 2.521 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 2.880 ; 2.627 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 3.940 ; 3.493 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 2.874 ; 2.621 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 2.874 ; 2.621 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 2.864 ; 2.611 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 3.931 ; 3.484 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 2.855 ; 2.602 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 2.865 ; 2.612 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 2.455 ; 2.677 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 2.455 ; 2.677 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 2.556 ; 2.864 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 2.577 ; 2.345 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 2.587 ; 2.355 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 6.227 ; 6.418 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 3.383 ; 3.228 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 3.014 ; 2.754 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 5.337 ; 5.478 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 2.357 ; 2.617 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 8.403 ;       ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 8.137 ; Fall       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]        ; FPGA_CLK   ; 1.861 ; 1.812 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]       ; FPGA_CLK   ; 2.089 ; 2.060 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]       ; FPGA_CLK   ; 4.664 ; 5.013 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]       ; FPGA_CLK   ; 1.861 ; 1.812 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]       ; FPGA_CLK   ; 4.643 ; 4.992 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]        ; FPGA_CLK   ; 1.786 ; 1.670 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]       ; FPGA_CLK   ; 4.547 ; 4.841 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]       ; FPGA_CLK   ; 1.786 ; 1.670 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]       ; FPGA_CLK   ; 1.796 ; 1.680 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]       ; FPGA_CLK   ; 1.786 ; 1.670 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_HS          ; FPGA_CLK   ; 4.536 ; 4.830 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_R[*]        ; FPGA_CLK   ; 1.765 ; 1.649 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[0]       ; FPGA_CLK   ; 1.765 ; 1.649 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[1]       ; FPGA_CLK   ; 1.775 ; 1.659 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[2]       ; FPGA_CLK   ; 1.776 ; 1.660 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[3]       ; FPGA_CLK   ; 1.766 ; 1.650 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_VS          ; FPGA_CLK   ; 1.775 ; 1.659 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; USB2_N          ; FPGA_CLK   ; 3.553 ; 3.437 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ;
; USB2_P          ; FPGA_CLK   ; 3.553 ; 3.437 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.631 ; 2.631 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.398 ; 3.398 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.398 ; 3.398 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.398 ; 3.398 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.488 ; 3.488 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.862 ; 3.862 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.847 ; 3.847 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.457 ; 3.457 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.484 ; 3.484 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.724 ; 3.724 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.388 ; 3.388 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.019 ; 3.019 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.019 ; 3.019 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.009 ; 3.009 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.641 ; 2.641 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.631 ; 2.631 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.641 ; 2.641 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.535 ; 3.159 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 5.361 ; 4.985 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ;
; USB2_P        ; FPGA_CLK   ; 5.361 ; 4.985 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                             ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.599 ; 1.599 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.336 ; 2.336 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.336 ; 2.336 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.336 ; 2.336 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.423 ; 2.423 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.782 ; 2.782 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.767 ; 2.767 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.393 ; 2.393 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.420 ; 2.420 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.649 ; 2.649 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.327 ; 2.327 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.972 ; 1.972 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.972 ; 1.972 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.962 ; 1.962 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 1.609 ; 1.609 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.599 ; 1.599 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.609 ; 1.609 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.684 ; 2.323 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 4.750 ; 4.389 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ;
; USB2_P        ; FPGA_CLK   ; 4.750 ; 4.389 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                            ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.462     ; 2.533     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.127     ; 3.198     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.127     ; 3.198     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.127     ; 3.198     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.249     ; 3.320     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.594     ; 3.665     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.594     ; 3.665     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.226     ; 3.297     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.264     ; 3.335     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.428     ; 3.499     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.137     ; 3.208     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.792     ; 2.863     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.792     ; 2.863     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.782     ; 2.853     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.472     ; 2.543     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.462     ; 2.533     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.472     ; 2.543     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.993     ; 3.369     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 4.782     ; 5.158     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ;
; USB2_P        ; FPGA_CLK   ; 4.782     ; 5.158     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                                    ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.505     ; 1.641     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.144     ; 2.280     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.144     ; 2.280     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.144     ; 2.280     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.261     ; 2.397     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.592     ; 2.728     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.593     ; 2.729     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.240     ; 2.376     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.276     ; 2.412     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.433     ; 2.569     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.155     ; 2.291     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.823     ; 1.959     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.823     ; 1.959     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.813     ; 1.949     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 1.515     ; 1.651     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.505     ; 1.641     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.515     ; 1.651     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.163     ; 2.524     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 4.195     ; 4.556     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ;
; USB2_P        ; FPGA_CLK   ; 4.195     ; 4.556     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+


---------------------------------------------
; Slow 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+--------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup Summary                                                                     ;
+-------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                         ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; -1.821 ; -67.826       ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; -0.232 ; -5.029        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 3.575  ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 14.165 ; 0.000         ;
+-------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold Summary                                                                      ;
+-------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                         ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------+--------+---------------+
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; -0.979 ; -36.949       ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.114  ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.185  ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.187  ; 0.000         ;
+-------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery Summary                                                                  ;
+-------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                         ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 9.263  ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 9.902  ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 14.743 ; 0.000         ;
+-------------------------------------------------------------------------------+--------+---------------+


+-------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal Summary                                                                  ;
+-------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                         ; Slack ; End Point TNS ;
+-------------------------------------------------------------------------------+-------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1.163 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 1.893 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 2.017 ; 0.000         ;
+-------------------------------------------------------------------------------+-------+---------------+


+--------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width Summary                                                       ;
+-------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                         ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.657  ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 8.557  ; 0.000         ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; 10.162 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.367 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]  ; 17.598 ; 0.000         ;
; FPGA_CLK                                                                      ; 99.405 ; 0.000         ;
+-------------------------------------------------------------------------------+--------+---------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                          ; To Node                                                                                                                                                                                            ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; -1.821 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[8]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[8]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.237     ; 0.542      ;
; -1.763 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[10]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[10]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.237     ; 0.484      ;
; -1.761 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[12]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[12]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.237     ; 0.482      ;
; -1.757 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[14]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[14]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.237     ; 0.478      ;
; -1.748 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[9]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.237     ; 0.469      ;
; -1.748 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[15]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[15]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.237     ; 0.469      ;
; -1.580 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[11]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[11]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.048     ; 0.490      ;
; -1.578 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[13]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.048     ; 0.488      ;
; -1.577 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[10]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[10]    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.049     ; 0.486      ;
; -1.574 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.073     ; 0.459      ;
; -1.572 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.073     ; 0.457      ;
; -1.556 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[0]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[0]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.052     ; 0.462      ;
; -1.547 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[7]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[7]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.048     ; 0.457      ;
; -1.544 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[2]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[2]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.052     ; 0.450      ;
; -1.543 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[1]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[1]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.052     ; 0.449      ;
; -1.540 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[3]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[3]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.052     ; 0.446      ;
; -1.501 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.073     ; 0.386      ;
; -1.500 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.073     ; 0.385      ;
; -1.499 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.073     ; 0.384      ;
; -1.499 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.073     ; 0.384      ;
; -1.499 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.073     ; 0.384      ;
; -1.497 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|bitStuffError                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[1]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.067     ; 0.388      ;
; -1.495 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[1] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.066     ; 0.387      ;
; -1.494 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXTimeOut                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[3]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.067     ; 0.385      ;
; -1.492 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CRCError                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[0]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.067     ; 0.383      ;
; -1.492 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[0] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.066     ; 0.384      ;
; -1.492 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|stallRxed                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[5]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.064     ; 0.386      ;
; -1.492 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXOverflow                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[2]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.064     ; 0.386      ;
; -1.491 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|NAKRxed                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[4]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.064     ; 0.385      ;
; -1.488 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[3]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[3]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.048     ; 0.398      ;
; -1.484 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInExtend[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInSTB[2]           ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.066     ; 0.376      ;
; -1.483 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.066     ; 0.375      ;
; -1.482 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.064     ; 0.376      ;
; -1.481 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.066     ; 0.373      ;
; -1.481 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|dataSequence                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[7]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.067     ; 0.372      ;
; -1.478 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|ACKRxed                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[6]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.064     ; 0.372      ;
; -1.476 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[8]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[8]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.048     ; 0.386      ;
; -1.476 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[0]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[0]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.049     ; 0.385      ;
; -1.476 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[5]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[5]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.049     ; 0.385      ;
; -1.475 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[6]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[6]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.048     ; 0.385      ;
; -1.474 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[4]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[4]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.049     ; 0.383      ;
; -1.474 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[2]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[2]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.048     ; 0.384      ;
; -1.473 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[1]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[1]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.048     ; 0.383      ;
; -1.473 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[9]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[9]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.048     ; 0.383      ;
; 7.661  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[0]                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 3.991      ;
; 7.661  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[1]                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 3.991      ;
; 7.661  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[2]                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 3.991      ;
; 7.661  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[3]                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 3.991      ;
; 7.661  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[4]                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 3.991      ;
; 7.661  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[5]                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 3.991      ;
; 7.661  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[6]                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 3.991      ;
; 7.661  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[7]                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 3.991      ;
; 7.664  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[7]                                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.076     ; 3.995      ;
; 7.664  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[9]                                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.076     ; 3.995      ;
; 7.664  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[10]                                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.076     ; 3.995      ;
; 7.664  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[8]                                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.076     ; 3.995      ;
; 7.732  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer2|count_reg[0]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.080     ; 3.923      ;
; 7.732  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer2|count_reg[1]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.080     ; 3.923      ;
; 7.732  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer2|count_reg[2]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.080     ; 3.923      ;
; 7.732  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer2|count_reg[3]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.080     ; 3.923      ;
; 7.732  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer2|count_reg[4]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.080     ; 3.923      ;
; 7.732  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer2|count_reg[5]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.080     ; 3.923      ;
; 7.732  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer2|count_reg[6]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.080     ; 3.923      ;
; 7.732  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer2|count_reg[7]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.080     ; 3.923      ;
; 7.752  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[5]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.898      ;
; 7.752  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[4]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.898      ;
; 7.752  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[2]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.898      ;
; 7.752  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[3]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.898      ;
; 7.752  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[1]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.898      ;
; 7.752  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[0]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.898      ;
; 7.777  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[5]                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.080     ; 3.878      ;
; 7.789  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[3]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.861      ;
; 7.789  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[6]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.861      ;
; 7.789  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[7]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.861      ;
; 7.789  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[4]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.861      ;
; 7.789  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[0]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.861      ;
; 7.789  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[1]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.861      ;
; 7.789  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[5]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.861      ;
; 7.789  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[2]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.861      ;
; 7.790  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.076     ; 3.869      ;
; 7.790  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[11]                                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.076     ; 3.869      ;
; 7.790  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.076     ; 3.869      ;
; 7.790  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.076     ; 3.869      ;
; 7.790  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[13]                                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.076     ; 3.869      ;
; 7.790  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[4]                                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.076     ; 3.869      ;
; 7.790  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.076     ; 3.869      ;
; 7.790  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]                                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.076     ; 3.869      ;
; 7.790  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]                                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.076     ; 3.869      ;
; 7.790  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[12]                                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.076     ; 3.869      ;
; 7.790  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.076     ; 3.869      ;
; 7.790  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.076     ; 3.869      ;
; 7.798  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[7]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.090     ; 3.847      ;
; 7.798  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[6]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.090     ; 3.847      ;
; 7.798  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[4]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.090     ; 3.847      ;
; 7.798  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[3]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.090     ; 3.847      ;
; 7.798  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[1]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.090     ; 3.847      ;
; 7.798  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[0]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.090     ; 3.847      ;
; 7.798  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[2]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.090     ; 3.847      ;
; 7.798  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[5]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.090     ; 3.847      ;
; 7.799  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[4]                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.080     ; 3.856      ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                               ; To Node                                                                                                                                                                                                          ; Launch Clock                                                                  ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -0.232 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.599      ; 0.717      ;
; -0.178 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.599      ; 0.663      ;
; -0.174 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.599      ; 0.659      ;
; -0.171 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate_reg1                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.598      ; 0.655      ;
; -0.164 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.600      ; 0.650      ;
; -0.157 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.599      ; 0.642      ;
; -0.154 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.599      ; 0.639      ;
; -0.151 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.603      ; 0.640      ;
; -0.147 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.598      ; 0.631      ;
; -0.146 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.599      ; 0.631      ;
; -0.145 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.599      ; 0.630      ;
; -0.145 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.599      ; 0.630      ;
; -0.144 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.604      ; 0.634      ;
; -0.143 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.604      ; 0.633      ;
; -0.141 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.599      ; 0.626      ;
; -0.140 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.603      ; 0.629      ;
; -0.140 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.604      ; 0.630      ;
; -0.139 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.611      ; 0.636      ;
; -0.139 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn_reg1                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.603      ; 0.628      ;
; -0.138 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.599      ; 0.623      ;
; -0.137 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.599      ; 0.622      ;
; -0.135 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg_reg1                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.598      ; 0.619      ;
; -0.135 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.603      ; 0.624      ;
; -0.134 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.603      ; 0.623      ;
; -0.133 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.603      ; 0.622      ;
; -0.131 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.603      ; 0.620      ;
; -0.131 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[0]                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.598      ; 0.615      ;
; -0.129 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.604      ; 0.619      ;
; -0.127 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.604      ; 0.617      ;
; -0.127 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.604      ; 0.617      ;
; -0.124 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.603      ; 0.613      ;
; -0.090 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.611      ; 0.587      ;
; -0.083 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.611      ; 0.580      ;
; -0.076 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.599      ; 0.561      ;
; -0.065 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.611      ; 0.562      ;
; -0.055 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.605      ; 0.546      ;
; -0.038 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.612      ; 0.536      ;
; -0.032 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.612      ; 0.530      ;
; -0.030 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.612      ; 0.528      ;
; -0.029 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.612      ; 0.527      ;
; 16.784 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.231     ; 3.805      ;
; 16.799 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.231     ; 3.790      ;
; 16.895 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.231     ; 3.694      ;
; 16.991 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[5]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.033     ; 3.796      ;
; 16.994 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.033     ; 3.793      ;
; 17.006 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[5]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.033     ; 3.781      ;
; 17.009 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.033     ; 3.778      ;
; 17.085 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[4]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.033     ; 3.702      ;
; 17.095 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.033     ; 3.692      ;
; 17.100 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[4]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.033     ; 3.687      ;
; 17.102 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[5]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.033     ; 3.685      ;
; 17.105 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.033     ; 3.682      ;
; 17.110 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.033     ; 3.677      ;
; 17.122 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[6]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.033     ; 3.665      ;
; 17.137 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[6]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.033     ; 3.650      ;
; 17.144 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.033     ; 3.643      ;
; 17.159 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.033     ; 3.628      ;
; 17.196 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[4]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.033     ; 3.591      ;
; 17.206 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.033     ; 3.581      ;
; 17.211 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.000            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.030     ; 3.579      ;
; 17.226 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.000            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.030     ; 3.564      ;
; 17.233 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[6]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.033     ; 3.554      ;
; 17.255 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.033     ; 3.532      ;
; 17.322 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.000            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.030     ; 3.468      ;
; 17.597 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[7]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.033     ; 3.190      ;
; 17.610 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.000 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.032     ; 3.178      ;
; 17.612 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[7]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.033     ; 3.175      ;
; 17.666 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.032     ; 3.122      ;
; 17.666 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.032     ; 3.122      ;
; 17.671 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFNearTime[15]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.038     ; 3.111      ;
; 17.679 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.000 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.032     ; 3.109      ;
; 17.686 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFNearTime[15]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.038     ; 3.096      ;
; 17.687 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.000 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.032     ; 3.101      ;
; 17.708 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[7]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.033     ; 3.079      ;
; 17.720 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.000 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.032     ; 3.068      ;
; 17.742 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.032     ; 3.046      ;
; 17.742 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.032     ; 3.046      ;
; 17.750 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.032     ; 3.038      ;
; 17.750 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.032     ; 3.038      ;
; 17.757 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.000 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.032     ; 3.031      ;
; 17.782 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFNearTime[15]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.038     ; 3.000      ;
; 17.788 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.000 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.032     ; 3.000      ;
; 17.792 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.032     ; 2.996      ;
; 17.792 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.032     ; 2.996      ;
; 17.814 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.032     ; 2.974      ;
; 17.814 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.032     ; 2.974      ;
; 17.823 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.010 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.032     ; 2.965      ;
; 17.824 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.032     ; 2.964      ;
; 17.846 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.032     ; 2.942      ;
; 17.846 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.032     ; 2.942      ;
; 17.870 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.033     ; 2.917      ;
; 17.885 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.033     ; 2.902      ;
; 17.887 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[7]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.000 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.032     ; 2.901      ;
; 17.899 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.010 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.032     ; 2.889      ;
; 17.900 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.032     ; 2.888      ;
; 17.907 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.010 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.032     ; 2.881      ;
; 17.908 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.032     ; 2.880      ;
; 17.941 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[8]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.033     ; 2.846      ;
; 17.949 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.010 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.032     ; 2.839      ;
; 17.950 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[0] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[4]              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.038     ; 2.832      ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                             ;
+-------+-------------------------+----------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node               ; To Node                                      ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------+----------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 3.575 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.129     ; 2.109      ;
; 3.663 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.129     ; 2.021      ;
; 3.666 ; SDRAM_ADDR[18]          ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.124     ; 2.023      ;
; 3.697 ; SDRAM_ADDR[16]          ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.121     ; 1.995      ;
; 3.706 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[0]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.138     ; 1.969      ;
; 3.706 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.138     ; 1.969      ;
; 3.706 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.138     ; 1.969      ;
; 3.706 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.138     ; 1.969      ;
; 3.730 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.131     ; 1.952      ;
; 3.750 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.132     ; 1.931      ;
; 3.750 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.132     ; 1.931      ;
; 3.764 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.138     ; 1.911      ;
; 3.794 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[0]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.138     ; 1.881      ;
; 3.794 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.138     ; 1.881      ;
; 3.794 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.138     ; 1.881      ;
; 3.794 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.138     ; 1.881      ;
; 3.797 ; SDRAM_ADDR[17]          ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.123     ; 1.893      ;
; 3.807 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_ras_n    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.136     ; 1.870      ;
; 3.818 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.131     ; 1.864      ;
; 3.838 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.132     ; 1.843      ;
; 3.838 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.132     ; 1.843      ;
; 3.852 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.138     ; 1.823      ;
; 3.863 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[9]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.126     ; 1.871      ;
; 3.864 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[0]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.126     ; 1.870      ;
; 3.867 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[8]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.126     ; 1.867      ;
; 3.877 ; SDRAM_ADDR[7]           ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.117     ; 1.819      ;
; 3.895 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_ras_n    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.136     ; 1.782      ;
; 3.901 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[1]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.126     ; 1.833      ;
; 3.936 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_ba[0]    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.136     ; 1.741      ;
; 3.942 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.130     ; 1.741      ;
; 3.956 ; SDRAM_ADDR[22]          ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.138     ; 1.719      ;
; 3.959 ; SDRAM_ADDR[12]          ; sdram_ctrl:sdram_controller|r_sdram_addr[0]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.136     ; 1.718      ;
; 4.005 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[15]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.121     ; 1.734      ;
; 4.006 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[13]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.121     ; 1.733      ;
; 4.007 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[10]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.121     ; 1.732      ;
; 4.024 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_ba[0]    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.136     ; 1.653      ;
; 4.030 ; SDRAM_ADDR[5]           ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.114     ; 1.669      ;
; 4.030 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.130     ; 1.653      ;
; 4.050 ; SDRAM_ADDR[20]          ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.122     ; 1.641      ;
; 4.077 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_ba[1]    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.138     ; 1.598      ;
; 4.094 ; SDRAM_ADDR[3]           ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.137     ; 1.582      ;
; 4.124 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.130     ; 1.559      ;
; 4.146 ; SDRAM_ADDR[19]          ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.124     ; 1.543      ;
; 4.165 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_ba[1]    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.138     ; 1.510      ;
; 4.175 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[2]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.121     ; 1.564      ;
; 4.175 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[5]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.121     ; 1.564      ;
; 4.175 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[7]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.122     ; 1.563      ;
; 4.176 ; SDRAM_READ_ENABLE       ; ram_do_reg[2]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.128     ; 1.556      ;
; 4.180 ; SDRAM_READ_ENABLE       ; ram_do_reg[3]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.127     ; 1.553      ;
; 4.180 ; SDRAM_READ_ENABLE       ; ram_do_reg[11]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.127     ; 1.553      ;
; 4.188 ; SDRAM_READ_ENABLE       ; ram_do_reg[7]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 1.547      ;
; 4.188 ; SDRAM_READ_ENABLE       ; ram_do_reg[15]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 1.547      ;
; 4.197 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[6]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.122     ; 1.541      ;
; 4.198 ; SDRAM_READ_ENABLE       ; ram_do_reg[6]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 1.537      ;
; 4.199 ; SDRAM_ADDR[6]           ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.116     ; 1.498      ;
; 4.201 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[4]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.122     ; 1.537      ;
; 4.202 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[14]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.122     ; 1.536      ;
; 4.212 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.130     ; 1.471      ;
; 4.241 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[11]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.122     ; 1.497      ;
; 4.248 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[12]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.122     ; 1.490      ;
; 4.266 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[3]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.122     ; 1.472      ;
; 4.286 ; SDRAM_ADDR[15]          ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.136     ; 1.391      ;
; 4.288 ; SDRAM_ADDR[1]           ; sdram_ctrl:sdram_controller|r_sdram_addr[0]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.137     ; 1.388      ;
; 4.303 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[15]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.107     ; 1.450      ;
; 4.304 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[13]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.107     ; 1.449      ;
; 4.305 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[10]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.107     ; 1.448      ;
; 4.306 ; SDRAM_ADDR[21]          ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.130     ; 1.377      ;
; 4.306 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[1]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.112     ; 1.442      ;
; 4.321 ; SDRAM_ADDR[8]           ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.131     ; 1.361      ;
; 4.330 ; SDRAM_ADDR[14]          ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.136     ; 1.347      ;
; 4.340 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[8]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.112     ; 1.408      ;
; 4.341 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[9]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.112     ; 1.407      ;
; 4.343 ; SDRAM_ADDR[13]          ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.136     ; 1.334      ;
; 4.352 ; SDRAM_ADDR[4]           ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.136     ; 1.325      ;
; 4.352 ; SDRAM_ADDR[2]           ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.136     ; 1.325      ;
; 4.385 ; SDRAM_ADDR[9]           ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.129     ; 1.299      ;
; 4.391 ; SDRAM_ADDR[10]          ; sdram_ctrl:sdram_controller|r_sdram_ba[0]    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.135     ; 1.287      ;
; 4.410 ; SDRAM_READ_ENABLE       ; ram_do_reg[29]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.129     ; 1.321      ;
; 4.410 ; SDRAM_READ_ENABLE       ; ram_do_reg[28]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.129     ; 1.321      ;
; 4.410 ; SDRAM_READ_ENABLE       ; ram_do_reg[21]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.129     ; 1.321      ;
; 4.410 ; SDRAM_READ_ENABLE       ; ram_do_reg[20]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.129     ; 1.321      ;
; 4.410 ; SDRAM_READ_ENABLE       ; ram_do_reg[18]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.129     ; 1.321      ;
; 4.410 ; SDRAM_READ_ENABLE       ; ram_do_reg[25]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.129     ; 1.321      ;
; 4.410 ; SDRAM_READ_ENABLE       ; ram_do_reg[19]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.129     ; 1.321      ;
; 4.410 ; SDRAM_READ_ENABLE       ; ram_do_reg[26]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.129     ; 1.321      ;
; 4.410 ; SDRAM_READ_ENABLE       ; ram_do_reg[16]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.129     ; 1.321      ;
; 4.410 ; SDRAM_READ_ENABLE       ; ram_do_reg[23]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.129     ; 1.321      ;
; 4.445 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[2]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.107     ; 1.308      ;
; 4.445 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[5]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.107     ; 1.308      ;
; 4.445 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[0]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.112     ; 1.303      ;
; 4.448 ; SDRAM_READ_ENABLE       ; ram_do_reg[30]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.129     ; 1.283      ;
; 4.448 ; SDRAM_READ_ENABLE       ; ram_do_reg[22]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.129     ; 1.283      ;
; 4.448 ; SDRAM_READ_ENABLE       ; ram_do_reg[31]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.129     ; 1.283      ;
; 4.448 ; SDRAM_READ_ENABLE       ; ram_do_reg[27]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.129     ; 1.283      ;
; 4.448 ; SDRAM_READ_ENABLE       ; ram_do_reg[24]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.129     ; 1.283      ;
; 4.448 ; SDRAM_READ_ENABLE       ; ram_do_reg[17]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.129     ; 1.283      ;
; 4.455 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[7]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.108     ; 1.297      ;
; 4.470 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[6]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.108     ; 1.282      ;
; 4.474 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[4]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.108     ; 1.278      ;
; 4.475 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[14]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.108     ; 1.277      ;
+-------+-------------------------+----------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                                                                                                                                          ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                ; To Node                                                                 ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 14.165 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.056     ; 3.340      ;
; 14.259 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.056     ; 3.246      ;
; 14.303 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.056     ; 3.202      ;
; 14.316 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.055     ; 3.190      ;
; 14.347 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.054     ; 3.160      ;
; 14.371 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.055     ; 3.135      ;
; 14.375 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.054     ; 3.132      ;
; 14.377 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.055     ; 3.129      ;
; 14.415 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.056     ; 3.090      ;
; 14.419 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.056     ; 3.086      ;
; 14.426 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.055     ; 3.080      ;
; 14.434 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.055     ; 3.072      ;
; 14.465 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.056     ; 3.040      ;
; 14.489 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.085     ; 2.987      ;
; 14.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.056     ; 3.003      ;
; 14.509 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.055     ; 2.997      ;
; 14.519 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.056     ; 2.986      ;
; 14.527 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.069     ; 2.965      ;
; 14.532 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.085     ; 2.944      ;
; 14.535 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.056     ; 2.970      ;
; 14.548 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.056     ; 2.957      ;
; 14.576 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.055     ; 2.930      ;
; 14.586 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.055     ; 2.920      ;
; 14.596 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.055     ; 2.910      ;
; 14.600 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.055     ; 2.906      ;
; 14.621 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.054     ; 2.886      ;
; 14.628 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.085     ; 2.848      ;
; 14.648 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.069     ; 2.844      ;
; 14.650 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.069     ; 2.842      ;
; 14.659 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.055     ; 2.847      ;
; 14.664 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.055     ; 2.842      ;
; 14.666 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.085     ; 2.810      ;
; 14.673 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.054     ; 2.834      ;
; 14.681 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.085     ; 2.795      ;
; 14.695 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.056     ; 2.810      ;
; 14.716 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.069     ; 2.776      ;
; 14.723 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.055     ; 2.783      ;
; 14.760 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.070     ; 2.731      ;
; 14.772 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.085     ; 2.704      ;
; 14.773 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.055     ; 2.733      ;
; 14.788 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.085     ; 2.688      ;
; 14.791 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.069     ; 2.701      ;
; 14.792 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.069     ; 2.700      ;
; 14.809 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.054     ; 2.698      ;
; 14.814 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.055     ; 2.692      ;
; 14.839 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.055     ; 2.667      ;
; 14.851 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.055     ; 2.655      ;
; 14.889 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.054     ; 2.618      ;
; 14.892 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.056     ; 2.613      ;
; 14.901 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.055     ; 2.605      ;
; 14.905 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.055     ; 2.601      ;
; 14.926 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.054     ; 2.581      ;
; 14.927 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.083     ; 2.551      ;
; 14.936 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.054     ; 2.571      ;
; 14.939 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.054     ; 2.568      ;
; 14.945 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.054     ; 2.562      ;
; 14.961 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.055     ; 2.545      ;
; 15.002 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.085     ; 2.474      ;
; 15.012 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.054     ; 2.495      ;
; 15.018 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.070     ; 2.473      ;
; 15.028 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.055     ; 2.478      ;
; 15.036 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.054     ; 2.471      ;
; 15.041 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.085     ; 2.435      ;
; 15.104 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.070     ; 2.387      ;
; 15.108 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.070     ; 2.383      ;
; 15.136 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.070     ; 2.355      ;
; 15.145 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.055     ; 2.361      ;
; 15.153 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.204     ; 2.251      ;
; 15.156 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.214     ; 2.238      ;
; 15.169 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.207     ; 2.232      ;
; 15.180 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.070     ; 2.311      ;
; 15.206 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.207     ; 2.195      ;
; 15.230 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.055     ; 2.276      ;
; 15.268 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.204     ; 2.136      ;
; 15.290 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.206     ; 2.112      ;
; 15.291 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.214     ; 2.103      ;
; 15.293 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.055     ; 2.213      ;
; 15.303 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.214     ; 2.091      ;
; 15.322 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.054     ; 2.185      ;
; 15.348 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.207     ; 2.053      ;
; 15.349 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.204     ; 2.055      ;
; 15.362 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.052     ; 2.147      ;
; 15.363 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.207     ; 2.038      ;
; 15.377 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.214     ; 2.017      ;
; 15.392 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.053     ; 2.116      ;
; 15.406 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.055     ; 2.100      ;
; 15.411 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.085     ; 2.065      ;
; 15.449 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 1.943      ;
; 15.450 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.054     ; 2.057      ;
; 15.479 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.055     ; 2.027      ;
; 15.486 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.052     ; 2.023      ;
; 15.493 ; sdram_reset_n_reg                                                                                                                                                        ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|hsync_in_reg  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.077     ; 2.038      ;
; 15.524 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 1.868      ;
; 15.533 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 1.859      ;
; 15.568 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.053     ; 1.940      ;
; 15.577 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.085     ; 1.899      ;
; 15.586 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.218     ; 1.804      ;
; 15.636 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.053     ; 1.872      ;
; 15.643 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.085     ; 1.833      ;
; 15.680 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.054     ; 1.827      ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                        ; To Node                                                                                                                                                                                                                                          ; Launch Clock                                                                  ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -0.979 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.243      ; 0.456      ;
; -0.977 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.248      ; 0.463      ;
; -0.976 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.248      ; 0.464      ;
; -0.974 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.248      ; 0.466      ;
; -0.968 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.248      ; 0.472      ;
; -0.958 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.249      ; 0.483      ;
; -0.947 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.237      ; 0.482      ;
; -0.942 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.249      ; 0.499      ;
; -0.942 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.249      ; 0.499      ;
; -0.940 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.242      ; 0.494      ;
; -0.938 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.237      ; 0.491      ;
; -0.938 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.242      ; 0.496      ;
; -0.937 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.242      ; 0.497      ;
; -0.936 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.236      ; 0.492      ;
; -0.935 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]                                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.242      ; 0.499      ;
; -0.934 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.249      ; 0.507      ;
; -0.933 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.242      ; 0.501      ;
; -0.932 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.242      ; 0.502      ;
; -0.932 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.242      ; 0.502      ;
; -0.930 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.242      ; 0.504      ;
; -0.929 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg_reg1                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.237      ; 0.500      ;
; -0.929 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.242      ; 0.505      ;
; -0.929 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.242      ; 0.505      ;
; -0.927 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.236      ; 0.501      ;
; -0.927 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.242      ; 0.507      ;
; -0.926 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.237      ; 0.503      ;
; -0.923 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1                                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.236      ; 0.505      ;
; -0.920 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]                                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.242      ; 0.514      ;
; -0.920 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.236      ; 0.508      ;
; -0.920 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn_reg1                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.242      ; 0.514      ;
; -0.913 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.236      ; 0.515      ;
; -0.905 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[0]                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.236      ; 0.523      ;
; -0.894 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.237      ; 0.535      ;
; -0.889 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.237      ; 0.540      ;
; -0.883 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.237      ; 0.546      ;
; -0.881 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.242      ; 0.553      ;
; -0.859 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate_reg1                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.236      ; 0.569      ;
; -0.852 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.237      ; 0.577      ;
; -0.851 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.237      ; 0.578      ;
; -0.824 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.237      ; 0.605      ;
; 0.183  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~porta_address_reg0 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.219      ; 0.506      ;
; 0.184  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[3]                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.219      ; 0.507      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[2]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[2]                                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|SIETxGnt            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|SIETxGnt                                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1110      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1110                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.10     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.10                                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.11     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.11                                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.00     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.00                                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.01     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.01                                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[0]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[0]                                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1]                                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[3]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[3]                                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[2]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[2]                                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxBitRdy             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxBitRdy                                             ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferInIndex[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferInIndex[0]                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferInIndex[1]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferInIndex[1]                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[0]     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[0]                                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[1]     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[1]                                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActive          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActive                                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1100      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1100                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[0]           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[0]                                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[1]           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[1]                                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[2]           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[2]                                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[3]           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[3]                                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxBits[1]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxBits[1]                                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxByteWEn            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxByteWEn                                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[7]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[7]                                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[6]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[6]                                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[5]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[5]                                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[4]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[4]                                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[3]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[3]                                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[2]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[2]                                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[1]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[1]                                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[0]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[0]                                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[1]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[1]                                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.010 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.010                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|rstCRC                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|rstCRC                                                    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1110   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1110                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC                                                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|loopEnd[0]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|loopEnd[0]                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|ready                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|ready                                                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1101   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1101                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|processRxByteRdy          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|processRxByteRdy                                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[0]              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[0]                                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1100  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1100                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1101  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1101                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0000  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0000                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketCPReady         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketCPReady                                         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000100                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000100                                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010100                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010100                                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010101                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010101                                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011011                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011011                                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011100                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011100                                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001110                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001110                                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|getPacketREn                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|getPacketREn                                                                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01101                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01101                                                                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[0]                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[0]                                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                                                                                                                                                                        ;
+-------+--------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                        ; To Node                                                                                                                                                                       ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 0.114 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_datain_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.277      ; 0.515      ;
; 0.156 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_datain_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.284      ; 0.564      ;
; 0.166 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_datain_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.284      ; 0.574      ;
; 0.166 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[3] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_datain_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.286      ; 0.576      ;
; 0.167 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[3] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_datain_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.274      ; 0.565      ;
; 0.170 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_datain_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.284      ; 0.578      ;
; 0.183 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_datain_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.277      ; 0.584      ;
; 0.187 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|buffer_select_reg                      ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|buffer_select_reg                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_hsync_reg                          ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_hsync_reg                                                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.307      ;
; 0.190 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_datain_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.284      ; 0.598      ;
; 0.193 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[118]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[117]                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.313      ;
; 0.193 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[114]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[113]                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.313      ;
; 0.193 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[85]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[84]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.312      ;
; 0.193 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[70]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[69]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.313      ;
; 0.193 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[68]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[67]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.313      ;
; 0.193 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[63]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[62]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.313      ;
; 0.193 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[55]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[54]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.313      ;
; 0.193 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[44]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[43]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.313      ;
; 0.193 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[40]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[39]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.313      ;
; 0.193 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[2]    ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[1]                                                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.313      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[121]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[120]                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[120]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[119]                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[119]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[118]                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[115]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[114]                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[113]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[112]                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[111]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[110]                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[110]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[109]                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[104]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[103]                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[100]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[99]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[98]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[97]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[97]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[96]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[96]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[95]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[76]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[75]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[74]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[73]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[73]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[72]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[71]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[70]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[66]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[65]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[62]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[61]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[59]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[58]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[58]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[57]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[56]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[55]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[45]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[44]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[42]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[41]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[41]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[40]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[37]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[36]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[18]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[17]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[17]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[16]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[13]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[12]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[10]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[9]                                                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; half_scandouble_enable_reg                                                                       ; half_scandouble_enable_reg                                                                                                                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[125]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[124]                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[1]    ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[0]                                                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[101]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[100]                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[90]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[89]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[89]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[88]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[83]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[82]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[82]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[81]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[60]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[59]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[46]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[45]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[39]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[38]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[33]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[32]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[29]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[28]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[28]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[27]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[27]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[26]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[9]    ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[8]                                                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[3]    ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[2]                                                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.196 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[105]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[104]                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.316      ;
; 0.196 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[91]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[90]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.315      ;
; 0.196 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[88]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[87]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.315      ;
; 0.196 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[81]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[80]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.315      ;
; 0.196 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[54]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[53]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.316      ;
; 0.196 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[53]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[52]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.316      ;
; 0.196 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[47]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[46]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.316      ;
; 0.196 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[34]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[33]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.315      ;
; 0.196 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[30]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[29]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.315      ;
; 0.196 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[24]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[23]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.315      ;
; 0.196 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[15]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[14]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.316      ;
; 0.196 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[14]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[13]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.316      ;
; 0.196 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[8]    ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[7]                                                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.316      ;
; 0.196 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[7]    ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[6]                                                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.316      ;
; 0.196 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[126]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[125]                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.316      ;
; 0.197 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[106]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[105]                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.317      ;
; 0.197 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[86]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[85]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.316      ;
; 0.197 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[48]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[47]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.317      ;
; 0.198 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[0]    ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_hsync_reg                                                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.318      ;
; 0.205 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[10]                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[10]                                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.325      ;
; 0.208 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[10]                 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[10]                                                                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.328      ;
; 0.220 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_datain_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.274      ; 0.618      ;
; 0.242 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_datain_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.277      ; 0.643      ;
; 0.243 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_datain_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.285      ; 0.652      ;
; 0.245 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_datain_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.274      ; 0.643      ;
; 0.261 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[108]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[107]                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.381      ;
; 0.261 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[77]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[76]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.381      ;
; 0.261 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[51]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[50]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.381      ;
; 0.261 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[23]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[22]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.380      ;
; 0.261 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[22]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[21]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.380      ;
; 0.262 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[35]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[34]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.381      ;
; 0.262 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[6]    ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[5]                                                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.382      ;
; 0.264 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_datain_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.273      ; 0.661      ;
; 0.264 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[93]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[92]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.384      ;
+-------+--------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                             ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                          ; To Node                                                                                                                                                                                                                                          ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 0.185 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[0]     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[0]                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.313      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[5]     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[5]                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.314      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[67]                                                                                                                                                     ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[67]                                                                                                                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[90]                                                                                                                                                     ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[90]                                                                                                                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[6]                                                                                                                                                      ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[6]                                                                                                                                                                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[66]                                                                                                                                                     ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[66]                                                                                                                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~porta_address_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.216      ; 0.507      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~porta_address_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.216      ; 0.507      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[120]                                                                                                                                                    ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[120]                                                                                                                                                                                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[0]                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.043      ; 0.314      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[0] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB[0]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.043      ; 0.314      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeInt                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeInt                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[3]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[3]                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.043      ; 0.314      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInt              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInt                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_count_reg[1]                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_count_reg[1]                                                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_count_reg[2]                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_count_reg[2]                                                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_count_reg[3]                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_count_reg[3]                                                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[1]                                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[1]                                                                                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[2]                                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[2]                                                                                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[3]                                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[3]                                                                                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[4]                                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[4]                                                                                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[5]                                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[5]                                                                                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[6]                                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[6]                                                                                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[7]                                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[7]                                                                                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[0]                                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[0]                                                                                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[5]                                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[5]                                                                                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                                                                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[9]                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[9]                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|state[0]                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|state[0]                                                                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|state[2]                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|state[2]                                                                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|skctl_reg[0]                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|skctl_reg[0]                                                                                                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[7]                                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[7]                                                                                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[0]                                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[0]                                                                                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[1]                                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[1]                                                                                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[2]                                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[2]                                                                                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[4]                                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[4]                                                                                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[5]                                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[5]                                                                                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[6]                                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[6]                                                                                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf1_reg[3]                                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf1_reg[3]                                                                                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf1_reg[0]                                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf1_reg[0]                                                                                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf1_reg[1]                                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf1_reg[1]                                                                                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf1_reg[2]                                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf1_reg[2]                                                                                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf1_reg[7]                                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf1_reg[7]                                                                                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[0]                                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[0]                                                                                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[1]                                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[1]                                                                                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[2]                                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[2]                                                                                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[3]                                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[3]                                                                                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[7]                                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[7]                                                                                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf2_reg[7]                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf2_reg[7]                                                                                                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf3_reg[1]                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf3_reg[1]                                                                                                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf3_reg[5]                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf3_reg[5]                                                                                                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf3_reg[4]                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf3_reg[4]                                                                                                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf3_reg[7]                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf3_reg[7]                                                                                                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf3_reg[6]                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf3_reg[6]                                                                                                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer3|delay_line:underflow0_delay|shift_reg[0]                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer3|delay_line:underflow0_delay|shift_reg[0]                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[7]                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[7]                                                                                                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[0]                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[0]                                                                                                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[1]                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[1]                                                                                                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[2]                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[2]                                                                                                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[3]                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[3]                                                                                                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[4]                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[4]                                                                                                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[5]                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[5]                                                                                                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[6]                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[6]                                                                                                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pl_reg[3]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pl_reg[3]                                                                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pl_reg[3]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pl_reg[3]                                                                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pl_reg[3]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pl_reg[3]                                                                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p3pf_reg[3]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p3pf_reg[3]                                                                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pf_reg[3]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pf_reg[3]                                                                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|nmist_reg[6]                                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|nmist_reg[6]                                                                                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[5]                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[5]                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|playfield_dma_start_shiftreg_reg[0]                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|playfield_dma_start_shiftreg_reg[0]                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|playfield_dma_start_shiftreg_reg[1]                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|playfield_dma_start_shiftreg_reg[1]                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[10]                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[10]                                                                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[3]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[3]                                                                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[0]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[0]                                                                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[1]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[1]                                                                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p3pf_reg[0]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p3pf_reg[0]                                                                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p2pf_reg[0]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p2pf_reg[0]                                                                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pl_reg[2]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pl_reg[2]                                                                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pf_reg[0]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pf_reg[0]                                                                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|irqst_reg[1]                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|irqst_reg[1]                                                                                                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p2pf_reg[1]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p2pf_reg[1]                                                                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pf_reg[1]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pf_reg[1]                                                                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pf_reg[1]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pf_reg[1]                                                                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p3pf_reg[1]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p3pf_reg[1]                                                                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[0]                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[0]                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|state[1]                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|state[1]                                                                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|cpu_fetch_real_reg                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|cpu_fetch_real_reg                                                                                                                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|irqst_reg[2]                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|irqst_reg[2]                                                                                                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pl_reg[2]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pl_reg[2]                                                                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pl_reg[2]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pl_reg[2]                                                                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[3]                                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[3]                                                                                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[2]                                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[2]                                                                                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                                                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                                                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_noise_filter:pokey_noise_filter3|out_reg                                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_noise_filter:pokey_noise_filter3|out_reg                                                                                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_noise_filter:pokey_noise_filter2|out_reg                                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_noise_filter:pokey_noise_filter2|out_reg                                                                                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_noise_filter:pokey_noise_filter2|out_reg                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_noise_filter:pokey_noise_filter2|out_reg                                                                                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_noise_filter:pokey_noise_filter1|out_reg                                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_noise_filter:pokey_noise_filter1|out_reg                                                                                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                             ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                 ; To Node                                                   ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 0.187 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sdram_ctrl:sdram_controller|r_wr_act                      ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|sdram_rdy                     ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_refr_act                    ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_rd_act                      ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_request_reg                                         ; sdram_request_reg                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_request_complete_reg                                ; sdram_request_complete_reg                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.194 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; ram_bena_reg[0]                                           ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.313      ;
; 0.195 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.314      ;
; 0.198 ; ram_bena_reg[1]                                           ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.317      ;
; 0.226 ; seq_reg[10]                                               ; seq_reg[11]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.345      ;
; 0.227 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.346      ;
; 0.234 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.353      ;
; 0.234 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.353      ;
; 0.258 ; sdram_ctrl:sdram_controller|r_rd_act                      ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.377      ;
; 0.277 ; seq_reg[9]                                                ; seq_reg[10]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.396      ;
; 0.278 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.398      ;
; 0.283 ; sdram_ctrl:sdram_controller|r_wr_act                      ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.403      ;
; 0.293 ; seq_reg[1]                                                ; seq_reg[2]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.412      ;
; 0.294 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.413      ;
; 0.295 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.414      ;
; 0.295 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.414      ;
; 0.296 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.415      ;
; 0.296 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.415      ;
; 0.296 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.415      ;
; 0.296 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.415      ;
; 0.296 ; sdram_ctrl:sdram_controller|r_refr_req                    ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.415      ;
; 0.297 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.416      ;
; 0.297 ; sdram_ctrl:sdram_controller|r_refr_req                    ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.416      ;
; 0.297 ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.416      ;
; 0.298 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.417      ;
; 0.301 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.420      ;
; 0.302 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.421      ;
; 0.321 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.440      ;
; 0.329 ; sdram_ctrl:sdram_controller|r_rd_act                      ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.448      ;
; 0.355 ; sdram_request_complete_reg                                ; sdram_request_reg                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.474      ;
; 0.364 ; seq_reg[11]                                               ; seq_reg[0]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.483      ;
; 0.367 ; seq_reg[2]                                                ; seq_reg[3]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.486      ;
; 0.367 ; seq_reg[3]                                                ; seq_reg[4]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.486      ;
; 0.367 ; sdram_ctrl:sdram_controller|r_refr_act                    ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.486      ;
; 0.398 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.517      ;
; 0.415 ; sdram_ctrl:sdram_controller|r_wr_act                      ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.534      ;
; 0.417 ; sdram_ctrl:sdram_controller|r_wr_act                      ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.536      ;
; 0.426 ; sdram_ctrl:sdram_controller|r_wr_act                      ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.546      ;
; 0.434 ; seq_reg[4]                                                ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.033      ; 0.551      ;
; 0.435 ; seq_reg[5]                                                ; seq_reg[6]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.554      ;
; 0.436 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.555      ;
; 0.443 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.562      ;
; 0.444 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.563      ;
; 0.445 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.564      ;
; 0.445 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.564      ;
; 0.449 ; sdram_ctrl:sdram_controller|r_refr_req                    ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.568      ;
; 0.451 ; seq_reg[6]                                                ; seq_reg[7]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.570      ;
; 0.453 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.572      ;
; 0.453 ; sdram_ctrl:sdram_controller|r_psel[0]                     ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.573      ;
; 0.454 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.573      ;
; 0.454 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.573      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.574      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.574      ;
; 0.456 ; seq_reg[4]                                                ; seq_reg[5]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.575      ;
; 0.456 ; sdram_ctrl:sdram_controller|r_refr_act                    ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.575      ;
; 0.456 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.575      ;
; 0.457 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.576      ;
; 0.457 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.576      ;
; 0.458 ; seq_reg[8]                                                ; seq_reg[9]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.577      ;
; 0.458 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.577      ;
; 0.458 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.577      ;
; 0.479 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.599      ;
; 0.499 ; sdram_ctrl:sdram_controller|r_refr_req                    ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.618      ;
; 0.506 ; sdram_ctrl:sdram_controller|r_psel[0]                     ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.627      ;
; 0.506 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.625      ;
; 0.507 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.626      ;
; 0.508 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.627      ;
; 0.509 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.628      ;
; 0.510 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.629      ;
; 0.511 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.630      ;
; 0.519 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.638      ;
; 0.520 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.639      ;
; 0.521 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.640      ;
; 0.521 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.640      ;
; 0.522 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.641      ;
; 0.523 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.643      ;
; 0.523 ; sdram_ctrl:sdram_controller|r_psel[0]                     ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.643      ;
; 0.523 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.642      ;
; 0.524 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.643      ;
; 0.524 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.643      ;
; 0.532 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.033      ; 0.649      ;
; 0.538 ; seq_reg[0]                                                ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.658      ;
; 0.547 ; seq_reg[7]                                                ; seq_reg[8]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.666      ;
; 0.548 ; seq_reg[11]                                               ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.668      ;
; 0.549 ; seq_reg[11]                                               ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.669      ;
; 0.554 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.674      ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                        ;
+-------+---------------------------------------+----------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                                                                                      ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+----------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[2]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 2.389      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[4]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 2.386      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[3]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 2.389      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.091     ; 2.381      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[7]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 2.389      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[30]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 2.385      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[21]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 2.383      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[21]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 2.383      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[21]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.091     ; 2.381      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[21]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 2.385      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[21]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 2.385      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[31]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 2.383      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[31]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 2.383      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[31]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 2.388      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[31]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 2.388      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[22]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 2.383      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[22]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 2.383      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[22]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.091     ; 2.381      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[27]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 2.385      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[12]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 2.388      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[6]                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 2.389      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[7]                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 2.389      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[7]                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 2.388      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[5]                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 2.389      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[13]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 2.385      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[13]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 2.388      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[13]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 2.385      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[19]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.091     ; 2.381      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[18]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.091     ; 2.381      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[20]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.091     ; 2.381      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[17]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.091     ; 2.381      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[4]                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 2.388      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[25]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 2.386      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[0]                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 2.389      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf3_reg[0]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.090     ; 2.382      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf3_reg[1]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.090     ; 2.382      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf3_reg[5]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.090     ; 2.382      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|serout_holding_reg[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.090     ; 2.382      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|serout_holding_reg[5] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.090     ; 2.382      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|serout_holding_reg[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.090     ; 2.382      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|serout_holding_reg[6] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.090     ; 2.382      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|serout_holding_reg[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.090     ; 2.382      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|serout_holding_reg[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.090     ; 2.382      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|serout_holding_reg[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.090     ; 2.382      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|serout_holding_reg[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.090     ; 2.382      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[8]                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 2.383      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[18]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 2.383      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[19]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 2.383      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[20]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 2.383      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[23]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 2.383      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[13]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 2.389      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[3]                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 2.388      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[5]                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 2.388      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[2]                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 2.388      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[20]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 2.383      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[20]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 2.385      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[14]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 2.389      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[11]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 2.385      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[11]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 2.385      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[18]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 2.383      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[18]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 2.388      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[18]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 2.388      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[29]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 2.385      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[19]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 2.383      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[4]                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 2.388      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[10]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 2.385      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[8]                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 2.385      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[8]                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 2.388      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[8]                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 2.388      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[8]                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 2.383      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[14]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 2.385      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[14]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 2.385      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[15]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 2.385      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[15]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 2.385      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pot0_reg[3]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 2.385      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[3]                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 2.388      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[5]                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 2.388      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[23]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 2.383      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[7]                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 2.388      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[7]                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 2.388      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[7]                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 2.388      ;
; 9.263 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pot0_reg[7]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 2.385      ;
; 9.264 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[11]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 2.382      ;
; 9.264 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[11]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 2.376      ;
; 9.264 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|state                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.096     ; 2.375      ;
; 9.264 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[21]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.093     ; 2.378      ;
; 9.264 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.090     ; 2.381      ;
; 9.264 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[29]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.097     ; 2.374      ;
; 9.264 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[29]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.091     ; 2.380      ;
; 9.264 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[16]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 2.382      ;
; 9.264 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[17]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 2.382      ;
; 9.264 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[18]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 2.382      ;
; 9.264 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[19]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 2.382      ;
; 9.264 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[20]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 2.382      ;
; 9.264 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[21]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 2.382      ;
; 9.264 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[22]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 2.382      ;
; 9.264 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[23]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 2.382      ;
; 9.264 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[24]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 2.382      ;
; 9.264 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[25]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 2.382      ;
; 9.264 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[25]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.093     ; 2.378      ;
+-------+---------------------------------------+----------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                          ;
+--------+------------------------+----------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node              ; To Node                                      ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------+----------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 9.902  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[0]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.137     ; 1.648      ;
; 9.902  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.137     ; 1.648      ;
; 9.902  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.137     ; 1.648      ;
; 9.902  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[3]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.139     ; 1.646      ;
; 9.903  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.138     ; 1.646      ;
; 9.904  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[0]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.191     ; 1.590      ;
; 9.904  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[3]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.193     ; 1.588      ;
; 9.904  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[1]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.191     ; 1.590      ;
; 9.904  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[2]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.191     ; 1.590      ;
; 9.904  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[6]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.138     ; 1.645      ;
; 9.905  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.192     ; 1.588      ;
; 9.906  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.192     ; 1.587      ;
; 9.906  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.142     ; 1.639      ;
; 9.907  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.144     ; 1.636      ;
; 9.908  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.196     ; 1.581      ;
; 9.909  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.198     ; 1.578      ;
; 9.912  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.136     ; 1.639      ;
; 9.912  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[11] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.136     ; 1.639      ;
; 9.912  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[12] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.136     ; 1.639      ;
; 9.912  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[1]    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.114     ; 1.661      ;
; 9.912  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.114     ; 1.661      ;
; 9.913  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[0]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.114     ; 1.660      ;
; 9.913  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.114     ; 1.660      ;
; 9.913  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.114     ; 1.660      ;
; 9.913  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.114     ; 1.660      ;
; 9.913  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[13] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.134     ; 1.640      ;
; 9.913  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[14] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.134     ; 1.640      ;
; 9.913  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[15] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.134     ; 1.640      ;
; 9.913  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[0]    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.112     ; 1.662      ;
; 9.914  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[12]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.190     ; 1.581      ;
; 9.914  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[11]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.190     ; 1.581      ;
; 9.914  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[10]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.190     ; 1.581      ;
; 9.915  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[13]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.188     ; 1.582      ;
; 9.915  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[14]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.188     ; 1.582      ;
; 9.915  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[15]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.188     ; 1.582      ;
; 9.917  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.130     ; 1.640      ;
; 9.917  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[9]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.136     ; 1.634      ;
; 9.918  ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.101     ; 1.715      ;
; 9.918  ; sdram_reset_ctrl_n_reg ; ram_do_reg[15]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.101     ; 1.715      ;
; 9.919  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[9]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.190     ; 1.576      ;
; 9.919  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[8]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.184     ; 1.582      ;
; 9.919  ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.101     ; 1.714      ;
; 9.926  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.107     ; 1.654      ;
; 9.926  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.108     ; 1.653      ;
; 9.926  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.108     ; 1.653      ;
; 9.927  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 1.655      ;
; 9.927  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.106     ; 1.654      ;
; 9.927  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.106     ; 1.654      ;
; 9.932  ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.699      ;
; 9.932  ; sdram_reset_ctrl_n_reg ; ram_do_reg[11]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.699      ;
; 9.941  ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 1.688      ;
; 9.941  ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 1.688      ;
; 9.941  ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 1.688      ;
; 9.941  ; sdram_reset_ctrl_n_reg ; ram_do_reg[20]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 1.688      ;
; 9.941  ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 1.688      ;
; 9.941  ; sdram_reset_ctrl_n_reg ; ram_do_reg[25]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 1.688      ;
; 9.941  ; sdram_reset_ctrl_n_reg ; ram_do_reg[19]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 1.688      ;
; 9.941  ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 1.688      ;
; 9.941  ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 1.688      ;
; 9.941  ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 1.688      ;
; 9.942  ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 1.687      ;
; 9.942  ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 1.687      ;
; 9.942  ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 1.687      ;
; 9.942  ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 1.687      ;
; 9.942  ; sdram_reset_ctrl_n_reg ; sdram_request_reg                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.100     ; 1.692      ;
; 9.942  ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.100     ; 1.692      ;
; 9.942  ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 1.687      ;
; 9.942  ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 1.687      ;
; 10.030 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.112     ; 1.545      ;
; 10.030 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.112     ; 1.545      ;
; 10.030 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.112     ; 1.545      ;
; 10.030 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.112     ; 1.545      ;
; 10.151 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.104     ; 1.479      ;
; 10.151 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 1.481      ;
; 10.151 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 1.481      ;
; 10.151 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 1.481      ;
; 10.151 ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 1.481      ;
; 10.153 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.484      ;
; 10.153 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.482      ;
; 10.153 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.482      ;
; 10.153 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.482      ;
; 10.153 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.482      ;
; 10.153 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.098     ; 1.483      ;
; 10.153 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_act         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.482      ;
; 10.153 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.482      ;
; 10.153 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.484      ;
; 10.153 ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.098     ; 1.483      ;
; 10.153 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.098     ; 1.483      ;
; 10.153 ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.484      ;
; 10.153 ; sdram_reset_ctrl_n_reg ; ram_di_reg[6]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.098     ; 1.483      ;
; 10.153 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.098     ; 1.483      ;
; 10.153 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.484      ;
; 10.153 ; sdram_reset_ctrl_n_reg ; ram_di_reg[11]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.098     ; 1.483      ;
; 10.153 ; sdram_reset_ctrl_n_reg ; ram_di_reg[12]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.098     ; 1.483      ;
; 10.153 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.484      ;
; 10.153 ; sdram_reset_ctrl_n_reg ; ram_di_reg[14]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.098     ; 1.483      ;
; 10.153 ; sdram_reset_ctrl_n_reg ; ram_di_reg[15]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.484      ;
; 10.153 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.482      ;
; 10.153 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[0]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.482      ;
; 10.153 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.482      ;
+--------+------------------------+----------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                        ;
+--------+-------------------+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node         ; To Node                                                                                         ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 14.743 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.126     ; 2.692      ;
; 14.743 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.126     ; 2.692      ;
; 14.762 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.111     ; 2.688      ;
; 14.763 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.110     ; 2.688      ;
; 14.767 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vsync_reg                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 2.697      ;
; 14.767 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.096     ; 2.698      ;
; 14.767 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.096     ; 2.698      ;
; 14.767 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.096     ; 2.698      ;
; 14.767 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.095     ; 2.699      ;
; 14.767 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.095     ; 2.699      ;
; 14.768 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|hsync_reg                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 2.696      ;
; 14.768 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.096     ; 2.697      ;
; 14.768 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 2.696      ;
; 14.768 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.097     ; 2.696      ;
; 14.981 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[66]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.540      ;
; 14.981 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[65]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.540      ;
; 14.981 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[64]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.540      ;
; 14.981 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[63]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.540      ;
; 14.981 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[62]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.540      ;
; 14.981 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[61]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.540      ;
; 14.981 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[60]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.540      ;
; 14.981 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[59]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.540      ;
; 14.981 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[58]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.540      ;
; 14.981 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[57]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.540      ;
; 14.981 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[56]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.540      ;
; 14.981 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[55]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.540      ;
; 14.981 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[54]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.540      ;
; 14.981 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[53]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.540      ;
; 14.981 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[52]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.540      ;
; 14.981 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[51]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.540      ;
; 14.981 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[50]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.540      ;
; 14.981 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[49]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.540      ;
; 14.981 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[48]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.540      ;
; 14.981 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[47]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.540      ;
; 14.981 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[46]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.540      ;
; 14.981 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[45]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.540      ;
; 14.981 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[44]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.540      ;
; 14.981 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[43]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.540      ;
; 14.981 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[42]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.540      ;
; 14.981 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[41]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.540      ;
; 14.981 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[40]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.540      ;
; 14.981 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[39]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.540      ;
; 14.981 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[38]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.540      ;
; 14.981 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[37]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.540      ;
; 14.981 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[36]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.540      ;
; 14.981 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[35]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.540      ;
; 14.981 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[21]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.088     ; 2.539      ;
; 14.981 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[20]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.088     ; 2.539      ;
; 14.981 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[19]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.088     ; 2.539      ;
; 14.981 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[18]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.088     ; 2.539      ;
; 14.981 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[17]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.088     ; 2.539      ;
; 14.981 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[16]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.088     ; 2.539      ;
; 14.981 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[15]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.088     ; 2.539      ;
; 14.981 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[14]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.088     ; 2.539      ;
; 14.981 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[13]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.088     ; 2.539      ;
; 14.981 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[12]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.088     ; 2.539      ;
; 14.981 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[11]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.088     ; 2.539      ;
; 14.981 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[10]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.088     ; 2.539      ;
; 14.981 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[9]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.088     ; 2.539      ;
; 14.981 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[8]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.088     ; 2.539      ;
; 14.981 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[7]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.088     ; 2.539      ;
; 14.981 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[6]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.088     ; 2.539      ;
; 14.982 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[123] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.539      ;
; 14.982 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[122] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.539      ;
; 14.982 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[121] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.539      ;
; 14.982 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[120] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.539      ;
; 14.982 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[119] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.539      ;
; 14.982 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[118] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.539      ;
; 14.982 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[117] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.539      ;
; 14.982 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[116] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.539      ;
; 14.982 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[115] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.539      ;
; 14.982 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[114] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.539      ;
; 14.982 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[113] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.539      ;
; 14.982 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[112] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.539      ;
; 14.982 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[111] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.539      ;
; 14.982 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[110] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.539      ;
; 14.982 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[109] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.539      ;
; 14.982 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[108] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.539      ;
; 14.982 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[107] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.539      ;
; 14.982 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[106] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.539      ;
; 14.982 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[105] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.539      ;
; 14.982 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[104] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.539      ;
; 14.982 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[103] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.539      ;
; 14.982 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[102] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.539      ;
; 14.982 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[101] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.539      ;
; 14.982 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[100] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.539      ;
; 14.982 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[99]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.539      ;
; 14.982 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[98]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.539      ;
; 14.982 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[97]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.539      ;
; 14.982 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[96]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.539      ;
; 14.982 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[95]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.539      ;
; 14.982 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[94]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.539      ;
; 14.982 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[93]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.087     ; 2.539      ;
; 14.982 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[92]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.086     ; 2.540      ;
; 14.982 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[91]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.086     ; 2.540      ;
; 14.982 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[90]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.086     ; 2.540      ;
; 14.982 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[89]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.086     ; 2.540      ;
; 14.982 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[88]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.086     ; 2.540      ;
; 14.982 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[87]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.086     ; 2.540      ;
; 14.982 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[86]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.086     ; 2.540      ;
+--------+-------------------+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                       ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                                   ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 1.163 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.350      ;
; 1.163 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.350      ;
; 1.163 ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.350      ;
; 1.163 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.350      ;
; 1.163 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.350      ;
; 1.163 ; sdram_reset_ctrl_n_reg ; ram_di_reg[15]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.350      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 1.350      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 1.350      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 1.350      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 1.350      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 1.350      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; seq_reg[5]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 1.350      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 1.350      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 1.350      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 1.350      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 1.350      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 1.350      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 1.350      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 1.350      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.351      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.351      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.351      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.351      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.351      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.351      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.351      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.351      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.351      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.351      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.351      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.351      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.351      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 1.350      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.349      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.349      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; ram_do_reg[5]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.349      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.349      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; ram_do_reg[13]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.349      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 1.350      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 1.350      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 1.350      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 1.350      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.349      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.349      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; ram_do_reg[9]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.349      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; ram_do_reg[14]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.349      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; ram_do_reg[12]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.349      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.349      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; ram_do_reg[8]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.349      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.349      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.351      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 1.350      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 1.350      ;
; 1.165 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.349      ;
; 1.165 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.349      ;
; 1.165 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.349      ;
; 1.165 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.349      ;
; 1.165 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.350      ;
; 1.165 ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.350      ;
; 1.165 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.350      ;
; 1.165 ; sdram_reset_ctrl_n_reg ; ram_di_reg[6]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.350      ;
; 1.165 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.350      ;
; 1.165 ; sdram_reset_ctrl_n_reg ; ram_di_reg[11]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.350      ;
; 1.165 ; sdram_reset_ctrl_n_reg ; ram_di_reg[12]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.350      ;
; 1.165 ; sdram_reset_ctrl_n_reg ; ram_di_reg[14]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.350      ;
; 1.165 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[0]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.349      ;
; 1.165 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.349      ;
; 1.165 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[1]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.349      ;
; 1.165 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.349      ;
; 1.167 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.076      ; 1.346      ;
; 1.167 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.348      ;
; 1.167 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.348      ;
; 1.167 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.348      ;
; 1.167 ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.348      ;
; 1.265 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.072      ; 1.414      ;
; 1.265 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.072      ; 1.414      ;
; 1.265 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.072      ; 1.414      ;
; 1.265 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.072      ; 1.414      ;
; 1.349 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.532      ;
; 1.349 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.532      ;
; 1.352 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.530      ;
; 1.352 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.530      ;
; 1.352 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.530      ;
; 1.352 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.530      ;
; 1.352 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.530      ;
; 1.352 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.530      ;
; 1.352 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.530      ;
; 1.352 ; sdram_reset_ctrl_n_reg ; ram_do_reg[20]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.530      ;
; 1.352 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.530      ;
; 1.352 ; sdram_reset_ctrl_n_reg ; ram_do_reg[25]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.530      ;
; 1.352 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.530      ;
; 1.352 ; sdram_reset_ctrl_n_reg ; ram_do_reg[19]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.530      ;
; 1.352 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.530      ;
; 1.352 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.530      ;
; 1.352 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.530      ;
; 1.352 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.075      ; 1.530      ;
; 1.354 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.077      ; 1.534      ;
; 1.354 ; sdram_reset_ctrl_n_reg ; ram_do_reg[11]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.077      ; 1.534      ;
; 1.363 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 1.545      ;
; 1.364 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 1.546      ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                         ;
+-------+---------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                                                                                                                                      ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 1.893 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[5]                                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.271      ; 2.269      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[0]                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.089      ; 2.268      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[1]                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.089      ; 2.268      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[2]                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.089      ; 2.268      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[3]                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.089      ; 2.268      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[4]                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.089      ; 2.268      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[5]                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.089      ; 2.268      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[6]                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.089      ; 2.268      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[7]                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.089      ; 2.268      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[8]                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.089      ; 2.268      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[9]                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.089      ; 2.268      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[10]                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.089      ; 2.268      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[11]                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.089      ; 2.268      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[12]                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.089      ; 2.268      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[23]                                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.090      ; 2.269      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[13]                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.089      ; 2.268      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[14]                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.089      ; 2.268      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[15]                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.089      ; 2.268      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[20]                                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.090      ; 2.269      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[19]                                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.090      ; 2.269      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|delay_line:stimer_delay|shift_reg[2]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 2.276      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|delay_line:stimer_delay|shift_reg[1]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 2.276      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|delay_line:stimer_delay|shift_reg[0]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 2.276      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audctl_reg[0]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.098      ; 2.277      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audctl_reg[3]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.098      ; 2.277      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audctl_reg[5]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.098      ; 2.277      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf2_reg[5]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 2.276      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf2_reg[0]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 2.276      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[0]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.098      ; 2.277      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf2_reg[1]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 2.276      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[1]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.098      ; 2.277      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf2_reg[2]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 2.276      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[2]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.098      ; 2.277      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf2_reg[3]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 2.276      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[3]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.098      ; 2.277      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf2_reg[4]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 2.276      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[4]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.098      ; 2.277      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[5]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.098      ; 2.277      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf2_reg[7]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 2.276      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf2_reg[6]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 2.276      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[6]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.098      ; 2.277      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[7]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.098      ; 2.277      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer2|delay_line:underflow0_delay|shift_reg[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.098      ; 2.277      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer2|delay_line:underflow0_delay|shift_reg[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.098      ; 2.277      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer2|delay_line:underflow0_delay|shift_reg[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.098      ; 2.277      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[0]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.098      ; 2.277      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf3_reg[2]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 2.276      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[1]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.098      ; 2.277      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[2]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.098      ; 2.277      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf3_reg[3]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 2.276      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[3]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.098      ; 2.277      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf3_reg[7]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 2.276      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf3_reg[4]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 2.276      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[4]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.098      ; 2.277      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[5]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.098      ; 2.277      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[6]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.098      ; 2.277      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[7]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.098      ; 2.277      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer3|delay_line:underflow0_delay|shift_reg[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.098      ; 2.277      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer3|delay_line:underflow0_delay|shift_reg[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.098      ; 2.277      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|serin_bitcount_reg[1]                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 2.276      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|serin_bitcount_reg[2]                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 2.276      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|serin_bitcount_reg[0]                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 2.276      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|skctl_reg[2]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 2.276      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|skctl_reg[3]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 2.276      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audctl_reg[4]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.098      ; 2.277      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[0]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 2.276      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[0]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 2.276      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[2]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 2.276      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[1]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 2.276      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[1]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 2.276      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[2]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 2.276      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[3]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 2.276      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[3]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 2.276      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[4]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 2.276      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[4]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 2.276      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[6]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 2.276      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[5]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 2.276      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[5]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 2.276      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[6]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 2.276      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf0_reg[7]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 2.276      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[7]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 2.276      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 2.276      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 2.276      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.098      ; 2.277      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[0]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.099      ; 2.278      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[1]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.099      ; 2.278      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[2]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.099      ; 2.278      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[3]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.099      ; 2.278      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|audf1_reg[4]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 2.276      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[4]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.099      ; 2.278      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[5]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.099      ; 2.278      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[6]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.099      ; 2.278      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[7]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.099      ; 2.278      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer1|delay_line:underflow0_delay|shift_reg[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.099      ; 2.278      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer1|delay_line:underflow0_delay|shift_reg[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.099      ; 2.278      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|pokey_countdown_timer:timer1|delay_line:underflow0_delay|shift_reg[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.098      ; 2.277      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|skctl_reg[7]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 2.276      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|delay_line:serout_clock_delay|shift_reg[1]                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 2.276      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|delay_line:serout_clock_delay|shift_reg[0]                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 2.276      ;
; 2.074 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_device:pokey1|pokey:pokey1|serout_clock_reg                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 2.276      ;
+-------+---------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                        ;
+-------+-------------------+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node         ; To Node                                                                                         ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 2.017 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|buffer_select_reg                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.104      ; 2.225      ;
; 2.017 ; sdram_reset_n_reg ; half_scandouble_enable_reg                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.104      ; 2.225      ;
; 2.017 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 2.224      ;
; 2.017 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[1]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 2.224      ;
; 2.017 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[2]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 2.224      ;
; 2.017 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[3]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 2.224      ;
; 2.017 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[4]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 2.224      ;
; 2.017 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[5]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 2.224      ;
; 2.017 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[6]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 2.224      ;
; 2.017 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[7]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 2.224      ;
; 2.017 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[8]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 2.224      ;
; 2.017 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[9]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 2.224      ;
; 2.017 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[10]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 2.224      ;
; 2.017 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[127] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.105      ; 2.226      ;
; 2.017 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[126] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.105      ; 2.226      ;
; 2.017 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[125] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.105      ; 2.226      ;
; 2.017 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[124] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.105      ; 2.226      ;
; 2.017 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[4]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.105      ; 2.226      ;
; 2.017 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[3]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.105      ; 2.226      ;
; 2.017 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[2]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.105      ; 2.226      ;
; 2.017 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[1]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.105      ; 2.226      ;
; 2.017 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[0]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.105      ; 2.226      ;
; 2.017 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_hsync_reg                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.105      ; 2.226      ;
; 2.017 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.102      ; 2.223      ;
; 2.017 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.104      ; 2.225      ;
; 2.017 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.104      ; 2.225      ;
; 2.017 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.104      ; 2.225      ;
; 2.017 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.104      ; 2.225      ;
; 2.017 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.104      ; 2.225      ;
; 2.017 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.104      ; 2.225      ;
; 2.017 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.104      ; 2.225      ;
; 2.018 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 2.225      ;
; 2.018 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[2]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 2.225      ;
; 2.018 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[3]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 2.225      ;
; 2.018 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[4]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 2.225      ;
; 2.018 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[5]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 2.225      ;
; 2.018 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[6]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 2.225      ;
; 2.018 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[7]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 2.225      ;
; 2.018 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[8]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 2.225      ;
; 2.018 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[9]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 2.225      ;
; 2.018 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[10]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 2.225      ;
; 2.018 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 2.225      ;
; 2.037 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[123] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.094      ; 2.235      ;
; 2.037 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[122] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.094      ; 2.235      ;
; 2.037 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[121] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.094      ; 2.235      ;
; 2.037 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[120] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.094      ; 2.235      ;
; 2.037 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[119] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.094      ; 2.235      ;
; 2.037 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[118] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.094      ; 2.235      ;
; 2.037 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[117] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.094      ; 2.235      ;
; 2.037 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[116] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.094      ; 2.235      ;
; 2.037 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[115] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.094      ; 2.235      ;
; 2.037 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[114] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.094      ; 2.235      ;
; 2.037 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[113] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.094      ; 2.235      ;
; 2.037 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[112] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.094      ; 2.235      ;
; 2.037 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[111] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.094      ; 2.235      ;
; 2.037 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[110] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.094      ; 2.235      ;
; 2.037 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[109] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.094      ; 2.235      ;
; 2.037 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[108] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.094      ; 2.235      ;
; 2.037 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[107] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.094      ; 2.235      ;
; 2.037 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[106] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.094      ; 2.235      ;
; 2.037 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[105] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.094      ; 2.235      ;
; 2.037 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[104] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.094      ; 2.235      ;
; 2.037 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[103] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.094      ; 2.235      ;
; 2.037 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[102] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.094      ; 2.235      ;
; 2.037 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[101] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.094      ; 2.235      ;
; 2.037 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[100] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.094      ; 2.235      ;
; 2.037 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[99]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.094      ; 2.235      ;
; 2.037 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[98]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.094      ; 2.235      ;
; 2.037 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[97]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.094      ; 2.235      ;
; 2.037 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[96]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.094      ; 2.235      ;
; 2.037 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[95]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.094      ; 2.235      ;
; 2.037 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[94]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.094      ; 2.235      ;
; 2.037 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[93]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.094      ; 2.235      ;
; 2.037 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[92]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.094      ; 2.235      ;
; 2.037 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[91]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.094      ; 2.235      ;
; 2.037 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[90]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.094      ; 2.235      ;
; 2.037 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[89]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.094      ; 2.235      ;
; 2.037 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[88]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.094      ; 2.235      ;
; 2.037 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[87]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.094      ; 2.235      ;
; 2.037 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[86]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.094      ; 2.235      ;
; 2.037 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[85]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.094      ; 2.235      ;
; 2.037 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[84]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.094      ; 2.235      ;
; 2.037 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[83]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.094      ; 2.235      ;
; 2.037 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[82]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.094      ; 2.235      ;
; 2.037 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[81]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.094      ; 2.235      ;
; 2.037 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[80]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.094      ; 2.235      ;
; 2.037 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[79]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.094      ; 2.235      ;
; 2.037 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[78]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.094      ; 2.235      ;
; 2.037 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[77]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.094      ; 2.235      ;
; 2.037 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[76]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.095      ; 2.236      ;
; 2.037 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[75]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.095      ; 2.236      ;
; 2.037 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[74]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.095      ; 2.236      ;
; 2.037 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[73]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.095      ; 2.236      ;
; 2.037 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[72]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.095      ; 2.236      ;
; 2.037 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[71]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.095      ; 2.236      ;
; 2.037 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[70]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.095      ; 2.236      ;
; 2.037 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[69]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.095      ; 2.236      ;
; 2.037 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[68]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.095      ; 2.236      ;
; 2.037 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[67]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.095      ; 2.236      ;
; 2.037 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[50]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.094      ; 2.235      ;
+-------+-------------------+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                         ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                         ; Clock Edge ; Target                                                    ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; 5.657 ; 5.873        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[11]                                            ;
; 5.657 ; 5.873        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[3]                                             ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[0]                                             ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[1]                                             ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[8]                                             ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[9]                                             ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[0]                                             ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[10]                                            ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[12]                                            ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[13]                                            ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[14]                                            ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[17]                                            ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[1]                                             ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[22]                                            ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[24]                                            ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[27]                                            ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[2]                                             ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[30]                                            ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[31]                                            ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[4]                                             ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[5]                                             ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[6]                                             ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[8]                                             ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[9]                                             ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel[0]                     ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_req                    ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_complete_reg                                ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_reg                                         ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[0]                                                ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[10]                                               ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[11]                                               ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[1]                                                ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[2]                                                ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[3]                                                ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[4]                                                ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[5]                                                ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[6]                                                ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[7]                                                ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[8]                                                ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[9]                                                ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[0]                                           ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[1]                                           ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[10]                                            ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[11]                                            ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[12]                                            ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[13]                                            ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[14]                                            ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[15]                                            ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[2]                                             ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[3]                                             ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[4]                                             ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[5]                                             ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[6]                                             ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[7]                                             ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[15]                                            ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[16]                                            ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[18]                                            ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[19]                                            ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[20]                                            ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[21]                                            ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[23]                                            ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[25]                                            ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[26]                                            ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[28]                                            ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[29]                                            ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[7]                                             ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_act                      ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_reg                      ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_act                    ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_act                      ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_reg                      ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|sdram_rdy                     ;
; 5.662 ; 5.817        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[5]                   ;
; 5.663 ; 5.818        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[0]                   ;
; 5.663 ; 5.818        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[13]                  ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                              ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                         ; Clock Edge ; Target                                                                                                                                                                         ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 8.557 ; 8.787        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_address_reg0 ;
; 8.557 ; 8.787        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg       ;
; 8.557 ; 8.787        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_address_reg0 ;
; 8.557 ; 8.787        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg       ;
; 8.559 ; 8.789        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 8.559 ; 8.789        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_datain_reg0  ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_address_reg0 ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg       ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_address_reg0 ;
; 8.560 ; 8.790        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg       ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_datain_reg0  ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[100]                                                                                ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[101]                                                                                ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[102]                                                                                ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[103]                                                                                ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[104]                                                                                ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[105]                                                                                ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[106]                                                                                ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[107]                                                                                ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[108]                                                                                ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[109]                                                                                ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[110]                                                                                ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[111]                                                                                ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[112]                                                                                ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[113]                                                                                ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[114]                                                                                ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[115]                                                                                ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[116]                                                                                ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[117]                                                                                ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[118]                                                                                ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[119]                                                                                ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[120]                                                                                ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[121]                                                                                ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[122]                                                                                ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[123]                                                                                ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[22]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[23]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[24]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[25]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[26]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[27]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[28]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[29]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[30]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[31]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[32]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[33]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[34]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[35]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[36]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[37]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[38]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[39]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[40]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[41]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[42]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[43]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[44]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[45]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[46]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[47]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[48]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[49]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[50]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[5]                                                                                  ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[67]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[68]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[69]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[70]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[71]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[72]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[73]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[74]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[75]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[76]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[77]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[78]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[79]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[80]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[81]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[82]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[83]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[84]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[85]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[86]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[87]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[88]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[89]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[90]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[91]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[92]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[93]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[94]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[95]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[96]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[97]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[98]                                                                                 ;
; 8.595 ; 8.811        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[99]                                                                                 ;
; 8.596 ; 8.812        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[10]                                                                                 ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                 ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                               ; Clock Edge ; Target                                                                                                                                                                                                                                           ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 10.162 ; 10.392       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~porta_address_reg0 ;
; 10.162 ; 10.392       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~porta_we_reg       ;
; 10.164 ; 10.394       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 10.165 ; 10.395       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~portb_address_reg0 ;
; 10.165 ; 10.395       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]                                                                             ;
; 10.165 ; 10.395       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]                                                                             ;
; 10.165 ; 10.395       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]                                                                             ;
; 10.165 ; 10.395       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]                                                                             ;
; 10.165 ; 10.395       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]                                                                             ;
; 10.165 ; 10.395       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]                                                                             ;
; 10.165 ; 10.395       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]                                                                             ;
; 10.165 ; 10.395       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]                                                                             ;
; 10.200 ; 10.384       ; 0.184          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]                                                                   ;
; 10.201 ; 10.417       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]                                            ;
; 10.201 ; 10.417       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[1]                                            ;
; 10.201 ; 10.417       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[2]                                            ;
; 10.201 ; 10.417       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[3]                                            ;
; 10.201 ; 10.417       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[4]                                            ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[1]                                                                                                 ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[2]                                                                                                 ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.001                                                     ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.010                                                     ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.011                                                     ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.100                                                     ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|SOFCntlGnt                                                                ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|directCntlGnt                                                             ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|muxCntl.00                                                                ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|muxCntl.10                                                                ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|sendPacketGnt                                                             ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[10]                                                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[11]                                                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[12]                                                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]                                                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[14]                                                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[15]                                                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1]                                                                   ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2]                                                                   ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3]                                                                   ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[4]                                                                   ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[5]                                                                   ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[6]                                                                   ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[7]                                                                   ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[8]                                                                   ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9]                                                                   ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[1]                                                                              ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[7]                                                                              ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1                                                            ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqExtend[0]                                                    ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqExtend[1]                                                    ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqExtend[2]                                                    ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol                                                            ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1                                                       ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate                                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn                                                                   ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1                                                              ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn                                                              ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1                                                         ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq                                                                ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1                                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|ACKRxed                                                                               ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01010                                                                ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01011                                                                ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01111                                                                ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|NAKRxed                                                                               ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[0]                                                                          ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[1]                                                                          ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[2]                                                                          ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[3]                                                                          ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[4]                                                                          ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[5]                                                                          ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[6]                                                                          ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[7]                                                                          ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[0]                                                                       ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[1]                                                                       ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[2]                                                                       ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[3]                                                                       ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[4]                                                                       ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[5]                                                                       ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[6]                                                                       ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[7]                                                                       ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[2]                                                                             ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[3]                                                                             ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[4]                                                                             ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[5]                                                                             ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[6]                                                                             ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[7]                                                                             ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXOverflow                                                                            ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXPacketRdy                                                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[0]                                                                              ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[1]                                                                              ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[2]                                                                              ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[3]                                                                              ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|SIERxTimeOutEn                                                                        ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|stallRxed                                                                             ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000001                                                   ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000010                                                   ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000011                                                   ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001001                                                   ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001010                                                   ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001100                                                   ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                 ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                         ; Clock Edge ; Target                                                                                                                                                                                                                                           ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|generic_ram_infer:freezer_bram|altsyncram:ram_block_rtl_0|altsyncram_jc41:auto_generated|ram_block1a0~porta_address_reg0       ;
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|generic_ram_infer:freezer_bram|altsyncram:ram_block_rtl_0|altsyncram_jc41:auto_generated|ram_block1a0~porta_we_reg             ;
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a10~porta_address_reg0                                                                                                                                            ;
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a11~porta_address_reg0                                                                                                                                            ;
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a12~porta_address_reg0                                                                                                                                            ;
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a13~porta_address_reg0                                                                                                                                            ;
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a15~porta_address_reg0                                                                                                                                            ;
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a18~porta_address_reg0                                                                                                                                            ;
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a20~porta_address_reg0                                                                                                                                            ;
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a21~porta_address_reg0                                                                                                                                            ;
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a22~porta_address_reg0                                                                                                                                            ;
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a25~porta_address_reg0                                                                                                                                            ;
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a27~porta_address_reg0                                                                                                                                            ;
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a28~porta_address_reg0                                                                                                                                            ;
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a29~porta_address_reg0                                                                                                                                            ;
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a31~porta_address_reg0                                                                                                                                            ;
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a3~porta_address_reg0                                                                                                                                             ;
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a4~porta_address_reg0                                                                                                                                             ;
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a6~porta_address_reg0                                                                                                                                             ;
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a7~porta_address_reg0                                                                                                                                             ;
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a3~porta_address_reg0                                                                                                                 ;
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a3~porta_we_reg                                                                                                                       ;
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a3~porta_address_reg0                                                                                                                 ;
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a3~porta_we_reg                                                                                                                       ;
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                ;
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                      ;
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a3~porta_address_reg0                                                                                                                ;
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a3~porta_we_reg                                                                                                                      ;
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a3~porta_address_reg0                                                                                                                  ;
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a3~porta_we_reg                                                                                                                        ;
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~porta_address_reg0 ;
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~porta_we_reg       ;
; 17.368 ; 17.598       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                                             ;
; 17.368 ; 17.598       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a14~porta_address_reg0                                                                                                                                            ;
; 17.368 ; 17.598       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a16~porta_address_reg0                                                                                                                                            ;
; 17.368 ; 17.598       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a19~porta_address_reg0                                                                                                                                            ;
; 17.368 ; 17.598       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a23~porta_address_reg0                                                                                                                                            ;
; 17.368 ; 17.598       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a24~porta_address_reg0                                                                                                                                            ;
; 17.368 ; 17.598       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a26~porta_address_reg0                                                                                                                                            ;
; 17.368 ; 17.598       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a8~porta_address_reg0                                                                                                                                             ;
; 17.368 ; 17.598       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a9~porta_address_reg0                                                                                                                                             ;
; 17.368 ; 17.598       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                 ;
; 17.368 ; 17.598       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                       ;
; 17.368 ; 17.598       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                 ;
; 17.368 ; 17.598       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                       ;
; 17.368 ; 17.598       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                  ;
; 17.368 ; 17.598       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                        ;
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|generic_ram_infer:freezer_bram|altsyncram:ram_block_rtl_0|altsyncram_jc41:auto_generated|ram_block1a0~porta_datain_reg0        ;
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a17~porta_address_reg0                                                                                                                                            ;
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a30~porta_address_reg0                                                                                                                                            ;
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a3~porta_datain_reg0                                                                                                                  ;
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a3~porta_datain_reg0                                                                                                                  ;
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                 ;
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a3~porta_datain_reg0                                                                                                                 ;
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a3~porta_datain_reg0                                                                                                                   ;
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a1~porta_address_reg0                                                                                                                                             ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a2~porta_address_reg0                                                                                                                                             ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ec71:auto_generated|ram_block1a5~porta_address_reg0                                                                                                                                             ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                  ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                  ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                   ;
; 17.373 ; 17.603       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~portb_address_reg0 ;
; 17.373 ; 17.603       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]                                                                             ;
; 17.373 ; 17.603       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]                                                                             ;
; 17.373 ; 17.603       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]                                                                             ;
; 17.373 ; 17.603       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]                                                                             ;
; 17.373 ; 17.603       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]                                                                             ;
; 17.373 ; 17.603       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]                                                                             ;
; 17.373 ; 17.603       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]                                                                             ;
; 17.373 ; 17.603       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]                                                                             ;
; 17.388 ; 17.604       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[11]                                                                                                                                                                                                                                   ;
; 17.388 ; 17.604       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[19]                                                                                                                                                                                                                                   ;
; 17.389 ; 17.605       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[0]                                                                                                                                                                                                                                    ;
; 17.389 ; 17.605       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[10]                                                                                                                                                                                                                                   ;
; 17.389 ; 17.605       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[12]                                                                                                                                                                                                                                   ;
; 17.389 ; 17.605       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[13]                                                                                                                                                                                                                                   ;
; 17.389 ; 17.605       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[14]                                                                                                                                                                                                                                   ;
; 17.389 ; 17.605       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[15]                                                                                                                                                                                                                                   ;
; 17.389 ; 17.605       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[16]                                                                                                                                                                                                                                   ;
; 17.389 ; 17.605       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[17]                                                                                                                                                                                                                                   ;
; 17.389 ; 17.605       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[18]                                                                                                                                                                                                                                   ;
; 17.389 ; 17.605       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[1]                                                                                                                                                                                                                                    ;
; 17.389 ; 17.605       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[20]                                                                                                                                                                                                                                   ;
; 17.389 ; 17.605       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[21]                                                                                                                                                                                                                                   ;
; 17.389 ; 17.605       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[22]                                                                                                                                                                                                                                   ;
; 17.389 ; 17.605       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[2]                                                                                                                                                                                                                                    ;
; 17.389 ; 17.605       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[3]                                                                                                                                                                                                                                    ;
; 17.389 ; 17.605       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[4]                                                                                                                                                                                                                                    ;
; 17.389 ; 17.605       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[8]                                                                                                                                                                                                                                    ;
; 17.389 ; 17.605       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[9]                                                                                                                                                                                                                                    ;
; 17.389 ; 17.605       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_DI[10]                                                                                                                                                                                                                                     ;
; 17.389 ; 17.605       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_DI[11]                                                                                                                                                                                                                                     ;
; 17.389 ; 17.605       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_DI[12]                                                                                                                                                                                                                                     ;
; 17.389 ; 17.605       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_DI[13]                                                                                                                                                                                                                                     ;
; 17.389 ; 17.605       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_DI[14]                                                                                                                                                                                                                                     ;
; 17.389 ; 17.605       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_DI[15]                                                                                                                                                                                                                                     ;
; 17.389 ; 17.605       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_DI[16]                                                                                                                                                                                                                                     ;
; 17.389 ; 17.605       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_DI[18]                                                                                                                                                                                                                                     ;
; 17.389 ; 17.605       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_DI[19]                                                                                                                                                                                                                                     ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                   ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                        ; Clock Edge ; Target                                                                                             ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------+
; 17.598 ; 17.598       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.598 ; 17.598       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.598 ; 17.598       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.598 ; 17.598       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]                      ;
; 17.598 ; 17.598       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 17.612 ; 17.612       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.619 ; 17.619       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.619 ; 17.619       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.623 ; 17.623       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.623 ; 17.623       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.629 ; 17.629       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.644 ; 17.644       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.644 ; 17.644       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.644 ; 17.644       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.644 ; 17.644       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]                      ;
; 17.644 ; 17.644       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'                                                                                                                        ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------+
; Slack   ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                                                 ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------+
; 99.405  ; 99.405       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 99.405  ; 99.405       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 99.407  ; 99.407       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                    ;
; 99.407  ; 99.407       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|observablevcoout                          ;
; 99.439  ; 99.439       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                       ;
; 99.450  ; 99.450       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 99.452  ; 99.452       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|inclk[0]                                  ;
; 100.000 ; 100.000      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                       ;
; 100.000 ; 100.000      ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                       ;
; 100.548 ; 100.548      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|inclk[0]                                  ;
; 100.549 ; 100.549      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 100.561 ; 100.561      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                       ;
; 100.591 ; 100.591      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                    ;
; 100.591 ; 100.591      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|observablevcoout                          ;
; 100.592 ; 100.592      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 100.592 ; 100.592      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 196.000 ; 200.000      ; 4.000          ; Port Rate        ; FPGA_CLK ; Rise       ; FPGA_CLK                                                                               ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                             ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.495 ; 2.053 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.474 ; 2.032 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.474 ; 2.032 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.474 ; 2.032 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 1.486 ; 2.044 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 1.491 ; 2.049 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 1.489 ; 2.047 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 1.485 ; 2.043 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 1.495 ; 2.053 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 1.487 ; 2.045 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 1.493 ; 2.051 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.493 ; 2.051 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.493 ; 2.051 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.483 ; 2.041 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 1.481 ; 2.039 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.471 ; 2.029 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.481 ; 2.039 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; 3.861 ; 4.234 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; 2.119 ; 2.603 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; 2.186 ; 2.674 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; 2.628 ; 3.205 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; 2.671 ; 3.236 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; 3.861 ; 4.234 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; 3.589 ; 3.914 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; 2.118 ; 2.605 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; 1.992 ; 2.493 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; 2.735 ; 3.245 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; 2.538 ; 3.070 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; 3.589 ; 3.914 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; 3.242 ; 4.059 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; 3.112 ; 3.883 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; 1.822 ; 2.348 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 0.437 ; 0.997 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ;
; USB2_P        ; FPGA_CLK   ; 0.437 ; 0.997 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; -1.005 ; -1.563 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; -1.008 ; -1.566 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; -1.008 ; -1.566 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; -1.008 ; -1.566 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; -1.020 ; -1.578 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; -1.025 ; -1.583 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; -1.023 ; -1.581 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; -1.019 ; -1.577 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; -1.029 ; -1.587 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; -1.021 ; -1.579 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; -1.027 ; -1.585 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; -1.027 ; -1.585 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; -1.027 ; -1.585 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; -1.017 ; -1.575 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; -1.015 ; -1.573 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; -1.005 ; -1.563 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; -1.015 ; -1.573 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; -1.606 ; -2.076 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; -1.606 ; -2.076 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; -1.672 ; -2.144 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; -2.038 ; -2.579 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; -2.081 ; -2.609 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; -2.055 ; -2.600 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; -1.491 ; -1.987 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; -1.611 ; -2.094 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; -1.491 ; -1.987 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; -2.170 ; -2.676 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; -2.016 ; -2.542 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; -1.765 ; -2.233 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; -2.689 ; -3.488 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; -2.562 ; -3.320 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; -1.327 ; -1.848 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; -0.108 ; -0.668 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ;
; USB2_P        ; FPGA_CLK   ; -0.108 ; -0.668 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                     ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 2.588 ; 2.294 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 1.607 ; 1.456 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 1.597 ; 1.446 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 1.597 ; 1.446 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 1.597 ; 1.446 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 1.596 ; 1.445 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 1.604 ; 1.453 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 1.613 ; 1.462 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 2.588 ; 2.294 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 1.615 ; 1.464 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 1.625 ; 1.474 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 1.607 ; 1.456 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 2.582 ; 2.288 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 1.609 ; 1.458 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 2.582 ; 2.288 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 2.594 ; 2.300 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 1.619 ; 1.468 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 2.640 ; 2.362 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 1.753 ; 1.607 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 1.753 ; 1.607 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 1.753 ; 1.607 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 2.627 ; 2.349 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 2.622 ; 2.344 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 1.163 ; 1.075 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 1.685 ; 1.535 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 1.695 ; 1.545 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 1.780 ; 1.634 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 2.640 ; 2.362 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 1.774 ; 1.628 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 1.774 ; 1.628 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 1.764 ; 1.618 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 2.632 ; 2.354 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 1.756 ; 1.610 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 1.766 ; 1.620 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 1.607 ; 1.601 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 1.545 ; 1.528 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 1.607 ; 1.601 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 1.619 ; 1.468 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 1.629 ; 1.478 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 3.664 ; 4.250 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 1.911 ; 2.049 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 1.605 ; 1.681 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 3.168 ; 3.680 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 1.475 ; 1.420 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 8.074 ;       ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 8.021 ; Fall       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]        ; FPGA_CLK   ; 2.932 ; 3.400 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]       ; FPGA_CLK   ; 1.316 ; 1.335 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]       ; FPGA_CLK   ; 2.932 ; 3.400 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]       ; FPGA_CLK   ; 1.131 ; 1.193 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]       ; FPGA_CLK   ; 2.917 ; 3.385 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]        ; FPGA_CLK   ; 2.885 ; 3.318 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]       ; FPGA_CLK   ; 2.885 ; 3.318 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]       ; FPGA_CLK   ; 1.108 ; 1.074 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]       ; FPGA_CLK   ; 1.118 ; 1.084 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]       ; FPGA_CLK   ; 1.108 ; 1.074 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_HS          ; FPGA_CLK   ; 2.873 ; 3.306 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_R[*]        ; FPGA_CLK   ; 1.099 ; 1.065 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[0]       ; FPGA_CLK   ; 1.086 ; 1.052 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[1]       ; FPGA_CLK   ; 1.096 ; 1.062 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[2]       ; FPGA_CLK   ; 1.099 ; 1.065 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[3]       ; FPGA_CLK   ; 1.089 ; 1.055 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_VS          ; FPGA_CLK   ; 1.097 ; 1.063 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; USB2_N          ; FPGA_CLK   ; 1.927 ; 1.893 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ;
; USB2_P          ; FPGA_CLK   ; 1.927 ; 1.893 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                             ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 1.178 ; 1.029 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 1.189 ; 1.040 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 1.179 ; 1.030 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 1.179 ; 1.030 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 1.179 ; 1.030 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 1.178 ; 1.029 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 1.186 ; 1.037 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 1.195 ; 1.046 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 2.192 ; 1.898 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 1.197 ; 1.048 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 1.207 ; 1.058 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 1.189 ; 1.040 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 1.191 ; 1.042 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 1.191 ; 1.042 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 2.186 ; 1.892 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 2.198 ; 1.904 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 1.201 ; 1.052 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 0.768 ; 0.680 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 1.334 ; 1.190 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 1.334 ; 1.190 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 1.334 ; 1.190 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 2.232 ; 1.954 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 2.227 ; 1.949 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 0.768 ; 0.680 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 1.266 ; 1.118 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 1.276 ; 1.128 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 1.361 ; 1.217 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 2.245 ; 1.967 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 1.355 ; 1.211 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 1.355 ; 1.211 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 1.345 ; 1.201 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 2.237 ; 1.959 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 1.337 ; 1.193 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 1.347 ; 1.203 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 1.131 ; 1.117 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 1.131 ; 1.117 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 1.191 ; 1.188 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 1.201 ; 1.052 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 1.211 ; 1.062 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 3.242 ; 3.824 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 1.495 ; 1.629 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 1.192 ; 1.264 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 2.763 ; 3.273 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 1.066 ; 1.015 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 7.701 ;       ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 7.647 ; Fall       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]        ; FPGA_CLK   ; 0.736 ; 0.798 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]       ; FPGA_CLK   ; 0.920 ; 0.939 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]       ; FPGA_CLK   ; 2.537 ; 3.005 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]       ; FPGA_CLK   ; 0.736 ; 0.798 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]       ; FPGA_CLK   ; 2.522 ; 2.990 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]        ; FPGA_CLK   ; 0.711 ; 0.677 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]       ; FPGA_CLK   ; 2.488 ; 2.921 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]       ; FPGA_CLK   ; 0.711 ; 0.677 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]       ; FPGA_CLK   ; 0.721 ; 0.687 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]       ; FPGA_CLK   ; 0.711 ; 0.677 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_HS          ; FPGA_CLK   ; 2.477 ; 2.910 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_R[*]        ; FPGA_CLK   ; 0.690 ; 0.656 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[0]       ; FPGA_CLK   ; 0.690 ; 0.656 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[1]       ; FPGA_CLK   ; 0.700 ; 0.666 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[2]       ; FPGA_CLK   ; 0.702 ; 0.668 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[3]       ; FPGA_CLK   ; 0.692 ; 0.658 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_VS          ; FPGA_CLK   ; 0.700 ; 0.666 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; USB2_N          ; FPGA_CLK   ; 1.669 ; 1.635 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ;
; USB2_P          ; FPGA_CLK   ; 1.669 ; 1.635 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.998 ; 1.971 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.347 ; 2.320 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.347 ; 2.320 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.347 ; 2.320 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.391 ; 2.364 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.581 ; 2.554 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.574 ; 2.547 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.388 ; 2.361 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.411 ; 2.384 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.515 ; 2.488 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.355 ; 2.328 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.179 ; 2.152 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.179 ; 2.152 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.169 ; 2.142 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.008 ; 1.981 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.998 ; 1.971 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.008 ; 1.981 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.645 ; 2.269 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 3.632 ; 3.256 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ;
; USB2_P        ; FPGA_CLK   ; 3.632 ; 3.256 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                             ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 0.703 ; 0.703 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.038 ; 1.038 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.038 ; 1.038 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.038 ; 1.038 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 1.080 ; 1.080 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 1.263 ; 1.263 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 1.256 ; 1.256 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 1.078 ; 1.078 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 1.101 ; 1.101 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 1.200 ; 1.200 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 1.047 ; 1.047 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 0.878 ; 0.878 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 0.878 ; 0.878 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 0.868 ; 0.868 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 0.713 ; 0.713 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 0.703 ; 0.703 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 0.713 ; 0.713 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.138 ; 1.777 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 3.257 ; 2.896 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ;
; USB2_P        ; FPGA_CLK   ; 3.257 ; 2.896 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                            ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.044     ; 2.044     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.451     ; 2.451     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.451     ; 2.451     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.451     ; 2.451     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.510     ; 2.510     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.712     ; 2.712     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.712     ; 2.712     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.504     ; 2.504     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.533     ; 2.533     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.613     ; 2.613     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.439     ; 2.439     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.241     ; 2.241     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.241     ; 2.241     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.231     ; 2.231     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.054     ; 2.054     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.044     ; 2.044     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.054     ; 2.054     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.343     ; 2.719     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 3.344     ; 3.720     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ;
; USB2_P        ; FPGA_CLK   ; 3.344     ; 3.720     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                                    ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 0.747     ; 0.864     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.138     ; 1.255     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.138     ; 1.255     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.138     ; 1.255     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 1.195     ; 1.312     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 1.388     ; 1.505     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 1.389     ; 1.506     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 1.189     ; 1.306     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 1.217     ; 1.334     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 1.294     ; 1.411     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 1.127     ; 1.244     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 0.937     ; 1.054     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 0.937     ; 1.054     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 0.927     ; 1.044     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 0.757     ; 0.874     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 0.747     ; 0.864     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 0.757     ; 0.874     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 1.848     ; 2.209     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 2.981     ; 3.342     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ;
; USB2_P        ; FPGA_CLK   ; 2.981     ; 3.342     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+


---------------------------------------------
; Fast 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+------------------------------------------------------------------------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary                                                                                                            ;
+--------------------------------------------------------------------------------+----------+---------+----------+---------+---------------------+
; Clock                                                                          ; Setup    ; Hold    ; Recovery ; Removal ; Minimum Pulse Width ;
+--------------------------------------------------------------------------------+----------+---------+----------+---------+---------------------+
; Worst-case Slack                                                               ; -3.853   ; -1.725  ; 6.223    ; 1.163   ; 5.570               ;
;  FPGA_CLK                                                                      ; N/A      ; N/A     ; N/A      ; N/A     ; 99.405              ;
;  \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.731    ; 0.187   ; 7.730    ; 1.163   ; 5.570               ;
;  \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; -3.853   ; 0.185   ; 6.223    ; 1.893   ; 17.191              ;
;  \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 9.765    ; 0.114   ; 11.432   ; 2.017   ; 8.510               ;
;  \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]  ; N/A      ; N/A     ; N/A      ; N/A     ; 17.584              ;
;  usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; -0.554   ; -1.725  ; N/A      ; N/A     ; 10.068              ;
; Design-wide TNS                                                                ; -150.861 ; -63.784 ; 0.0      ; 0.0     ; 0.0                 ;
;  FPGA_CLK                                                                      ; N/A      ; N/A     ; N/A      ; N/A     ; 0.000               ;
;  \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000    ; 0.000   ; 0.000    ; 0.000   ; 0.000               ;
;  \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; -139.896 ; 0.000   ; 0.000    ; 0.000   ; 0.000               ;
;  \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000    ; 0.000   ; 0.000    ; 0.000   ; 0.000               ;
;  \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]  ; N/A      ; N/A     ; N/A      ; N/A     ; 0.000               ;
;  usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; -12.827  ; -63.784 ; N/A      ; N/A     ; 0.000               ;
+--------------------------------------------------------------------------------+----------+---------+----------+---------+---------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                             ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 3.046 ; 3.153 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.025 ; 3.132 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.025 ; 3.132 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.025 ; 3.132 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.036 ; 3.143 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.040 ; 3.147 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.038 ; 3.145 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.034 ; 3.141 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.046 ; 3.153 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.032 ; 3.139 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.036 ; 3.143 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.036 ; 3.143 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.036 ; 3.143 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.026 ; 3.133 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 3.024 ; 3.131 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 3.014 ; 3.121 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 3.024 ; 3.131 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; 8.007 ; 8.404 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; 4.300 ; 4.502 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; 4.421 ; 4.705 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; 5.608 ; 5.757 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; 5.665 ; 5.827 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; 8.007 ; 8.404 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; 7.242 ; 7.710 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; 4.272 ; 4.508 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; 4.037 ; 4.257 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; 5.797 ; 5.884 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; 5.341 ; 5.500 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; 7.242 ; 7.710 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; 6.709 ; 7.028 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; 6.466 ; 6.712 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; 3.650 ; 3.852 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 0.864 ; 0.997 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ;
; USB2_P        ; FPGA_CLK   ; 0.864 ; 0.997 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; -1.005 ; -1.563 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; -1.008 ; -1.566 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; -1.008 ; -1.566 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; -1.008 ; -1.566 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; -1.020 ; -1.578 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; -1.025 ; -1.583 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; -1.023 ; -1.581 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; -1.019 ; -1.577 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; -1.029 ; -1.587 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; -1.021 ; -1.579 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; -1.027 ; -1.585 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; -1.027 ; -1.585 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; -1.027 ; -1.585 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; -1.017 ; -1.575 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; -1.015 ; -1.573 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; -1.005 ; -1.563 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; -1.015 ; -1.573 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; -1.606 ; -2.076 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; -1.606 ; -2.076 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; -1.672 ; -2.144 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; -2.038 ; -2.579 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; -2.081 ; -2.609 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; -2.055 ; -2.600 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; -1.491 ; -1.987 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; -1.611 ; -2.094 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; -1.491 ; -1.987 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; -2.170 ; -2.676 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; -2.016 ; -2.542 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; -1.765 ; -2.233 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; -2.689 ; -3.488 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; -2.562 ; -3.320 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; -1.327 ; -1.848 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; -0.093 ; -0.204 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ;
; USB2_P        ; FPGA_CLK   ; -0.093 ; -0.204 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                     ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 4.590 ; 4.140 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 3.323 ; 3.087 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 3.313 ; 3.077 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 3.313 ; 3.077 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 3.313 ; 3.077 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 3.317 ; 3.081 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 3.326 ; 3.090 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 3.335 ; 3.099 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 4.590 ; 4.140 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 3.336 ; 3.100 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 3.346 ; 3.110 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 3.323 ; 3.087 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 4.578 ; 4.128 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 3.325 ; 3.089 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 4.578 ; 4.128 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 4.590 ; 4.140 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 3.335 ; 3.099 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 4.657 ; 4.209 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 3.607 ; 3.350 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 3.607 ; 3.350 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 3.607 ; 3.350 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 4.637 ; 4.189 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 4.633 ; 4.185 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 2.563 ; 2.365 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 3.507 ; 3.264 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 3.519 ; 3.276 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 3.639 ; 3.382 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 4.657 ; 4.209 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 3.633 ; 3.376 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 3.633 ; 3.376 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 3.623 ; 3.366 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 4.648 ; 4.200 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 3.614 ; 3.357 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 3.624 ; 3.367 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 3.312 ; 3.626 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 3.207 ; 3.432 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 3.312 ; 3.626 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 3.335 ; 3.099 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 3.345 ; 3.109 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 7.005 ; 7.188 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 4.148 ; 3.987 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 3.778 ; 3.512 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 6.084 ; 6.217 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 3.098 ; 3.364 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 9.081 ;       ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 8.810 ; Fall       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]        ; FPGA_CLK   ; 5.382 ; 5.730 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]       ; FPGA_CLK   ; 2.808 ; 2.778 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]       ; FPGA_CLK   ; 5.382 ; 5.730 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]       ; FPGA_CLK   ; 2.578 ; 2.528 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]       ; FPGA_CLK   ; 5.360 ; 5.708 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]        ; FPGA_CLK   ; 5.266 ; 5.559 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]       ; FPGA_CLK   ; 5.266 ; 5.559 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]       ; FPGA_CLK   ; 2.506 ; 2.389 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]       ; FPGA_CLK   ; 2.516 ; 2.399 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]       ; FPGA_CLK   ; 2.506 ; 2.389 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_HS          ; FPGA_CLK   ; 5.255 ; 5.548 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_R[*]        ; FPGA_CLK   ; 2.496 ; 2.379 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[0]       ; FPGA_CLK   ; 2.484 ; 2.367 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[1]       ; FPGA_CLK   ; 2.494 ; 2.377 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[2]       ; FPGA_CLK   ; 2.496 ; 2.379 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[3]       ; FPGA_CLK   ; 2.486 ; 2.369 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_VS          ; FPGA_CLK   ; 2.495 ; 2.378 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; USB2_N          ; FPGA_CLK   ; 4.032 ; 3.908 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ;
; USB2_P          ; FPGA_CLK   ; 4.032 ; 3.908 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                             ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 1.178 ; 1.029 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 1.189 ; 1.040 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 1.179 ; 1.030 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 1.179 ; 1.030 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 1.179 ; 1.030 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 1.178 ; 1.029 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 1.186 ; 1.037 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 1.195 ; 1.046 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 2.192 ; 1.898 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 1.197 ; 1.048 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 1.207 ; 1.058 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 1.189 ; 1.040 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 1.191 ; 1.042 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 1.191 ; 1.042 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 2.186 ; 1.892 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 2.198 ; 1.904 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 1.201 ; 1.052 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 0.768 ; 0.680 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 1.334 ; 1.190 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 1.334 ; 1.190 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 1.334 ; 1.190 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 2.232 ; 1.954 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 2.227 ; 1.949 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 0.768 ; 0.680 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 1.266 ; 1.118 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 1.276 ; 1.128 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 1.361 ; 1.217 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 2.245 ; 1.967 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 1.355 ; 1.211 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 1.355 ; 1.211 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 1.345 ; 1.201 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 2.237 ; 1.959 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 1.337 ; 1.193 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 1.347 ; 1.203 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 1.131 ; 1.117 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 1.131 ; 1.117 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 1.191 ; 1.188 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 1.201 ; 1.052 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 1.211 ; 1.062 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 3.242 ; 3.824 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 1.495 ; 1.629 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 1.192 ; 1.264 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 2.763 ; 3.273 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 1.066 ; 1.015 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 7.701 ;       ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 7.647 ; Fall       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]        ; FPGA_CLK   ; 0.736 ; 0.798 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]       ; FPGA_CLK   ; 0.920 ; 0.939 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]       ; FPGA_CLK   ; 2.537 ; 3.005 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]       ; FPGA_CLK   ; 0.736 ; 0.798 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]       ; FPGA_CLK   ; 2.522 ; 2.990 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]        ; FPGA_CLK   ; 0.711 ; 0.677 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]       ; FPGA_CLK   ; 2.488 ; 2.921 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]       ; FPGA_CLK   ; 0.711 ; 0.677 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]       ; FPGA_CLK   ; 0.721 ; 0.687 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]       ; FPGA_CLK   ; 0.711 ; 0.677 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_HS          ; FPGA_CLK   ; 2.477 ; 2.910 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_R[*]        ; FPGA_CLK   ; 0.690 ; 0.656 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[0]       ; FPGA_CLK   ; 0.690 ; 0.656 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[1]       ; FPGA_CLK   ; 0.700 ; 0.666 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[2]       ; FPGA_CLK   ; 0.702 ; 0.668 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[3]       ; FPGA_CLK   ; 0.692 ; 0.658 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_VS          ; FPGA_CLK   ; 0.700 ; 0.666 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; USB2_N          ; FPGA_CLK   ; 1.669 ; 1.635 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ;
; USB2_P          ; FPGA_CLK   ; 1.669 ; 1.635 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                     ;
+----------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; Pin            ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
+----------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; VGA_VS         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_HS         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[0]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[1]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[2]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[3]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[0]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[1]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[2]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[3]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[0]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[1]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[2]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[3]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; AUDIO_L        ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; AUDIO_R        ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_BA[0]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_BA[1]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_CS_N     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_RAS_N    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_CAS_N    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_WE_N     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQM_n[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQM_n[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_CLK      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[0]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[1]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[2]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[3]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[4]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[5]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[6]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[7]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[8]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[9]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[10]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[11]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[12]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SD_CLK         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SD_CMD         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SD_DAT3        ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[0]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[1]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[2]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[3]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[4]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[5]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[6]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[7]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[8]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[9]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[10]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[11]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[12]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[13]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[14]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[15]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; USB2_P         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; USB2_N         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+----------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+


+-----------------------------------------------------------------+
; Input Transition Times                                          ;
+--------------+--------------+-----------------+-----------------+
; Pin          ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+--------------+--------------+-----------------+-----------------+
; PS2M_CLK     ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; PS2M_DAT     ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY1_n[5]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY2_n[5]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[0]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[1]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[2]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[3]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[4]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[5]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[6]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[7]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[8]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[9]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[10] ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[11] ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[12] ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[13] ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[14] ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[15] ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; USB2_P       ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; USB2_N       ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; FPGA_CLK     ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY1_n[4]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY2_n[4]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY2_n[2]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY1_n[2]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY1_n[0]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY1_n[1]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY1_n[3]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY2_n[3]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY2_n[0]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY2_n[1]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SD_DAT0      ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; PS2K_CLK     ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; PS2K_DAT     ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
+--------------+--------------+-----------------+-----------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin            ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; VGA_VS         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_HS         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.00154 V          ; 0.08 V                               ; 0.145 V                              ; 7.32e-09 s                  ; 7.58e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.00154 V         ; 0.08 V                              ; 0.145 V                             ; 7.32e-09 s                 ; 7.58e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[0]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.46e-07 V                   ; 3.09 V              ; -0.011 V            ; 0.146 V                              ; 0.189 V                              ; 1.76e-09 s                  ; 1.77e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.46e-07 V                  ; 3.09 V             ; -0.011 V           ; 0.146 V                             ; 0.189 V                             ; 1.76e-09 s                 ; 1.77e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[1]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.46e-07 V                   ; 3.08 V              ; -0.00108 V          ; 0.089 V                              ; 0.161 V                              ; 7.68e-09 s                  ; 7.97e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.46e-07 V                  ; 3.08 V             ; -0.00108 V         ; 0.089 V                             ; 0.161 V                             ; 7.68e-09 s                 ; 7.97e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[2]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.46e-07 V                   ; 3.09 V              ; -0.013 V            ; 0.091 V                              ; 0.178 V                              ; 1.33e-09 s                  ; 1.36e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.46e-07 V                  ; 3.09 V             ; -0.013 V           ; 0.091 V                             ; 0.178 V                             ; 1.33e-09 s                 ; 1.36e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[3]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.46e-07 V                   ; 3.08 V              ; -0.00108 V          ; 0.089 V                              ; 0.161 V                              ; 7.68e-09 s                  ; 7.97e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.46e-07 V                  ; 3.08 V             ; -0.00108 V         ; 0.089 V                             ; 0.161 V                             ; 7.68e-09 s                 ; 7.97e-09 s                 ; Yes                       ; Yes                       ;
; VGA_G[0]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.00154 V          ; 0.08 V                               ; 0.145 V                              ; 7.32e-09 s                  ; 7.58e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.00154 V         ; 0.08 V                              ; 0.145 V                             ; 7.32e-09 s                 ; 7.58e-09 s                 ; Yes                       ; Yes                       ;
; VGA_G[1]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_G[2]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_G[3]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_R[0]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_R[1]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_R[2]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_R[3]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; AUDIO_L        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.46e-07 V                   ; 3.08 V              ; -0.00108 V          ; 0.089 V                              ; 0.161 V                              ; 7.68e-09 s                  ; 7.97e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.46e-07 V                  ; 3.08 V             ; -0.00108 V         ; 0.089 V                             ; 0.161 V                             ; 7.68e-09 s                 ; 7.97e-09 s                 ; Yes                       ; Yes                       ;
; AUDIO_R        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.46e-07 V                   ; 3.09 V              ; -0.011 V            ; 0.146 V                              ; 0.189 V                              ; 1.76e-09 s                  ; 1.77e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.46e-07 V                  ; 3.09 V             ; -0.011 V           ; 0.146 V                             ; 0.189 V                             ; 1.76e-09 s                 ; 1.77e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_BA[0]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_BA[1]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.08 V              ; -0.00469 V          ; 0.309 V                              ; 0.24 V                               ; 5.8e-09 s                   ; 4.65e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.08 V             ; -0.00469 V         ; 0.309 V                             ; 0.24 V                              ; 5.8e-09 s                  ; 4.65e-09 s                 ; No                        ; Yes                       ;
; SDRAM_CS_N     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_RAS_N    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_CAS_N    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.08 V              ; -0.00469 V          ; 0.309 V                              ; 0.24 V                               ; 5.8e-09 s                   ; 4.65e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.08 V             ; -0.00469 V         ; 0.309 V                             ; 0.24 V                              ; 5.8e-09 s                  ; 4.65e-09 s                 ; No                        ; Yes                       ;
; SDRAM_WE_N     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQM_n[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQM_n[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_CLK      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[6]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[7]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.08 V              ; -0.00469 V          ; 0.309 V                              ; 0.24 V                               ; 5.8e-09 s                   ; 4.65e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.08 V             ; -0.00469 V         ; 0.309 V                             ; 0.24 V                              ; 5.8e-09 s                  ; 4.65e-09 s                 ; No                        ; Yes                       ;
; SDRAM_A[8]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[9]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[10]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[11]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[12]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.08 V              ; -0.00469 V          ; 0.309 V                              ; 0.24 V                               ; 5.8e-09 s                   ; 4.65e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.08 V             ; -0.00469 V         ; 0.309 V                             ; 0.24 V                              ; 5.8e-09 s                  ; 4.65e-09 s                 ; No                        ; Yes                       ;
; SD_CLK         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; SD_CMD         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.00154 V          ; 0.08 V                               ; 0.145 V                              ; 7.32e-09 s                  ; 7.58e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.00154 V         ; 0.08 V                              ; 0.145 V                             ; 7.32e-09 s                 ; 7.58e-09 s                 ; Yes                       ; Yes                       ;
; SD_DAT3        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[0]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[1]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[2]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[3]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.08 V              ; -0.00384 V          ; 0.283 V                              ; 0.244 V                              ; 6.17e-09 s                  ; 4.9e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.08 V             ; -0.00384 V         ; 0.283 V                             ; 0.244 V                             ; 6.17e-09 s                 ; 4.9e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[4]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.08 V              ; -0.00384 V          ; 0.283 V                              ; 0.244 V                              ; 6.17e-09 s                  ; 4.9e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.08 V             ; -0.00384 V         ; 0.283 V                             ; 0.244 V                             ; 6.17e-09 s                 ; 4.9e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[5]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[6]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.12 V              ; -0.0417 V           ; 0.221 V                              ; 0.245 V                              ; 1.09e-09 s                  ; 8.59e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.12 V             ; -0.0417 V          ; 0.221 V                             ; 0.245 V                             ; 1.09e-09 s                 ; 8.59e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[7]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.12 V              ; -0.0417 V           ; 0.221 V                              ; 0.245 V                              ; 1.09e-09 s                  ; 8.59e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.12 V             ; -0.0417 V          ; 0.221 V                             ; 0.245 V                             ; 1.09e-09 s                 ; 8.59e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[8]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[9]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.08 V              ; -0.00384 V          ; 0.283 V                              ; 0.244 V                              ; 6.17e-09 s                  ; 4.9e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.08 V             ; -0.00384 V         ; 0.283 V                             ; 0.244 V                             ; 6.17e-09 s                 ; 4.9e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[10]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[11]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[12]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[13]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.08 V              ; -0.00384 V          ; 0.283 V                              ; 0.244 V                              ; 6.17e-09 s                  ; 4.9e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.08 V             ; -0.00384 V         ; 0.283 V                             ; 0.244 V                             ; 6.17e-09 s                 ; 4.9e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[14]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[15]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; USB2_P         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; USB2_N         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin            ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; VGA_VS         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_HS         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.47 V              ; -0.0076 V           ; 0.323 V                              ; 0.334 V                              ; 4.77e-09 s                  ; 5.17e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 3.1e-07 V                   ; 3.47 V             ; -0.0076 V          ; 0.323 V                             ; 0.334 V                             ; 4.77e-09 s                 ; 5.17e-09 s                 ; No                        ; No                        ;
; VGA_B[0]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.1e-07 V                    ; 3.51 V              ; -0.0419 V           ; 0.296 V                              ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.1e-07 V                   ; 3.51 V             ; -0.0419 V          ; 0.296 V                             ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; VGA_B[1]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.1e-07 V                    ; 3.47 V              ; -0.00709 V          ; 0.326 V                              ; 0.34 V                               ; 5.02e-09 s                  ; 5.43e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.1e-07 V                   ; 3.47 V             ; -0.00709 V         ; 0.326 V                             ; 0.34 V                              ; 5.02e-09 s                 ; 5.43e-09 s                 ; No                        ; No                        ;
; VGA_B[2]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.1e-07 V                    ; 3.52 V              ; -0.0514 V           ; 0.253 V                              ; 0.324 V                              ; 8.77e-10 s                  ; 8.98e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 2.1e-07 V                   ; 3.52 V             ; -0.0514 V          ; 0.253 V                             ; 0.324 V                             ; 8.77e-10 s                 ; 8.98e-10 s                 ; No                        ; No                        ;
; VGA_B[3]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.1e-07 V                    ; 3.47 V              ; -0.00709 V          ; 0.326 V                              ; 0.34 V                               ; 5.02e-09 s                  ; 5.43e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.1e-07 V                   ; 3.47 V             ; -0.00709 V         ; 0.326 V                             ; 0.34 V                              ; 5.02e-09 s                 ; 5.43e-09 s                 ; No                        ; No                        ;
; VGA_G[0]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.47 V              ; -0.0076 V           ; 0.323 V                              ; 0.334 V                              ; 4.77e-09 s                  ; 5.17e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 3.1e-07 V                   ; 3.47 V             ; -0.0076 V          ; 0.323 V                             ; 0.334 V                             ; 4.77e-09 s                 ; 5.17e-09 s                 ; No                        ; No                        ;
; VGA_G[1]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_G[2]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_G[3]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_R[0]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_R[1]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_R[2]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_R[3]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; AUDIO_L        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.1e-07 V                    ; 3.47 V              ; -0.00709 V          ; 0.326 V                              ; 0.34 V                               ; 5.02e-09 s                  ; 5.43e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.1e-07 V                   ; 3.47 V             ; -0.00709 V         ; 0.326 V                             ; 0.34 V                              ; 5.02e-09 s                 ; 5.43e-09 s                 ; No                        ; No                        ;
; AUDIO_R        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.1e-07 V                    ; 3.51 V              ; -0.0419 V           ; 0.296 V                              ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.1e-07 V                   ; 3.51 V             ; -0.0419 V          ; 0.296 V                             ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; SDRAM_BA[0]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_BA[1]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.48 V              ; -0.0142 V           ; 0.362 V                              ; 0.291 V                              ; 3.89e-09 s                  ; 3.25e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.9e-07 V                   ; 3.48 V             ; -0.0142 V          ; 0.362 V                             ; 0.291 V                             ; 3.89e-09 s                 ; 3.25e-09 s                 ; No                        ; No                        ;
; SDRAM_CS_N     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_RAS_N    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_CAS_N    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.48 V              ; -0.0142 V           ; 0.362 V                              ; 0.291 V                              ; 3.89e-09 s                  ; 3.25e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.9e-07 V                   ; 3.48 V             ; -0.0142 V          ; 0.362 V                             ; 0.291 V                             ; 3.89e-09 s                 ; 3.25e-09 s                 ; No                        ; No                        ;
; SDRAM_WE_N     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_DQM_n[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_DQM_n[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_CLK      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[6]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[7]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.48 V              ; -0.0142 V           ; 0.362 V                              ; 0.291 V                              ; 3.89e-09 s                  ; 3.25e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.9e-07 V                   ; 3.48 V             ; -0.0142 V          ; 0.362 V                             ; 0.291 V                             ; 3.89e-09 s                 ; 3.25e-09 s                 ; No                        ; No                        ;
; SDRAM_A[8]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[9]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[10]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[11]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[12]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.48 V              ; -0.0142 V           ; 0.362 V                              ; 0.291 V                              ; 3.89e-09 s                  ; 3.25e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.9e-07 V                   ; 3.48 V             ; -0.0142 V          ; 0.362 V                             ; 0.291 V                             ; 3.89e-09 s                 ; 3.25e-09 s                 ; No                        ; No                        ;
; SD_CLK         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SD_CMD         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.47 V              ; -0.0076 V           ; 0.323 V                              ; 0.334 V                              ; 4.77e-09 s                  ; 5.17e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 3.1e-07 V                   ; 3.47 V             ; -0.0076 V          ; 0.323 V                             ; 0.334 V                             ; 4.77e-09 s                 ; 5.17e-09 s                 ; No                        ; No                        ;
; SD_DAT3        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[0]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[1]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[2]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[3]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.48 V              ; -0.0136 V           ; 0.352 V                              ; 0.346 V                              ; 4.12e-09 s                  ; 3.34e-09 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.48 V             ; -0.0136 V          ; 0.352 V                             ; 0.346 V                             ; 4.12e-09 s                 ; 3.34e-09 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[4]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.48 V              ; -0.0136 V           ; 0.352 V                              ; 0.346 V                              ; 4.12e-09 s                  ; 3.34e-09 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.48 V             ; -0.0136 V          ; 0.352 V                             ; 0.346 V                             ; 4.12e-09 s                 ; 3.34e-09 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[5]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[6]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.57 V              ; -0.0645 V           ; 0.332 V                              ; 0.165 V                              ; 6.78e-10 s                  ; 6.19e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.57 V             ; -0.0645 V          ; 0.332 V                             ; 0.165 V                             ; 6.78e-10 s                 ; 6.19e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[7]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.57 V              ; -0.0645 V           ; 0.332 V                              ; 0.165 V                              ; 6.78e-10 s                  ; 6.19e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.57 V             ; -0.0645 V          ; 0.332 V                             ; 0.165 V                             ; 6.78e-10 s                 ; 6.19e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[8]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[9]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.48 V              ; -0.0136 V           ; 0.352 V                              ; 0.346 V                              ; 4.12e-09 s                  ; 3.34e-09 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.48 V             ; -0.0136 V          ; 0.352 V                             ; 0.346 V                             ; 4.12e-09 s                 ; 3.34e-09 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[10]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[11]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[12]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[13]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.48 V              ; -0.0136 V           ; 0.352 V                              ; 0.346 V                              ; 4.12e-09 s                  ; 3.34e-09 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.48 V             ; -0.0136 V          ; 0.352 V                             ; 0.346 V                             ; 4.12e-09 s                 ; 3.34e-09 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[14]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[15]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; USB2_P         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; USB2_N         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Transfers                                                                                                                                                                                           ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                                    ; To Clock                                                                      ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------+----------+----------+----------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1826     ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1        ; 248      ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 9836     ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 18681520 ; 0        ; 81871    ; 0        ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 44       ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 42       ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 1253     ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; 40       ; 0        ; 0        ; 0        ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; 10028    ; 0        ; 0        ; 0        ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Transfers                                                                                                                                                                                            ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                                    ; To Clock                                                                      ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------+----------+----------+----------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1826     ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1        ; 248      ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 9836     ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 18681520 ; 0        ; 81871    ; 0        ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 44       ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 42       ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 1253     ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; 40       ; 0        ; 0        ; 0        ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                           ; 10028    ; 0        ; 0        ; 0        ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Recovery Transfers                                                                                                                                                                                        ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                                    ; To Clock                                                                      ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------+----------+----------+----------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 146      ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 655      ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 2423     ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 175      ; 0        ; 0        ; 0        ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Removal Transfers                                                                                                                                                                                         ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                                    ; To Clock                                                                      ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------+----------+----------+----------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 146      ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 655      ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 2423     ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 175      ; 0        ; 0        ; 0        ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design


---------------
; Report RSKM ;
---------------
No dedicated SERDES Receiver circuitry present in device or used in design


+------------------------------------------------+
; Unconstrained Paths                            ;
+---------------------------------+-------+------+
; Property                        ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks                  ; 0     ; 0    ;
; Unconstrained Clocks            ; 0     ; 0    ;
; Unconstrained Input Ports       ; 31    ; 31   ;
; Unconstrained Input Port Paths  ; 63    ; 63   ;
; Unconstrained Output Ports      ; 57    ; 57   ;
; Unconstrained Output Port Paths ; 76    ; 76   ;
+---------------------------------+-------+------+


+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II 32-bit TimeQuest Timing Analyzer
    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
    Info: Processing started: Sat Mar 28 00:12:43 2015
Info: Command: quartus_sta atari800core -c atari800core
Info: qsta_default_script.tcl version: #1
Info (11104): Parallel Compilation has detected 4 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 2 of the 2 physical processors detected instead.
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (332104): Reading SDC File: 'atari800core.sdc'
Info (332110): Deriving PLL clocks
    Info (332110): create_generated_clock -source {\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 3 -duty_cycle 50.00 -name {\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]} {\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]}
    Info (332110): create_generated_clock -source {\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]} -duty_cycle 50.00 -name {\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]} {\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]}
    Info (332110): create_generated_clock -source {\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 3 -phase 225.00 -duty_cycle 50.00 -name {\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]} {\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]}
    Info (332110): create_generated_clock -source {\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -duty_cycle 50.00 -name {\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]} {\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]}
    Info (332110): create_generated_clock -source {\gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 40 -multiply_by 227 -duty_cycle 50.00 -name {\gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]} {\gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]}
    Info (332110): create_generated_clock -source {usb_pll|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 5 -multiply_by 48 -duty_cycle 50.00 -name {usb_pll|altpll_component|auto_generated|pll1|clk[0]} {usb_pll|altpll_component|auto_generated|pll1|clk[0]}
Info (332151): Clock uncertainty is not calculated until you update the timing netlist.
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Analyzing Slow 1200mV 85C Model
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -3.853
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -3.853      -139.896 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    -0.486       -10.965 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.731         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     9.765         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case hold slack is -1.725
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -1.725       -63.784 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.370         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):     0.453         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.454         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case recovery slack is 6.223
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     6.223         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     7.730         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    11.432         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case removal slack is 2.605
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     2.605         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     4.075         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     4.546         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case minimum pulse width slack is 5.570
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     5.570         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     8.513         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):    10.104         0.000 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    17.191         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    17.584         0.000 \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    99.858         0.000 FPGA_CLK 
Info: Analyzing Slow 1200mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -3.449
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -3.449      -123.744 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    -0.554       -12.827 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     1.007         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    10.082         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case hold slack is -1.488
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -1.488       -55.680 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.372         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):     0.402         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.403         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case recovery slack is 6.696
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     6.696         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     8.124         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    11.795         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case removal slack is 2.337
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     2.337         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     3.704         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     4.061         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case minimum pulse width slack is 5.571
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     5.571         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     8.510         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):    10.068         0.000 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    17.223         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    17.587         0.000 \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    99.831         0.000 FPGA_CLK 
Info: Analyzing Fast 1200mV 0C Model
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -1.821
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -1.821       -67.826 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    -0.232        -5.029 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     3.575         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    14.165         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case hold slack is -0.979
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -0.979       -36.949 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.114         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):     0.185         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.187         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case recovery slack is 9.263
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     9.263         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     9.902         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    14.743         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case removal slack is 1.163
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     1.163         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     1.893         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     2.017         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case minimum pulse width slack is 5.657
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     5.657         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     8.557         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):    10.162         0.000 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    17.367         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    17.598         0.000 \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    99.405         0.000 FPGA_CLK 
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 3 warnings
    Info: Peak virtual memory: 534 megabytes
    Info: Processing ended: Sat Mar 28 00:12:59 2015
    Info: Elapsed time: 00:00:16
    Info: Total CPU time (on all processors): 00:00:19


