TimeQuest Timing Analyzer report for atari800core
Sat Nov  8 23:41:07 2014
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Parallel Compilation
  4. SDC File List
  5. Clocks
  6. Slow 1200mV 85C Model Fmax Summary
  7. Timing Closure Recommendations
  8. Slow 1200mV 85C Model Setup Summary
  9. Slow 1200mV 85C Model Hold Summary
 10. Slow 1200mV 85C Model Recovery Summary
 11. Slow 1200mV 85C Model Removal Summary
 12. Slow 1200mV 85C Model Minimum Pulse Width Summary
 13. Slow 1200mV 85C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 14. Slow 1200mV 85C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 15. Slow 1200mV 85C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3]'
 16. Slow 1200mV 85C Model Setup: 'mcc_pll3|altpll_component|auto_generated|pll1|clk[0]'
 17. Slow 1200mV 85C Model Setup: 'altera_reserved_tck'
 18. Slow 1200mV 85C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3]'
 19. Slow 1200mV 85C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 20. Slow 1200mV 85C Model Hold: 'mcc_pll3|altpll_component|auto_generated|pll1|clk[0]'
 21. Slow 1200mV 85C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 22. Slow 1200mV 85C Model Hold: 'altera_reserved_tck'
 23. Slow 1200mV 85C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 24. Slow 1200mV 85C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 25. Slow 1200mV 85C Model Recovery: 'altera_reserved_tck'
 26. Slow 1200mV 85C Model Recovery: 'mcc_pll3|altpll_component|auto_generated|pll1|clk[0]'
 27. Slow 1200mV 85C Model Removal: 'mcc_pll3|altpll_component|auto_generated|pll1|clk[0]'
 28. Slow 1200mV 85C Model Removal: 'altera_reserved_tck'
 29. Slow 1200mV 85C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 30. Slow 1200mV 85C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 31. Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3]'
 32. Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 33. Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 34. Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]'
 35. Slow 1200mV 85C Model Minimum Pulse Width: 'mcc_pll3|altpll_component|auto_generated|pll1|clk[0]'
 36. Slow 1200mV 85C Model Minimum Pulse Width: 'altera_reserved_tck'
 37. Slow 1200mV 85C Model Minimum Pulse Width: 'FPGA_CLK'
 38. Setup Times
 39. Hold Times
 40. Clock to Output Times
 41. Minimum Clock to Output Times
 42. Output Enable Times
 43. Minimum Output Enable Times
 44. Output Disable Times
 45. Minimum Output Disable Times
 46. Slow 1200mV 85C Model Metastability Report
 47. Slow 1200mV 0C Model Fmax Summary
 48. Slow 1200mV 0C Model Setup Summary
 49. Slow 1200mV 0C Model Hold Summary
 50. Slow 1200mV 0C Model Recovery Summary
 51. Slow 1200mV 0C Model Removal Summary
 52. Slow 1200mV 0C Model Minimum Pulse Width Summary
 53. Slow 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 54. Slow 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 55. Slow 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3]'
 56. Slow 1200mV 0C Model Setup: 'mcc_pll3|altpll_component|auto_generated|pll1|clk[0]'
 57. Slow 1200mV 0C Model Setup: 'altera_reserved_tck'
 58. Slow 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3]'
 59. Slow 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 60. Slow 1200mV 0C Model Hold: 'altera_reserved_tck'
 61. Slow 1200mV 0C Model Hold: 'mcc_pll3|altpll_component|auto_generated|pll1|clk[0]'
 62. Slow 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 63. Slow 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 64. Slow 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 65. Slow 1200mV 0C Model Recovery: 'altera_reserved_tck'
 66. Slow 1200mV 0C Model Recovery: 'mcc_pll3|altpll_component|auto_generated|pll1|clk[0]'
 67. Slow 1200mV 0C Model Removal: 'mcc_pll3|altpll_component|auto_generated|pll1|clk[0]'
 68. Slow 1200mV 0C Model Removal: 'altera_reserved_tck'
 69. Slow 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 70. Slow 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 71. Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3]'
 72. Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 73. Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 74. Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]'
 75. Slow 1200mV 0C Model Minimum Pulse Width: 'mcc_pll3|altpll_component|auto_generated|pll1|clk[0]'
 76. Slow 1200mV 0C Model Minimum Pulse Width: 'altera_reserved_tck'
 77. Slow 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'
 78. Setup Times
 79. Hold Times
 80. Clock to Output Times
 81. Minimum Clock to Output Times
 82. Output Enable Times
 83. Minimum Output Enable Times
 84. Output Disable Times
 85. Minimum Output Disable Times
 86. Slow 1200mV 0C Model Metastability Report
 87. Fast 1200mV 0C Model Setup Summary
 88. Fast 1200mV 0C Model Hold Summary
 89. Fast 1200mV 0C Model Recovery Summary
 90. Fast 1200mV 0C Model Removal Summary
 91. Fast 1200mV 0C Model Minimum Pulse Width Summary
 92. Fast 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 93. Fast 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 94. Fast 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3]'
 95. Fast 1200mV 0C Model Setup: 'mcc_pll3|altpll_component|auto_generated|pll1|clk[0]'
 96. Fast 1200mV 0C Model Setup: 'altera_reserved_tck'
 97. Fast 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3]'
 98. Fast 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 99. Fast 1200mV 0C Model Hold: 'mcc_pll3|altpll_component|auto_generated|pll1|clk[0]'
100. Fast 1200mV 0C Model Hold: 'altera_reserved_tck'
101. Fast 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
102. Fast 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
103. Fast 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
104. Fast 1200mV 0C Model Recovery: 'altera_reserved_tck'
105. Fast 1200mV 0C Model Recovery: 'mcc_pll3|altpll_component|auto_generated|pll1|clk[0]'
106. Fast 1200mV 0C Model Removal: 'mcc_pll3|altpll_component|auto_generated|pll1|clk[0]'
107. Fast 1200mV 0C Model Removal: 'altera_reserved_tck'
108. Fast 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
109. Fast 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
110. Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3]'
111. Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
112. Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
113. Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]'
114. Fast 1200mV 0C Model Minimum Pulse Width: 'mcc_pll3|altpll_component|auto_generated|pll1|clk[0]'
115. Fast 1200mV 0C Model Minimum Pulse Width: 'altera_reserved_tck'
116. Fast 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'
117. Setup Times
118. Hold Times
119. Clock to Output Times
120. Minimum Clock to Output Times
121. Output Enable Times
122. Minimum Output Enable Times
123. Output Disable Times
124. Minimum Output Disable Times
125. Fast 1200mV 0C Model Metastability Report
126. Multicorner Timing Analysis Summary
127. Setup Times
128. Hold Times
129. Clock to Output Times
130. Minimum Clock to Output Times
131. Board Trace Model Assignments
132. Input Transition Times
133. Signal Integrity Metrics (Slow 1200mv 0c Model)
134. Signal Integrity Metrics (Slow 1200mv 85c Model)
135. Signal Integrity Metrics (Fast 1200mv 0c Model)
136. Setup Transfers
137. Hold Transfers
138. Recovery Transfers
139. Removal Transfers
140. Report TCCS
141. Report RSKM
142. Unconstrained Paths
143. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
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Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
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(including device programming or simulation files), and any 
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Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                                      ;
+--------------------+-------------------------------------------------------------------+
; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ;
; Revision Name      ; atari800core                                                      ;
; Device Family      ; Cyclone IV E                                                      ;
; Device Name        ; EP4CE15E22C7                                                      ;
; Timing Models      ; Final                                                             ;
; Delay Model        ; Combined                                                          ;
; Rise/Fall Delays   ; Enabled                                                           ;
+--------------------+-------------------------------------------------------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 4           ;
; Maximum allowed            ; 2           ;
;                            ;             ;
; Average used               ; 1.27        ;
; Maximum used               ; 2           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processor 2            ;  27.0%      ;
;     Processors 3-4         ;   0.0%      ;
+----------------------------+-------------+


+------------------------------------------------------+
; SDC File List                                        ;
+------------------+--------+--------------------------+
; SDC File Path    ; Status ; Read at                  ;
+------------------+--------+--------------------------+
; atari800core.sdc ; OK     ; Sat Nov  8 23:40:33 2014 ;
+------------------+--------+--------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                                                                                                                                                                                                                                                                                                                              ;
+-------------------------------------------------------------------------------+-----------+---------+------------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+------------------------------------------------------------------------------+---------------------------------------------------------------------------------+-----------------------------------------------------------------------------------+
; Clock Name                                                                    ; Type      ; Period  ; Frequency  ; Rise  ; Fall    ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master                                                                       ; Source                                                                          ; Targets                                                                           ;
+-------------------------------------------------------------------------------+-----------+---------+------------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+------------------------------------------------------------------------------+---------------------------------------------------------------------------------+-----------------------------------------------------------------------------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Generated ; 11.747  ; 85.13 MHz  ; 0.000 ; 5.873   ; 50.00      ; 1         ; 3           ;       ;        ;           ;            ; false    ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] } ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Generated ; 35.242  ; 28.38 MHz  ; 0.000 ; 17.621  ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] } ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ; Generated ; 11.747  ; 85.13 MHz  ; 7.341 ; 13.214  ; 50.00      ; 1         ; 3           ; 225.0 ;        ;           ;            ; false    ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] } ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Generated ; 8.810   ; 113.51 MHz ; 0.000 ; 4.405   ; 50.00      ; 1         ; 4           ;       ;        ;           ;            ; false    ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] } ;
; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]  ; Generated ; 35.242  ; 28.38 MHz  ; 0.000 ; 17.621  ; 50.00      ; 40        ; 227         ;       ;        ;           ;            ; false    ; FPGA_CLK                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]  ; { \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] }  ;
; altera_reserved_tck                                                           ; Base      ; 100.000 ; 10.0 MHz   ; 0.000 ; 50.000  ;            ;           ;             ;       ;        ;           ;            ;          ;                                                                              ;                                                                                 ; { altera_reserved_tck }                                                           ;
; FPGA_CLK                                                                      ; Base      ; 200.000 ; 5.0 MHz    ; 0.000 ; 100.000 ;            ;           ;             ;       ;        ;           ;            ;          ;                                                                              ;                                                                                 ; { FPGA_CLK }                                                                      ;
; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ; Generated ; 66.666  ; 15.0 MHz   ; 0.000 ; 33.333  ; 50.00      ; 1         ; 3           ;       ;        ;           ;            ; false    ; FPGA_CLK                                                                     ; mcc_pll3|altpll_component|auto_generated|pll1|inclk[0]                          ; { mcc_pll3|altpll_component|auto_generated|pll1|clk[0] }                          ;
+-------------------------------------------------------------------------------+-----------+---------+------------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+------------------------------------------------------------------------------+---------------------------------------------------------------------------------+-----------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Fmax Summary                                                                                  ;
+------------+-----------------+-------------------------------------------------------------------------------+------+
; Fmax       ; Restricted Fmax ; Clock Name                                                                    ; Note ;
+------------+-----------------+-------------------------------------------------------------------------------+------+
; 52.06 MHz  ; 52.06 MHz       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;      ;
; 67.21 MHz  ; 67.21 MHz       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;      ;
; 106.2 MHz  ; 106.2 MHz       ; altera_reserved_tck                                                           ;      ;
; 115.54 MHz ; 115.54 MHz      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;      ;
; 226.5 MHz  ; 226.5 MHz       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;      ;
+------------+-----------------+-------------------------------------------------------------------------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


----------------------------------
; Timing Closure Recommendations ;
----------------------------------
HTML report is unavailable in plain text report export.


+--------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup Summary                                                                    ;
+-------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                         ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; -8.084 ; -912.430      ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.263 ; -0.507        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 4.395  ; 0.000         ;
; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ; 25.894 ; 0.000         ;
; altera_reserved_tck                                                           ; 45.292 ; 0.000         ;
+-------------------------------------------------------------------------------+--------+---------------+


+-------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold Summary                                                                    ;
+-------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                         ; Slack ; End Point TNS ;
+-------------------------------------------------------------------------------+-------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.355 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.380 ; 0.000         ;
; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ; 0.412 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.413 ; 0.000         ;
; altera_reserved_tck                                                           ; 0.413 ; 0.000         ;
+-------------------------------------------------------------------------------+-------+---------------+


+--------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery Summary                                                                 ;
+-------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                         ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 6.765  ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 7.798  ; 0.000         ;
; altera_reserved_tck                                                           ; 47.801 ; 0.000         ;
; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ; 63.166 ; 0.000         ;
+-------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal Summary                                                                  ;
+-------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                         ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------+--------+---------------+
; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ; -0.012 ; -0.217        ;
; altera_reserved_tck                                                           ; 1.254  ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 1.451  ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 2.199  ; 0.000         ;
+-------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width Summary                                                      ;
+-------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                         ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 4.128  ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.598  ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.342 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]  ; 17.594 ; 0.000         ;
; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ; 33.028 ; 0.000         ;
; altera_reserved_tck                                                           ; 49.479 ; 0.000         ;
; FPGA_CLK                                                                      ; 99.796 ; 0.000         ;
+-------------------------------------------------------------------------------+--------+---------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                        ;
+--------+--------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                        ; To Node                                                                                                                 ; Launch Clock                                         ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; -8.084 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.973     ; 6.257      ;
; -8.023 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.973     ; 6.196      ;
; -7.952 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.972     ; 6.126      ;
; -7.765 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[38] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.973     ; 5.938      ;
; -7.752 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.963     ; 5.935      ;
; -7.717 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[6]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[28]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.369     ; 5.494      ;
; -7.705 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[27] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.973     ; 5.878      ;
; -7.663 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[7] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[27]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.369     ; 5.440      ;
; -7.661 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[7]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[27]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.369     ; 5.438      ;
; -7.603 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[5]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.963     ; 5.786      ;
; -7.602 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[2]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.380     ; 5.368      ;
; -7.598 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[7] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[28]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.369     ; 5.375      ;
; -7.596 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[7]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[28]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.369     ; 5.373      ;
; -7.587 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[6]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[27]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.369     ; 5.364      ;
; -7.575 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[6] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[28]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.369     ; 5.352      ;
; -7.557 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[2]   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.382     ; 5.321      ;
; -7.550 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[10]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.387     ; 5.309      ;
; -7.528 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[18] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.973     ; 5.701      ;
; -7.527 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.955     ; 5.718      ;
; -7.524 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.956     ; 5.714      ;
; -7.515 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[0]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.974     ; 5.687      ;
; -7.512 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[29] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.963     ; 5.695      ;
; -7.512 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[4] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.959     ; 5.699      ;
; -7.511 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[2]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.358     ; 5.299      ;
; -7.502 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[41] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.975     ; 5.673      ;
; -7.495 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[37] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.975     ; 5.666      ;
; -7.487 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[1]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.341     ; 5.292      ;
; -7.486 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[7] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[29]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.368     ; 5.264      ;
; -7.484 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[2]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.368     ; 5.262      ;
; -7.484 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[7]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[29]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.368     ; 5.262      ;
; -7.471 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.959     ; 5.658      ;
; -7.453 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[1]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.342     ; 5.257      ;
; -7.445 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[6] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[27]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.369     ; 5.222      ;
; -7.443 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[6]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[30]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.368     ; 5.221      ;
; -7.433 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|doReg[2]    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.008     ; 5.571      ;
; -7.425 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[6]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[29]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.368     ; 5.203      ;
; -7.420 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[2]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.972     ; 5.594      ;
; -7.413 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.955     ; 5.604      ;
; -7.410 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.956     ; 5.600      ;
; -7.384 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[39] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.975     ; 5.555      ;
; -7.383 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[4] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.959     ; 5.570      ;
; -7.373 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[1]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.341     ; 5.178      ;
; -7.362 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[6]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[26]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.368     ; 5.140      ;
; -7.355 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[1]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.351     ; 5.150      ;
; -7.348 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[4] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[0]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.960     ; 5.534      ;
; -7.346 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.956     ; 5.536      ;
; -7.342 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.959     ; 5.529      ;
; -7.339 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[1]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.342     ; 5.143      ;
; -7.321 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[7] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[30]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.368     ; 5.099      ;
; -7.315 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_reg[2]                   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.355     ; 5.106      ;
; -7.307 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[0]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.960     ; 5.493      ;
; -7.307 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[7]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[30]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.368     ; 5.085      ;
; -7.305 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[7] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[23]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.370     ; 5.081      ;
; -7.303 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[6]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[24]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.368     ; 5.081      ;
; -7.303 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[7]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[23]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.370     ; 5.079      ;
; -7.301 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[6] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[30]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.368     ; 5.079      ;
; -7.287 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[2]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.008     ; 5.425      ;
; -7.283 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[6] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[29]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.368     ; 5.061      ;
; -7.279 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[11] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.966     ; 5.459      ;
; -7.274 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[25] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.370     ; 5.050      ;
; -7.274 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[24] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.370     ; 5.050      ;
; -7.273 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[6]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.370     ; 5.049      ;
; -7.273 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[4] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[0]                                                                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.354     ; 5.065      ;
; -7.259 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[11] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.949     ; 5.456      ;
; -7.258 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[1]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.973     ; 5.431      ;
; -7.244 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[15] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.973     ; 5.417      ;
; -7.241 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[1]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.351     ; 5.036      ;
; -7.240 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[7] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[26]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.368     ; 5.018      ;
; -7.232 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.956     ; 5.422      ;
; -7.231 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[7] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[31]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.964     ; 5.413      ;
; -7.229 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[7]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[31]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.964     ; 5.411      ;
; -7.227 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[1]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.363     ; 5.010      ;
; -7.226 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[6]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[23]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.370     ; 5.002      ;
; -7.223 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[1] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[0]                                                                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.354     ; 5.015      ;
; -7.220 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[6] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[26]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.368     ; 4.998      ;
; -7.206 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[34] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.973     ; 5.379      ;
; -7.205 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[7]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[26]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.368     ; 4.983      ;
; -7.195 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[29] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.946     ; 5.395      ;
; -7.190 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[10] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.973     ; 5.363      ;
; -7.188 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[41] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.958     ; 5.376      ;
; -7.181 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[7] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[24]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.368     ; 4.959      ;
; -7.172 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[4] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[38] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.959     ; 5.359      ;
; -7.172 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[6]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[31]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.964     ; 5.354      ;
; -7.161 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[6] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[24]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.368     ; 4.939      ;
; -7.146 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[22] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.975     ; 5.317      ;
; -7.146 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[7]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[24]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.368     ; 4.924      ;
; -7.145 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[11] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.949     ; 5.342      ;
; -7.144 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.946     ; 5.344      ;
; -7.141 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[16] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.975     ; 5.312      ;
; -7.140 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[27] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.956     ; 5.330      ;
; -7.138 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[26] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.973     ; 5.311      ;
; -7.131 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[38] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.959     ; 5.318      ;
; -7.113 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[1]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.363     ; 4.896      ;
; -7.095 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[7] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[25]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.369     ; 4.872      ;
; -7.093 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[7]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[25]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.369     ; 4.870      ;
; -7.091 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[6]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[20]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.370     ; 4.867      ;
; -7.089 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[1]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.956     ; 5.279      ;
; -7.081 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[29] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.946     ; 5.281      ;
; -7.079 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[6] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[23]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.370     ; 4.855      ;
; -7.074 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[41] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.958     ; 5.262      ;
+--------+--------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                       ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                         ; To Node                                      ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; -0.263 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.184     ; 11.709     ;
; -0.194 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 11.638     ;
; -0.166 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.191     ; 11.605     ;
; -0.150 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.191     ; 11.589     ;
; -0.144 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 11.588     ;
; -0.132 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.184     ; 11.578     ;
; -0.112 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.172     ; 11.570     ;
; -0.100 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.184     ; 11.546     ;
; -0.063 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 11.507     ;
; -0.046 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[9]                             ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.172     ; 11.504     ;
; -0.043 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 11.499     ;
; -0.039 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[11]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.173     ; 11.496     ;
; -0.035 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.191     ; 11.474     ;
; -0.019 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.191     ; 11.458     ;
; -0.015 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.179     ; 11.466     ;
; -0.013 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 11.457     ;
; -0.011 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.173     ; 11.468     ;
; -0.005 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 11.449     ;
; 0.001  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.179     ; 11.450     ;
; 0.007  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 11.448     ;
; 0.007  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 11.449     ;
; 0.031  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.184     ; 11.415     ;
; 0.051  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.172     ; 11.407     ;
; 0.076  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.177     ; 11.377     ;
; 0.085  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[9]                             ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.172     ; 11.373     ;
; 0.092  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[11]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.173     ; 11.365     ;
; 0.104  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 11.344     ;
; 0.105  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[9]                             ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.160     ; 11.365     ;
; 0.112  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[11]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.161     ; 11.357     ;
; 0.120  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.173     ; 11.337     ;
; 0.120  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 11.328     ;
; 0.126  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 11.318     ;
; 0.126  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.177     ; 11.327     ;
; 0.131  ; sdram_reset_n_reg                                                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 11.323     ;
; 0.133  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[13]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 11.323     ;
; 0.140  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.161     ; 11.329     ;
; 0.146  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 11.310     ;
; 0.148  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.185     ; 11.297     ;
; 0.169  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.191     ; 11.270     ;
; 0.170  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 11.285     ;
; 0.203  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[12]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 11.253     ;
; 0.204  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.187     ; 11.239     ;
; 0.212  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[10]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.172     ; 11.246     ;
; 0.220  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.188     ; 11.222     ;
; 0.224  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[9]                             ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.163     ; 11.243     ;
; 0.231  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[11]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.164     ; 11.235     ;
; 0.233  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.185     ; 11.212     ;
; 0.245  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.191     ; 11.194     ;
; 0.259  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.164     ; 11.207     ;
; 0.262  ; sdram_reset_n_reg                                                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 11.192     ;
; 0.264  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[13]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 11.192     ;
; 0.265  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.177     ; 11.188     ;
; 0.268  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[13]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.188     ; 11.174     ;
; 0.279  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.187     ; 11.164     ;
; 0.282  ; sdram_reset_n_reg                                                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.164     ; 11.184     ;
; 0.284  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[13]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.162     ; 11.184     ;
; 0.285  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.188     ; 11.157     ;
; 0.300  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.191     ; 11.139     ;
; 0.318  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.173     ; 11.139     ;
; 0.320  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.179     ; 11.131     ;
; 0.322  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[11]                                                                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 11.122     ;
; 0.334  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[12]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 11.122     ;
; 0.343  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[10]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.172     ; 11.115     ;
; 0.349  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 11.107     ;
; 0.351  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.188     ; 11.091     ;
; 0.354  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[12]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.162     ; 11.114     ;
; 0.363  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[10]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.160     ; 11.107     ;
; 0.371  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 11.083     ;
; 0.376  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.191     ; 11.063     ;
; 0.396  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.179     ; 11.055     ;
; 0.399  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[13]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.188     ; 11.043     ;
; 0.401  ; sdram_reset_n_reg                                                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.167     ; 11.062     ;
; 0.403  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[13]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.165     ; 11.062     ;
; 0.406  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 11.038     ;
; 0.411  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 11.044     ;
; 0.416  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.188     ; 11.026     ;
; 0.419  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[13]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 11.035     ;
; 0.434  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.192     ; 11.004     ;
; 0.436  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 11.018     ;
; 0.436  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                                                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 11.008     ;
; 0.439  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 11.009     ;
; 0.440  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[8]                             ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.194     ; 10.996     ;
; 0.449  ; sdram_reset_n_reg                                                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.177     ; 11.004     ;
; 0.449  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.173     ; 11.008     ;
; 0.452  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.187     ; 10.991     ;
; 0.453  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[11]                                                                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 10.991     ;
; 0.461  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.177     ; 10.992     ;
; 0.469  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[13]                                                                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.185     ; 10.976     ;
; 0.469  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.161     ; 11.000     ;
; 0.473  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[12]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.165     ; 10.992     ;
; 0.473  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[11]                                                                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 10.983     ;
; 0.473  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.192     ; 10.965     ;
; 0.475  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.193     ; 10.962     ;
; 0.482  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[10]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.163     ; 10.985     ;
; 0.490  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.179     ; 10.961     ;
; 0.490  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 10.965     ;
; 0.491  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.193     ; 10.946     ;
; 0.515  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 10.933     ;
; 0.524  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[9]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 10.917     ;
; 0.536  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.177     ; 10.917     ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3]'                                                                                                                                                 ;
+-------+-------------------------+-------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node               ; To Node           ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------+-------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 4.395 ; svideo_yout_dly2[4]     ; cvbs2_out[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.074     ; 4.224      ;
; 4.404 ; svideo_yout_dly2[6]     ; cvbs2_out[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.074     ; 4.215      ;
; 4.466 ; svideo_yout_dly2[2]     ; cvbs2_out[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.074     ; 4.153      ;
; 4.467 ; svideo_yout_dly2[3]     ; cvbs2_out[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.074     ; 4.152      ;
; 4.550 ; svideo_yout_dly2[4]     ; cvbs2_out[2]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 4.068      ;
; 4.559 ; svideo_yout_dly2[6]     ; cvbs2_out[2]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 4.059      ;
; 4.621 ; svideo_yout_dly2[2]     ; cvbs2_out[2]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 3.997      ;
; 4.622 ; svideo_yout_dly2[3]     ; cvbs2_out[2]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 3.996      ;
; 4.695 ; svideo_yout_dly2[4]     ; cvbs2_out[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.076     ; 3.922      ;
; 4.702 ; svideo_yout_dly2[5]     ; cvbs2_out[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.074     ; 3.917      ;
; 4.704 ; svideo_yout_dly2[6]     ; cvbs2_out[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.076     ; 3.913      ;
; 4.721 ; svideo_yout_dly2[7]     ; cvbs2_out[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.074     ; 3.898      ;
; 4.767 ; svideo_yout_dly2[3]     ; cvbs2_out[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.076     ; 3.850      ;
; 4.782 ; svideo_yout_dly2[1]     ; cvbs2_out[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.074     ; 3.837      ;
; 4.784 ; svideo_yout_dly2[4]     ; cvbs2_out[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.077     ; 3.832      ;
; 4.793 ; svideo_yout_dly2[6]     ; cvbs2_out[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.077     ; 3.823      ;
; 4.805 ; svideo_yout_dly2[2]     ; cvbs2_out[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.076     ; 3.812      ;
; 4.806 ; svideo_yout_dly2[4]     ; cvbs2_out[3]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 3.812      ;
; 4.815 ; svideo_yout_dly2[6]     ; cvbs2_out[3]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 3.803      ;
; 4.856 ; svideo_yout_dly2[3]     ; cvbs2_out[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.077     ; 3.760      ;
; 4.857 ; svideo_yout_dly2[5]     ; cvbs2_out[2]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 3.761      ;
; 4.872 ; svideo_yout_dly2[2]     ; cvbs2_out[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.077     ; 3.744      ;
; 4.876 ; svideo_yout_dly2[7]     ; cvbs2_out[2]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 3.742      ;
; 4.878 ; svideo_yout_dly2[3]     ; cvbs2_out[3]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 3.740      ;
; 4.891 ; svideo_yout_dly2[2]     ; cvbs2_out[3]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 3.727      ;
; 4.937 ; svideo_yout_dly2[1]     ; cvbs2_out[2]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 3.681      ;
; 4.941 ; svideo_yout_dly2[4]     ; cvbs2_out[0]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 3.677      ;
; 4.950 ; svideo_yout_dly2[6]     ; cvbs2_out[0]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 3.668      ;
; 4.952 ; svideo_yout_dly2[4]     ; cvbs2_out[1]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 3.666      ;
; 4.959 ; svideo_yout_dly2[6]     ; cvbs2_out[1]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 3.659      ;
; 4.987 ; svideo_yout_dly2[2]     ; cvbs2_out[0]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 3.631      ;
; 4.990 ; svideo_yout_dly2[2]     ; cvbs2_out[1]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 3.628      ;
; 5.002 ; svideo_yout_dly2[5]     ; cvbs2_out[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.076     ; 3.615      ;
; 5.013 ; svideo_yout_dly2[3]     ; cvbs2_out[0]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 3.605      ;
; 5.024 ; svideo_yout_dly2[3]     ; cvbs2_out[1]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 3.594      ;
; 5.060 ; svideo_yout_dly2[7]     ; cvbs2_out[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.076     ; 3.557      ;
; 5.078 ; svideo_yout_dly2[0]     ; cvbs2_out[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.074     ; 3.541      ;
; 5.082 ; svideo_yout_dly2[1]     ; cvbs2_out[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.076     ; 3.535      ;
; 5.091 ; svideo_yout_dly2[5]     ; cvbs2_out[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.077     ; 3.525      ;
; 5.101 ; svideo_yout_dly2[4]     ; cvbs2_out[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.077     ; 3.515      ;
; 5.110 ; svideo_yout_dly2[6]     ; cvbs2_out[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.077     ; 3.506      ;
; 5.113 ; svideo_yout_dly2[5]     ; cvbs2_out[3]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 3.505      ;
; 5.127 ; svideo_yout_dly2[7]     ; cvbs2_out[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.077     ; 3.489      ;
; 5.146 ; svideo_yout_dly2[7]     ; cvbs2_out[3]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 3.472      ;
; 5.171 ; svideo_yout_dly2[1]     ; cvbs2_out[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.077     ; 3.445      ;
; 5.173 ; svideo_yout_dly2[3]     ; cvbs2_out[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.077     ; 3.443      ;
; 5.193 ; svideo_yout_dly2[1]     ; cvbs2_out[3]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 3.425      ;
; 5.201 ; svideo_yout_dly2[2]     ; cvbs2_out[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.077     ; 3.415      ;
; 5.233 ; svideo_yout_dly2[0]     ; cvbs2_out[2]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 3.385      ;
; 5.242 ; svideo_yout_dly2[7]     ; cvbs2_out[0]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 3.376      ;
; 5.245 ; svideo_yout_dly2[7]     ; cvbs2_out[1]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 3.373      ;
; 5.248 ; svideo_yout_dly2[5]     ; cvbs2_out[0]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 3.370      ;
; 5.259 ; svideo_yout_dly2[5]     ; cvbs2_out[1]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 3.359      ;
; 5.328 ; svideo_yout_dly2[1]     ; cvbs2_out[0]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 3.290      ;
; 5.339 ; svideo_yout_dly2[1]     ; cvbs2_out[1]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 3.279      ;
; 5.408 ; svideo_yout_dly2[5]     ; cvbs2_out[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.077     ; 3.208      ;
; 5.417 ; svideo_yout_dly2[0]     ; cvbs2_out[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.076     ; 3.200      ;
; 5.456 ; svideo_yout_dly2[7]     ; cvbs2_out[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.077     ; 3.160      ;
; 5.484 ; svideo_yout_dly2[0]     ; cvbs2_out[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.077     ; 3.132      ;
; 5.488 ; svideo_yout_dly2[1]     ; cvbs2_out[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.077     ; 3.128      ;
; 5.503 ; svideo_yout_dly2[0]     ; cvbs2_out[3]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 3.115      ;
; 5.599 ; svideo_yout_dly2[0]     ; cvbs2_out[0]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 3.019      ;
; 5.602 ; svideo_yout_dly2[0]     ; cvbs2_out[1]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 3.016      ;
; 5.691 ; cvbs1_out[4]            ; cvbs2_out[2]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.073     ; 2.929      ;
; 5.717 ; cvbs1_out[9]            ; cvbs2_out[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.072     ; 2.904      ;
; 5.813 ; svideo_yout_dly2[0]     ; cvbs2_out[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.077     ; 2.803      ;
; 5.900 ; cvbs1_out[2]            ; cvbs2_out[0]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.073     ; 2.720      ;
; 5.923 ; cvbs1_out[7]            ; cvbs2_out[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 2.695      ;
; 5.935 ; cvbs1_out[3]            ; cvbs2_out[1]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.073     ; 2.685      ;
; 5.995 ; svideo:svideo|chroma[1] ; cvbs1_out[8]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.185     ; 2.628      ;
; 6.014 ; svideo:svideo|chroma[1] ; cvbs1_out[9]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.185     ; 2.609      ;
; 6.019 ; svideo:svideo|chroma[0] ; cvbs1_out[9]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.185     ; 2.604      ;
; 6.109 ; svideo:svideo|chroma[2] ; cvbs1_out[9]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.185     ; 2.514      ;
; 6.123 ; svideo:svideo|chroma[3] ; cvbs1_out[8]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.185     ; 2.500      ;
; 6.127 ; svideo:svideo|chroma[1] ; cvbs1_out[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.185     ; 2.496      ;
; 6.134 ; cvbs1_out[5]            ; cvbs2_out[3]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.073     ; 2.486      ;
; 6.142 ; svideo:svideo|chroma[3] ; cvbs1_out[9]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.185     ; 2.481      ;
; 6.146 ; svideo:svideo|chroma[1] ; cvbs1_out[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.185     ; 2.477      ;
; 6.146 ; svideo:svideo|chroma[0] ; cvbs1_out[8]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.185     ; 2.477      ;
; 6.151 ; svideo:svideo|chroma[0] ; cvbs1_out[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.185     ; 2.472      ;
; 6.227 ; svideo:svideo|luma[3]   ; luma_saturated[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.185     ; 2.396      ;
; 6.233 ; svideo:svideo|luma[3]   ; luma_saturated[9] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.185     ; 2.390      ;
; 6.241 ; svideo:svideo|chroma[2] ; cvbs1_out[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.185     ; 2.382      ;
; 6.242 ; cvbs1_out[8]            ; cvbs2_out[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.075     ; 2.376      ;
; 6.247 ; svideo:svideo|chroma[2] ; cvbs1_out[8]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.185     ; 2.376      ;
; 6.251 ; svideo:svideo|chroma[4] ; cvbs1_out[9]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.185     ; 2.372      ;
; 6.255 ; svideo:svideo|chroma[3] ; cvbs1_out[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.185     ; 2.368      ;
; 6.259 ; svideo:svideo|chroma[1] ; cvbs1_out[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.185     ; 2.364      ;
; 6.274 ; svideo:svideo|chroma[3] ; cvbs1_out[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.185     ; 2.349      ;
; 6.278 ; svideo:svideo|chroma[1] ; cvbs1_out[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.185     ; 2.345      ;
; 6.278 ; svideo:svideo|chroma[0] ; cvbs1_out[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.185     ; 2.345      ;
; 6.283 ; svideo:svideo|chroma[0] ; cvbs1_out[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.185     ; 2.340      ;
; 6.294 ; svideo:svideo|chroma[5] ; cvbs1_out[8]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.185     ; 2.329      ;
; 6.313 ; svideo:svideo|chroma[5] ; cvbs1_out[9]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.185     ; 2.310      ;
; 6.339 ; luma_saturated[2]       ; cvbs1_out[9]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.070     ; 2.399      ;
; 6.359 ; svideo:svideo|luma[3]   ; luma_saturated[6] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.185     ; 2.264      ;
; 6.365 ; svideo:svideo|luma[3]   ; luma_saturated[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.185     ; 2.258      ;
; 6.370 ; svideo:svideo|chroma[4] ; cvbs1_out[8]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.185     ; 2.253      ;
; 6.373 ; svideo:svideo|chroma[2] ; cvbs1_out[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.185     ; 2.250      ;
; 6.379 ; svideo:svideo|chroma[2] ; cvbs1_out[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.185     ; 2.244      ;
+-------+-------------------------+-------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'mcc_pll3|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                               ;
+--------+-----------------------------------------------+---------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                     ; To Node                                           ; Launch Clock                                         ; Latch Clock                                          ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------+---------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+
; 25.894 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[7] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[14] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.091     ; 7.336      ;
; 25.900 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[7] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[3]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.091     ; 7.330      ;
; 25.924 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[7] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[6]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.091     ; 7.306      ;
; 25.926 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[7] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[11] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.091     ; 7.304      ;
; 25.927 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[7] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[10] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.091     ; 7.303      ;
; 25.931 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[7] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[5]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.091     ; 7.299      ;
; 25.933 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[7] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[9]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.091     ; 7.297      ;
; 25.934 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[7] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[7]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.091     ; 7.296      ;
; 25.955 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[14] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 7.274      ;
; 25.961 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[3]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 7.268      ;
; 25.985 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[6]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 7.244      ;
; 25.987 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[11] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 7.242      ;
; 25.988 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[10] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 7.241      ;
; 25.992 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[5]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 7.237      ;
; 25.994 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[9]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 7.235      ;
; 25.995 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[7]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 7.234      ;
; 26.048 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[14] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 7.181      ;
; 26.054 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[3]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 7.175      ;
; 26.078 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[6]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 7.151      ;
; 26.080 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[11] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 7.149      ;
; 26.081 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[10] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 7.148      ;
; 26.085 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[5]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 7.144      ;
; 26.087 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[9]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 7.142      ;
; 26.088 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[7]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 7.141      ;
; 26.118 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[0]      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.080     ; 7.123      ;
; 26.118 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[1]      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.080     ; 7.123      ;
; 26.168 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[0]      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.080     ; 7.073      ;
; 26.168 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[1]      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.080     ; 7.073      ;
; 26.184 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[4]      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.080     ; 7.057      ;
; 26.184 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[6]      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.080     ; 7.057      ;
; 26.191 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[14] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.091     ; 7.039      ;
; 26.196 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[3]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.091     ; 7.034      ;
; 26.206 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[7] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[4]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.091     ; 7.024      ;
; 26.210 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[7] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[8]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.091     ; 7.020      ;
; 26.219 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[7] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[1]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.091     ; 7.011      ;
; 26.219 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[2]      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.084     ; 7.018      ;
; 26.220 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[7] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[2]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.091     ; 7.010      ;
; 26.229 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[6]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.091     ; 7.001      ;
; 26.231 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[11] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.091     ; 6.999      ;
; 26.232 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[10] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.091     ; 6.998      ;
; 26.234 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[4]      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.080     ; 7.007      ;
; 26.234 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[6]      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.080     ; 7.007      ;
; 26.236 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[5]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.091     ; 6.994      ;
; 26.238 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[9]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.091     ; 6.992      ;
; 26.239 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[7]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.091     ; 6.991      ;
; 26.241 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[14] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.091     ; 6.989      ;
; 26.246 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[3]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.091     ; 6.984      ;
; 26.267 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[4]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 6.962      ;
; 26.271 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[8]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 6.958      ;
; 26.280 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[1]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 6.949      ;
; 26.281 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[2]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 6.948      ;
; 26.283 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[2]      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.084     ; 6.954      ;
; 26.289 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[6]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.091     ; 6.941      ;
; 26.291 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[11] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.091     ; 6.939      ;
; 26.292 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[10] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.091     ; 6.938      ;
; 26.294 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[5]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.091     ; 6.936      ;
; 26.296 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[9]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.091     ; 6.934      ;
; 26.297 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[7]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.091     ; 6.933      ;
; 26.302 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[14] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.091     ; 6.928      ;
; 26.308 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[3]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.091     ; 6.922      ;
; 26.329 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[0]      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.081     ; 6.911      ;
; 26.329 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[1]      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.081     ; 6.911      ;
; 26.332 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[6]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.091     ; 6.898      ;
; 26.334 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[11] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.091     ; 6.896      ;
; 26.335 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[10] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.091     ; 6.895      ;
; 26.339 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[5]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.091     ; 6.891      ;
; 26.341 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[9]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.091     ; 6.889      ;
; 26.342 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[7]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.091     ; 6.888      ;
; 26.360 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[4]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 6.869      ;
; 26.364 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[8]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 6.865      ;
; 26.373 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[1]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 6.856      ;
; 26.374 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[2]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.092     ; 6.855      ;
; 26.384 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[6] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[14] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.091     ; 6.846      ;
; 26.386 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[7] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[13] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.080     ; 6.855      ;
; 26.390 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[6] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[3]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.091     ; 6.840      ;
; 26.395 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[4]      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.081     ; 6.845      ;
; 26.395 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[6]      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.081     ; 6.845      ;
; 26.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[6] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[6]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.091     ; 6.816      ;
; 26.416 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[6] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[11] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.091     ; 6.814      ;
; 26.417 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[6] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[10] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.091     ; 6.813      ;
; 26.421 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[6] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[5]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.091     ; 6.809      ;
; 26.423 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[6] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[9]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.091     ; 6.807      ;
; 26.424 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[6] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[7]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.091     ; 6.806      ;
; 26.431 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[2]      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.085     ; 6.805      ;
; 26.447 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[13] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.081     ; 6.793      ;
; 26.450 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[0]      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.080     ; 6.791      ;
; 26.450 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[1]      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.080     ; 6.791      ;
; 26.485 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[5] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[0]      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.115     ; 6.721      ;
; 26.485 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[5] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[1]      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.115     ; 6.721      ;
; 26.511 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[4]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.091     ; 6.719      ;
; 26.515 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[8]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.091     ; 6.715      ;
; 26.516 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[4]      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.080     ; 6.725      ;
; 26.516 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[6]      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.080     ; 6.725      ;
; 26.524 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[1]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.091     ; 6.706      ;
; 26.525 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[2]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.091     ; 6.705      ;
; 26.540 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[13] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.081     ; 6.700      ;
; 26.566 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[0]      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.081     ; 6.674      ;
; 26.566 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[1]      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.081     ; 6.674      ;
; 26.575 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[4]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.091     ; 6.655      ;
; 26.579 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[8]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.091     ; 6.651      ;
+--------+-----------------------------------------------+---------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'altera_reserved_tck'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                        ; To Node                                                                                                                                                                                                               ; Launch Clock        ; Latch Clock         ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; 45.292 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.172      ; 4.878      ;
; 45.581 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                                                   ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.172      ; 4.589      ;
; 45.777 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.172      ; 4.393      ;
; 45.796 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]                                              ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.173      ; 4.375      ;
; 45.948 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.172      ; 4.222      ;
; 46.207 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.184      ; 3.975      ;
; 46.218 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.185      ; 3.965      ;
; 46.265 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2]                                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.174      ; 3.907      ;
; 46.267 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.174      ; 3.905      ;
; 46.325 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.184      ; 3.857      ;
; 46.359 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]                                              ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.181      ; 3.820      ;
; 46.646 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.184      ; 3.536      ;
; 46.785 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.174      ; 3.387      ;
; 46.965 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.173      ; 3.206      ;
; 46.987 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                                                   ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.176      ; 3.187      ;
; 47.042 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.174      ; 3.130      ;
; 47.234 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.174      ; 2.938      ;
; 47.245 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.183      ; 2.936      ;
; 47.669 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.183      ; 2.512      ;
; 47.826 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.172      ; 2.344      ;
; 47.998 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[0]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.183      ; 2.183      ;
; 48.013 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg                                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.182      ; 2.167      ;
; 48.349 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[0]                                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.182      ; 1.831      ;
; 48.511 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[0]                                                                                                                               ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.182      ; 1.669      ;
; 95.134 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.351     ; 4.513      ;
; 95.153 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.352     ; 4.493      ;
; 95.171 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.352     ; 4.475      ;
; 95.186 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.352     ; 4.460      ;
; 95.263 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.352     ; 4.383      ;
; 95.296 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[5]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.352     ; 4.350      ;
; 95.297 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[5]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.352     ; 4.349      ;
; 95.322 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[6]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.352     ; 4.324      ;
; 95.344 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.352     ; 4.302      ;
; 95.348 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.352     ; 4.298      ;
; 95.422 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 4.515      ;
; 95.422 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[6]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 4.515      ;
; 95.422 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[5]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 4.515      ;
; 95.422 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 4.515      ;
; 95.422 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 4.515      ;
; 95.422 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 4.515      ;
; 95.422 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 4.515      ;
; 95.452 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[6]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.352     ; 4.194      ;
; 95.472 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.356     ; 4.170      ;
; 95.499 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.059     ; 4.440      ;
; 95.499 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.059     ; 4.440      ;
; 95.499 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.059     ; 4.440      ;
; 95.499 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.059     ; 4.440      ;
; 95.499 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.059     ; 4.440      ;
; 95.509 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.356     ; 4.133      ;
; 95.618 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.356     ; 4.024      ;
; 95.638 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.067     ; 4.293      ;
; 95.638 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.067     ; 4.293      ;
; 95.638 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.067     ; 4.293      ;
; 95.638 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.067     ; 4.293      ;
; 95.638 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.067     ; 4.293      ;
; 95.639 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 4.298      ;
; 95.639 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 4.298      ;
; 95.639 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 4.298      ;
; 95.639 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 4.298      ;
; 95.639 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 4.298      ;
; 95.648 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.060     ; 4.290      ;
; 95.655 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3]                                                                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.079     ; 4.264      ;
; 95.655 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2]                                                                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.079     ; 4.264      ;
; 95.655 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1]                                                                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.079     ; 4.264      ;
; 95.655 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0]                                                                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.079     ; 4.264      ;
; 95.663 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.356     ; 3.979      ;
; 95.675 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.071     ; 4.252      ;
; 95.675 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0                                                                                                                                        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.071     ; 4.252      ;
; 95.698 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.071     ; 4.229      ;
; 95.698 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.071     ; 4.229      ;
; 95.698 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.071     ; 4.229      ;
; 95.698 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.071     ; 4.229      ;
; 95.724 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[3]      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.071     ; 4.203      ;
; 95.724 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[2]      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.071     ; 4.203      ;
; 95.724 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[1]      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.071     ; 4.203      ;
; 95.724 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[0]      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.071     ; 4.203      ;
; 95.736 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.078     ; 4.184      ;
; 95.736 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.078     ; 4.184      ;
; 95.736 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.078     ; 4.184      ;
; 95.736 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.078     ; 4.184      ;
; 95.736 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.078     ; 4.184      ;
; 95.771 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4]                                                                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.079     ; 4.148      ;
; 95.800 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.074     ; 4.124      ;
; 95.800 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.074     ; 4.124      ;
; 95.800 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.074     ; 4.124      ;
; 95.800 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.074     ; 4.124      ;
; 95.800 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.074     ; 4.124      ;
; 95.803 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.059     ; 4.136      ;
; 95.803 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.059     ; 4.136      ;
; 95.803 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.059     ; 4.136      ;
; 95.803 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.059     ; 4.136      ;
; 95.803 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.059     ; 4.136      ;
; 95.814 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.356     ; 3.828      ;
; 95.849 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3]                                                                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.079     ; 4.070      ;
; 95.849 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2]                                                                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.079     ; 4.070      ;
; 95.849 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1]                                                                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.079     ; 4.070      ;
; 95.849 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0]                                                                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.079     ; 4.070      ;
; 95.902 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[3]      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.071     ; 4.025      ;
; 95.921 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[3]                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.077     ; 4.000      ;
; 95.921 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[2]                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.077     ; 4.000      ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3]'                                                                                                                                                            ;
+-------+---------------------------+---------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                 ; To Node                   ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------+---------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 0.355 ; svideo:svideo|luma[8]     ; svideo:svideo|luma_1[8]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.159      ; 0.718      ;
; 0.355 ; svideo:svideo|luma[9]     ; svideo:svideo|luma_1[9]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.159      ; 0.718      ;
; 0.439 ; svideo_yout_dly1[1]       ; svideo_yout_dly2[1]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.695      ;
; 0.440 ; svideo_yout_dly1[4]       ; svideo_yout_dly2[4]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.696      ;
; 0.440 ; svideo_yout_dly1[3]       ; svideo_yout_dly2[3]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.696      ;
; 0.443 ; svideo:svideo|luma_1[9]   ; svideo:svideo|luma_2[9]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.069      ; 0.698      ;
; 0.504 ; svideo:svideo|luma[5]     ; svideo:svideo|luma_1[5]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.157      ; 0.865      ;
; 0.525 ; svideo:svideo|luma[6]     ; svideo:svideo|luma_1[6]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.159      ; 0.888      ;
; 0.526 ; svideo:svideo|luma[7]     ; svideo:svideo|luma_1[7]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.159      ; 0.889      ;
; 0.527 ; svideo:svideo|luma[9]     ; luma_saturated[9]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.159      ; 0.890      ;
; 0.527 ; svideo:svideo|luma[4]     ; svideo:svideo|luma_1[4]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.159      ; 0.890      ;
; 0.548 ; svideo:svideo|luma[1]     ; svideo:svideo|luma_1[1]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.159      ; 0.911      ;
; 0.562 ; svideo:svideo|luma[2]     ; luma_saturated[2]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.159      ; 0.925      ;
; 0.567 ; svideo:svideo|luma[6]     ; luma_saturated[6]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.159      ; 0.930      ;
; 0.578 ; svideo:svideo|luma[0]     ; luma_saturated[1]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.159      ; 0.941      ;
; 0.579 ; svideo:svideo|luma[1]     ; luma_saturated[1]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.159      ; 0.942      ;
; 0.604 ; svideo:svideo|luma_acc[7] ; svideo_yout_dly1[5]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.860      ;
; 0.606 ; svideo:svideo|luma_1[3]   ; svideo:svideo|luma_2[3]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.862      ;
; 0.609 ; svideo:svideo|luma_1[0]   ; svideo:svideo|luma_2[0]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.865      ;
; 0.609 ; svideo:svideo|luma_1[4]   ; svideo:svideo|luma_2[4]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.865      ;
; 0.610 ; svideo_yout_dly1[5]       ; svideo_yout_dly2[5]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.866      ;
; 0.611 ; svideo:svideo|luma_1[8]   ; svideo:svideo|luma_2[8]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.069      ; 0.866      ;
; 0.611 ; svideo_yout_dly1[6]       ; svideo_yout_dly2[6]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.867      ;
; 0.611 ; svideo_yout_dly1[2]       ; svideo_yout_dly2[2]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.867      ;
; 0.613 ; luma_saturated[9]         ; cvbs1_out[9]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.069      ; 0.868      ;
; 0.613 ; svideo_yout_dly1[7]       ; svideo_yout_dly2[7]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.869      ;
; 0.613 ; svideo_yout_dly1[0]       ; svideo_yout_dly2[0]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.869      ;
; 0.630 ; svideo:svideo|luma_1[6]   ; svideo:svideo|luma_2[6]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.886      ;
; 0.630 ; svideo:svideo|luma_1[7]   ; svideo:svideo|luma_2[7]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.886      ;
; 0.631 ; svideo:svideo|luma_acc[8] ; svideo_yout_dly1[6]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.887      ;
; 0.634 ; svideo:svideo|luma_1[2]   ; svideo:svideo|luma_2[2]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.890      ;
; 0.644 ; svideo:svideo|luma[0]     ; luma_saturated[0]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.159      ; 1.007      ;
; 0.648 ; svideo:svideo|luma_2[7]   ; svideo:svideo|luma_acc[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.904      ;
; 0.648 ; svideo:svideo|luma_2[6]   ; svideo:svideo|luma_acc[6] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.904      ;
; 0.649 ; svideo:svideo|luma_acc[1] ; svideo:svideo|luma_acc[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.905      ;
; 0.649 ; svideo:svideo|luma_2[2]   ; svideo:svideo|luma_acc[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.905      ;
; 0.650 ; svideo:svideo|luma_2[4]   ; svideo:svideo|luma_acc[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.906      ;
; 0.663 ; svideo:svideo|luma_acc[0] ; svideo:svideo|luma_acc[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.919      ;
; 0.667 ; svideo:svideo|luma_2[0]   ; svideo:svideo|luma_acc[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 0.923      ;
; 0.699 ; svideo:svideo|luma[0]     ; svideo:svideo|luma_1[0]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.159      ; 1.062      ;
; 0.714 ; svideo:svideo|luma[4]     ; luma_saturated[4]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.159      ; 1.077      ;
; 0.714 ; svideo:svideo|luma[5]     ; luma_saturated[5]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.157      ; 1.075      ;
; 0.724 ; svideo:svideo|luma[7]     ; luma_saturated[7]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.159      ; 1.087      ;
; 0.728 ; svideo:svideo|luma[8]     ; luma_saturated[8]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.159      ; 1.091      ;
; 0.729 ; svideo:svideo|luma[2]     ; svideo:svideo|luma_1[2]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.159      ; 1.092      ;
; 0.775 ; svideo:svideo|luma_acc[9] ; svideo_yout_dly1[7]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.031      ;
; 0.778 ; svideo:svideo|luma_acc[4] ; svideo_yout_dly1[2]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.034      ;
; 0.805 ; luma_saturated[6]         ; cvbs1_out[6]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.069      ; 1.060      ;
; 0.805 ; luma_saturated[4]         ; cvbs1_out[4]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.069      ; 1.060      ;
; 0.810 ; svideo:svideo|luma_acc[6] ; svideo_yout_dly1[4]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.066      ;
; 0.811 ; svideo:svideo|luma_2[3]   ; svideo:svideo|luma_acc[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.067      ;
; 0.811 ; svideo:svideo|luma_acc[5] ; svideo_yout_dly1[3]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.067      ;
; 0.812 ; svideo:svideo|luma_1[1]   ; svideo:svideo|luma_2[1]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.068      ;
; 0.812 ; svideo:svideo|luma_acc[3] ; svideo_yout_dly1[1]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.068      ;
; 0.814 ; luma_saturated[3]         ; cvbs1_out[3]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.069      ; 1.069      ;
; 0.815 ; svideo:svideo|luma_2[1]   ; svideo:svideo|luma_acc[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.071      ;
; 0.817 ; svideo:svideo|luma_1[5]   ; svideo:svideo|luma_2[5]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.073      ;
; 0.833 ; svideo:svideo|luma_acc[2] ; svideo_yout_dly1[0]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.089      ;
; 0.849 ; luma_saturated[7]         ; cvbs1_out[7]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.069      ; 1.104      ;
; 0.849 ; luma_saturated[8]         ; cvbs1_out[8]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.069      ; 1.104      ;
; 0.849 ; luma_saturated[5]         ; cvbs1_out[5]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.069      ; 1.104      ;
; 0.858 ; svideo:svideo|luma_2[5]   ; svideo:svideo|luma_acc[5] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.114      ;
; 0.860 ; svideo:svideo|luma_2[8]   ; svideo:svideo|luma_acc[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.116      ;
; 0.862 ; svideo:svideo|luma_2[9]   ; svideo:svideo|luma_acc[9] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.118      ;
; 0.879 ; svideo:svideo|luma[2]     ; luma_saturated[3]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.159      ; 1.242      ;
; 0.881 ; svideo:svideo|luma[6]     ; luma_saturated[7]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.159      ; 1.244      ;
; 0.888 ; svideo:svideo|luma[0]     ; luma_saturated[2]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.159      ; 1.251      ;
; 0.892 ; svideo:svideo|luma[1]     ; luma_saturated[2]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.159      ; 1.255      ;
; 0.893 ; svideo:svideo|luma[0]     ; luma_saturated[3]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.159      ; 1.256      ;
; 0.897 ; svideo:svideo|luma[1]     ; luma_saturated[3]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.159      ; 1.260      ;
; 0.963 ; svideo:svideo|luma_acc[1] ; svideo:svideo|luma_acc[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.219      ;
; 0.965 ; svideo:svideo|luma_2[7]   ; svideo:svideo|luma_acc[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.221      ;
; 0.975 ; svideo:svideo|luma_2[6]   ; svideo:svideo|luma_acc[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.231      ;
; 0.976 ; svideo:svideo|luma_acc[0] ; svideo:svideo|luma_acc[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.232      ;
; 0.976 ; svideo:svideo|luma_2[2]   ; svideo:svideo|luma_acc[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.232      ;
; 0.977 ; svideo:svideo|luma_2[4]   ; svideo:svideo|luma_acc[5] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.233      ;
; 0.977 ; svideo:svideo|luma_2[0]   ; svideo:svideo|luma_acc[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.233      ;
; 0.980 ; svideo:svideo|luma_2[6]   ; svideo:svideo|luma_acc[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.236      ;
; 0.981 ; svideo:svideo|luma_2[2]   ; svideo:svideo|luma_acc[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.237      ;
; 0.981 ; svideo:svideo|luma_acc[0] ; svideo:svideo|luma_acc[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.237      ;
; 0.982 ; svideo:svideo|luma_2[4]   ; svideo:svideo|luma_acc[6] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.238      ;
; 0.982 ; svideo:svideo|luma_2[0]   ; svideo:svideo|luma_acc[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.070      ; 1.238      ;
; 0.983 ; svideo:svideo|chroma[6]   ; cvbs1_out[6]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.156      ; 1.343      ;
; 0.996 ; svideo:svideo|luma[3]     ; svideo:svideo|luma_1[3]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.157      ; 1.357      ;
; 1.000 ; svideo:svideo|luma[2]     ; luma_saturated[4]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.159      ; 1.363      ;
; 1.002 ; svideo:svideo|luma[6]     ; luma_saturated[8]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.159      ; 1.365      ;
; 1.005 ; svideo:svideo|luma[2]     ; luma_saturated[5]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.159      ; 1.368      ;
; 1.007 ; svideo:svideo|luma[6]     ; luma_saturated[9]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.159      ; 1.370      ;
; 1.014 ; svideo:svideo|luma[0]     ; luma_saturated[4]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.159      ; 1.377      ;
; 1.018 ; svideo:svideo|chroma[5]   ; cvbs1_out[5]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.156      ; 1.378      ;
; 1.018 ; svideo:svideo|luma[1]     ; luma_saturated[4]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.159      ; 1.381      ;
; 1.019 ; svideo:svideo|luma[0]     ; luma_saturated[5]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.159      ; 1.382      ;
; 1.021 ; svideo:svideo|chroma[4]   ; cvbs1_out[4]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.156      ; 1.381      ;
; 1.023 ; svideo:svideo|luma[1]     ; luma_saturated[5]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.159      ; 1.386      ;
; 1.023 ; luma_saturated[2]         ; cvbs1_out[2]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.069      ; 1.278      ;
; 1.030 ; svideo:svideo|chroma[2]   ; cvbs1_out[2]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.156      ; 1.390      ;
; 1.032 ; svideo:svideo|luma[4]     ; luma_saturated[5]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.159      ; 1.395      ;
; 1.043 ; svideo:svideo|luma[3]     ; luma_saturated[3]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.157      ; 1.404      ;
; 1.044 ; svideo:svideo|luma[5]     ; luma_saturated[6]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.157      ; 1.405      ;
; 1.044 ; svideo:svideo|luma[8]     ; luma_saturated[9]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.159      ; 1.407      ;
+-------+---------------------------+---------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                       ; To Node                                                                                                                                                                                                                                   ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 0.380 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|sizep0_raw_reg[0]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a0~porta_datain_reg0     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.431      ; 1.033      ;
; 0.385 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|cntr_pqf:cntr1|counter_reg_bit[4] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a0~portb_address_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.430      ; 1.037      ;
; 0.385 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|cntr_pqf:cntr1|counter_reg_bit[4] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a0~porta_address_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.429      ; 1.036      ;
; 0.386 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_raw_reg[5]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a8~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.431      ; 1.039      ;
; 0.388 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_raw_reg[6]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a8~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.427      ; 1.037      ;
; 0.388 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_raw_reg[4]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a8~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.427      ; 1.037      ;
; 0.389 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_raw_reg[7]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.431      ; 1.042      ;
; 0.396 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[7]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.427      ; 1.045      ;
; 0.396 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_raw_reg[5]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.431      ; 1.049      ;
; 0.396 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|sizem_raw_reg[5]                                                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a0~porta_datain_reg0     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.426      ; 1.044      ;
; 0.398 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[2]                                                                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[2]                                                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.085      ; 0.669      ;
; 0.399 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp0_raw_reg[0]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.425      ; 1.046      ;
; 0.399 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_raw_reg[1]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a8~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.427      ; 1.048      ;
; 0.399 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|sizep0_raw_reg[1]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a0~porta_datain_reg0     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.431      ; 1.052      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_raw_reg[3]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.431      ; 1.055      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|cntr_pqf:cntr1|counter_reg_bit[3] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a0~portb_address_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.430      ; 1.055      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|cntr_pqf:cntr1|counter_reg_bit[3] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a0~porta_address_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.429      ; 1.054      ;
; 0.404 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|sizem_raw_reg[4]                                                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a0~porta_datain_reg0     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.426      ; 1.052      ;
; 0.405 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_raw_reg[0]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a8~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.431      ; 1.058      ;
; 0.407 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_raw_reg[3]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.426      ; 1.055      ;
; 0.409 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[4]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.427      ; 1.058      ;
; 0.409 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_raw_reg[0]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a8~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.431      ; 1.062      ;
; 0.409 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_raw_reg[6]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a8~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.426      ; 1.057      ;
; 0.410 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[1]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.432      ; 1.064      ;
; 0.411 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_raw_reg[4]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.431      ; 1.064      ;
; 0.412 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_load2                                                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_load2                                                                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|idim_r                                                                                                                                                    ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|idim_r                                                                                                                                                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[1]                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[1]                                                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[0]                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[0]                                                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[2]                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[2]                                                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[3]                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[3]                                                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[6]                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[6]                                                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[4]                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[4]                                                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[5]                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[5]                                                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[7]                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[7]                                                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[2]                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[2]                                                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[3]                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[3]                                                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[6]                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[6]                                                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[4]                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[4]                                                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[5]                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[5]                                                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[7]                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[7]                                                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[6]                                                                                                                                                    ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[6]                                                                                                                                                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|spi_speed_reg[7]                                                                                                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|spi_speed_reg[7]                                                                                                                                                                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|irqst_reg[1]                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|irqst_reg[1]                                                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[7]                                                                                                                                                    ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[7]                                                                                                                                                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serial_ip_framing_reg                                                                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serial_ip_framing_reg                                                                                                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_fetch                                                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_fetch                                                                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|irqst_reg[2]                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|irqst_reg[2]                                                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|irqst_reg[0]                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|irqst_reg[0]                                                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_loadb2                                                                                                                                           ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_loadb2                                                                                                                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[3]                                                                                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[3]                                                                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|oss_bank[0]                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|oss_bank[0]                                                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|oss_bank[1]                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|oss_bank[1]                                                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|count_reg[1]                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|count_reg[1]                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[6]                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[6]                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf2_reg[0]                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf2_reg[0]                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf2_reg[1]                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf2_reg[1]                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf2_reg[6]                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf2_reg[6]                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf2_reg[2]                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf2_reg[2]                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf2_reg[3]                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf2_reg[3]                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf2_reg[4]                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf2_reg[4]                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf2_reg[5]                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf2_reg[5]                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf2_reg[7]                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf2_reg[7]                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf3_reg[1]                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf3_reg[1]                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf3_reg[4]                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf3_reg[4]                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf3_reg[7]                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf3_reg[7]                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf0_reg[7]                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf0_reg[7]                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0]                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer1|delay_line:underflow0_delay|shift_reg[0]                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer1|delay_line:underflow0_delay|shift_reg[0]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_raw_reg[3]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a8~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.431      ; 1.065      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_raw_reg[2]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a8~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.427      ; 1.061      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0]                                                                                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0]                                                                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.413 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_add_sp2                                                                                                                                          ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_add_sp2                                                                                                                                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[22]                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[22]                                                                                                                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[30]                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[30]                                                                                                                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[29]                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[29]                                                                                                                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[14]                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[14]                                                                                                                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[18]                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[18]                                                                                                                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[21]                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[21]                                                                                                                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[20]                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[20]                                                                                                                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[19]                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[19]                                                                                                                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[25]                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[25]                                                                                                                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[5]                                                                                                                                                                 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[5]                                                                                                                                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[6]                                                                                                                                                                 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[6]                                                                                                                                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[2]                                                                                                                                                                 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[2]                                                                                                                                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[1]                                                                                                                                                      ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[1]                                                                                                                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[2]                                                                                                                                                      ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[2]                                                                                                                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[3]                                                                                                                                                      ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[3]                                                                                                                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|skctl_reg[1]                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|skctl_reg[1]                                                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[0]                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[0]                                                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[2]                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[2]                                                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[1]                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[1]                                                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[3]                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[3]                                                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[7]                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[7]                                                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[4]                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[4]                                                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[5]                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[5]                                                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[6]                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[6]                                                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0]                                                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[0]                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[0]                                                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[3]                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[3]                                                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.669      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'mcc_pll3|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                       ;
+-------+---------------------------------------------------------------------+---------------------------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                           ; To Node                                                             ; Launch Clock                                         ; Latch Clock                                          ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------+---------------------------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+
; 0.412 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state1                  ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state1                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state2                  ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state2                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[2]                       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[2]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[1]                       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[1]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.413 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_send_com.Idle                  ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_send_com.Idle                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_send_com.reset_start           ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_send_com.reset_start           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|send_frame                         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|send_frame                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[6]                     ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[6]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[7]                     ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[7]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[4]                     ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[4]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[5]                     ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[5]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; cntr_reset[1]                                                       ; cntr_reset[1]                                                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; cntr_reset[2]                                                       ; cntr_reset[2]                                                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; cntr_reset[5]                                                       ; cntr_reset[5]                                                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; cntr_reset[6]                                                       ; cntr_reset[6]                                                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; reset_usbdrv                                                        ; reset_usbdrv                                                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[2]                       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[2]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[3]                       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[3]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3]                       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[0]                       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[0]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[1]                       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[1]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1]                       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|val                                ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|val                                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|read_byte_valid                    ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|read_byte_valid                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[0]                         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[0]                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state3                  ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state3                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[2]                         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[2]                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[3]                         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[3]                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[0]                       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[0]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[4]                       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[4]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[2]                       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[2]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[3]                       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[3]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[3]                       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[3]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[5]                       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[5]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[1]                       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[1]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[7]                       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[7]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[6]                       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[6]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state4                  ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state4                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|stuffin1[2]                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|stuffin1[2]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|stuffin1[1]                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|stuffin1[1]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[1]                         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[1]                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|val                                ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|val                                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|read_byte_valid                    ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|read_byte_valid                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|send_frame                         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|send_frame                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte2         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte2         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte3         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte3         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte4         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte4         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte5         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte5         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte6         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte6         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte7         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte7         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte8         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte8         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[0]                     ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[0]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[3]                     ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[3]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[2]                     ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[2]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[1]                     ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[1]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|dp_previous                        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|dp_previous                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|dm_previous                        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|dm_previous                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state2                  ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state2                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state4                  ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state4                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|stuffin1[1]                        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|stuffin1[1]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|stuffin1[2]                        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|stuffin1[2]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[2]                         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[2]                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state1                  ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state1                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state3                  ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state3                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[0]                         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[0]                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[1]                         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[1]                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[3]                         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[3]                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[6]                       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[6]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2]                       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4]                       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5]                       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[7]                       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[7]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.Idle                  ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.Idle                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.reset_start           ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.reset_start           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[4]                     ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[4]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[5]                     ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[5]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[0]                     ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[0]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[1]                     ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[1]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[3]                     ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[3]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[2]                     ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[2]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[7]                     ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[7]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[6]                     ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[6]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dp_previous                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dp_previous                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dm_previous                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dm_previous                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.start_get_data          ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.start_get_data          ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte9         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte9         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte10        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte10        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|read_byte_valid_c                  ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|read_byte_valid_c                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait2                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait2                   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.setaddress_sendpkt1_end ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.setaddress_sendpkt1_end ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte11        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte11        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.Idle                    ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.Idle                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|set_command[0]                     ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|set_command[0]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.end_set_address         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.end_set_address         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait4                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait4                   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.setaddress_sendpkt3_end ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.setaddress_sendpkt3_end ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_pktin2             ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_pktin2             ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait6                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait6                   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.end_set_configuration   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.end_set_configuration   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|set_command[1]                     ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|set_command[1]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
+-------+---------------------------------------------------------------------+---------------------------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                              ;
+-------+-----------------------------------------------------------------------------------------------------------------+-------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                       ; To Node                                               ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------+-------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 0.413 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                                      ; sdram_ctrl:sdram_controller|r_init_tmr[10]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.414 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[0]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                           ; sdram_ctrl:sdram_controller|sdram_rdy                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; sdram_ctrl:sdram_controller|r_wr_act                                                                            ; sdram_ctrl:sdram_controller|r_wr_act                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                                                                        ; sdram_ctrl:sdram_controller|r_bst_stp[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_rd_bctr[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; sdram_ctrl:sdram_controller|r_rd_act                                                                            ; sdram_ctrl:sdram_controller|r_rd_act                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; sdram_ctrl:sdram_controller|r_refr_act                                                                          ; sdram_ctrl:sdram_controller|r_refr_act                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.418 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[0]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.674      ;
; 0.573 ; sdram_ctrl:sdram_controller|r_rd_act                                                                            ; sdram_ctrl:sdram_controller|ap1_rd_bst_act            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.828      ;
; 0.600 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_rd_act                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.855      ;
; 0.602 ; sdram_ctrl:sdram_controller|r_psel_dly[0]                                                                       ; sdram_ctrl:sdram_controller|ap1_rd_bst_act            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.857      ;
; 0.639 ; seq_reg[6]                                                                                                      ; seq_reg[7]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.895      ;
; 0.641 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_wr_act                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.896      ;
; 0.642 ; seq_reg[5]                                                                                                      ; seq_reg[6]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.898      ;
; 0.642 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[25] ; ram_di_reg[9]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 1.006      ;
; 0.644 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.900      ;
; 0.644 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.900      ;
; 0.644 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[23] ; ram_di_reg[7]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 1.007      ;
; 0.645 ; seq_reg[11]                                                                                                     ; sdram_ctrl:sdram_controller|r_init_fsm[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.900      ;
; 0.645 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[21] ; ram_di_reg[5]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 1.008      ;
; 0.646 ; seq_reg[11]                                                                                                     ; sdram_ctrl:sdram_controller|r_init_fsm[0]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.901      ;
; 0.646 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[16] ; ram_di_reg[0]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 1.010      ;
; 0.646 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[18] ; ram_di_reg[2]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 1.010      ;
; 0.647 ; seq_reg[4]                                                                                                      ; seq_reg[5]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.903      ;
; 0.647 ; seq_reg[9]                                                                                                      ; seq_reg[10]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.903      ;
; 0.647 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.903      ;
; 0.647 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.903      ;
; 0.649 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.905      ;
; 0.649 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.905      ;
; 0.650 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.906      ;
; 0.650 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.906      ;
; 0.650 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                                                                        ; sdram_ctrl:sdram_controller|r_rd_bctr[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.905      ;
; 0.657 ; seq_reg[1]                                                                                                      ; seq_reg[2]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.913      ;
; 0.663 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.919      ;
; 0.663 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.919      ;
; 0.705 ; sdram_ctrl:sdram_controller|r_rd_act                                                                            ; sdram_ctrl:sdram_controller|r_rd_bctr[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.960      ;
; 0.746 ; sdram_ctrl:sdram_controller|r_refr_act                                                                          ; sdram_ctrl:sdram_controller|r_rd_reg                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.001      ;
; 0.755 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.010      ;
; 0.759 ; sdram_ctrl:sdram_controller|r_refr_act                                                                          ; sdram_ctrl:sdram_controller|r_wr_reg                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.014      ;
; 0.760 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[0]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.015      ;
; 0.780 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[24] ; ram_di_reg[8]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 1.144      ;
; 0.785 ; seq_reg[10]                                                                                                     ; seq_reg[11]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.040      ;
; 0.810 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[1]  ; ram_di_reg[1]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 1.174      ;
; 0.856 ; seq_reg[7]                                                                                                      ; seq_reg[8]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.111      ;
; 0.864 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[20] ; ram_di_reg[4]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 1.228      ;
; 0.864 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[22] ; ram_di_reg[6]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 1.228      ;
; 0.865 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[26] ; ram_di_reg[10]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 1.229      ;
; 0.865 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[27] ; ram_di_reg[11]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.160      ; 1.230      ;
; 0.867 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[30] ; ram_di_reg[14]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 1.231      ;
; 0.867 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[31] ; ram_di_reg[15]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 1.230      ;
; 0.867 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[17] ; ram_di_reg[1]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 1.231      ;
; 0.875 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[28] ; ram_di_reg[12]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 1.239      ;
; 0.882 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[19] ; ram_di_reg[3]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 1.245      ;
; 0.885 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[29] ; ram_di_reg[13]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 1.248      ;
; 0.889 ; seq_reg[10]                                                                                                     ; sdram_ctrl:sdram_controller|sdram_rdy                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.144      ;
; 0.899 ; sdram_ctrl:sdram_controller|r_wr_act                                                                            ; sdram_ctrl:sdram_controller|r_wr_bctr[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.154      ;
; 0.902 ; seq_reg[11]                                                                                                     ; sdram_ctrl:sdram_controller|r_init_fsm[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.157      ;
; 0.904 ; sdram_ctrl:sdram_controller|r_rd_reg                                                                            ; sdram_ctrl:sdram_controller|r_rd_act                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.160      ;
; 0.962 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.218      ;
; 0.962 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.218      ;
; 0.964 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.220      ;
; 0.964 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.220      ;
; 0.973 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.229      ;
; 0.976 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.232      ;
; 0.976 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.232      ;
; 0.977 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.233      ;
; 0.977 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.233      ;
; 0.978 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.234      ;
; 0.981 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.237      ;
; 0.981 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.237      ;
; 0.982 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.238      ;
; 0.982 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.238      ;
; 0.983 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[8]  ; ram_di_reg[8]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 1.347      ;
; 0.983 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[12] ; ram_di_reg[12]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 1.347      ;
; 0.983 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[15] ; ram_di_reg[15]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 1.346      ;
; 0.984 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[13] ; ram_di_reg[13]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 1.347      ;
; 0.987 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[2]  ; ram_di_reg[2]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 1.351      ;
; 1.013 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                                       ; sdram_ctrl:sdram_controller|sdram_rdy                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.268      ;
; 1.030 ; seq_reg[8]                                                                                                      ; seq_reg[9]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.286      ;
; 1.040 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg          ; sdram_ctrl:sdram_controller|r_refr_req                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 1.407      ;
; 1.066 ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1                                                           ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.321      ;
; 1.068 ; sdram_ctrl:sdram_controller|r_refr_req                                                                          ; sdram_ctrl:sdram_controller|r_rd_reg                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.324      ;
; 1.068 ; sdram_ctrl:sdram_controller|r_refr_req                                                                          ; sdram_ctrl:sdram_controller|r_wr_reg                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.324      ;
; 1.083 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.339      ;
; 1.085 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.341      ;
; 1.085 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.341      ;
; 1.087 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.342      ;
; 1.088 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.344      ;
; 1.089 ; seq_reg[2]                                                                                                      ; seq_reg[3]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.345      ;
; 1.090 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.346      ;
; 1.090 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.346      ;
; 1.099 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.355      ;
; 1.102 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.358      ;
; 1.103 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.359      ;
; 1.103 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.359      ;
; 1.104 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.360      ;
; 1.107 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.363      ;
+-------+-----------------------------------------------------------------------------------------------------------------+-------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'altera_reserved_tck'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                          ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                             ; To Node                                                                                                                                                                                                               ; Launch Clock        ; Latch Clock         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2]                                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]                                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg                                                                                                                                          ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg                                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.070      ; 0.669      ;
; 0.414 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1]                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1]                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2]                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2]                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0]                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1]                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6]                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11]                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11]                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1]                                                                                                                                         ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1]                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2]                                                                                                                                         ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2]                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                             ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2]                                        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]                                        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4]                                                                                                                                             ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4]                                                                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0]                                                                                                                                         ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0]                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg                                                         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg                                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg                                                         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg                                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                                                        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[1] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                                                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13]                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13]                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.669      ;
; 0.418 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[0] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.070      ; 0.674      ;
; 0.419 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0]                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0]                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.674      ;
; 0.419 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[0] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.674      ;
; 0.437 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0]                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1]                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.692      ;
; 0.439 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3]                                                                                                                                          ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2]                                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.694      ;
; 0.439 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][2]                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.070      ; 0.695      ;
; 0.439 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0]                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2]                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.694      ;
; 0.440 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[3]                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[2]                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.695      ;
; 0.440 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3]                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.070      ; 0.696      ;
; 0.440 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3]                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.070      ; 0.696      ;
; 0.440 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1]                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.070      ; 0.696      ;
; 0.440 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2]                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.070      ; 0.696      ;
; 0.440 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0]                                                                                                                           ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[0]                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.070      ; 0.696      ;
; 0.441 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[2]                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[1]                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.696      ;
; 0.441 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2]                                                                                                                                         ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                                                                                                                                                 ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.696      ;
; 0.441 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][1]                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.070      ; 0.697      ;
; 0.441 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0]                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.070      ; 0.697      ;
; 0.441 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0]                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.070      ; 0.697      ;
; 0.441 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[1]      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[0]      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.696      ;
; 0.442 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[1]                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[0]                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.697      ;
; 0.442 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][4]                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.070      ; 0.698      ;
; 0.443 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13]                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[14]                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.698      ;
; 0.446 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[3]                                                                                                                           ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[2]                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.070      ; 0.702      ;
; 0.448 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8]                                                                                                                                          ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7]                                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.703      ;
; 0.448 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2]                                                                                                                                          ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1]                                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.703      ;
; 0.448 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[3]                                                                                                                           ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[3]                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.070      ; 0.704      ;
; 0.448 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[2]                                                                                                                           ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1]                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.070      ; 0.704      ;
; 0.448 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1]                                                                                                                           ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[1]                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.070      ; 0.704      ;
; 0.448 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1]                                                                                                                           ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0]                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.070      ; 0.704      ;
; 0.448 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[12]                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13]                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.703      ;
; 0.449 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7]                                                                                                                                          ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6]                                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.704      ;
; 0.449 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[2]                                                                                                                           ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[2]                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.070      ; 0.705      ;
; 0.449 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[10]                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[12]                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.704      ;
; 0.449 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[14]                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11]                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.704      ;
; 0.450 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6]                                                                                                                                          ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5]                                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.705      ;
; 0.451 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]                                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.070      ; 0.707      ;
; 0.453 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.070      ; 0.709      ;
; 0.454 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]                                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.070      ; 0.710      ;
; 0.454 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.709      ;
; 0.454 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7]                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.709      ;
; 0.455 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0]                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.710      ;
; 0.455 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.710      ;
; 0.461 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                                                                                           ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1]                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.070      ; 0.717      ;
; 0.461 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2]                                                                                                                                           ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2]                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.070      ; 0.717      ;
; 0.462 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                                                                                           ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3]                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.070      ; 0.718      ;
; 0.462 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.717      ;
; 0.463 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                                                                                           ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0]                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.070      ; 0.719      ;
; 0.463 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.718      ;
; 0.463 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.718      ;
; 0.464 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[6]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[5]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.070      ; 0.720      ;
; 0.466 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[4]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[4]                                                                                                                 ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.721      ;
; 0.468 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[15]                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[2]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.723      ;
; 0.469 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]                                        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 0.724      ;
; 0.473 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_datain_reg0                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.363      ; 1.058      ;
; 0.479 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_datain_reg0                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.363      ; 1.064      ;
; 0.484 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.352      ; 1.058      ;
; 0.485 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[6]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.352      ; 1.059      ;
; 0.487 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.352      ; 1.061      ;
; 0.491 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.352      ; 1.065      ;
; 0.493 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_datain_reg0                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.359      ; 1.074      ;
; 0.494 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_datain_reg0                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.363      ; 1.079      ;
; 0.494 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_datain_reg0                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.363      ; 1.079      ;
; 0.496 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.352      ; 1.070      ;
; 0.499 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_datain_reg0                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.363      ; 1.084      ;
; 0.504 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.352      ; 1.078      ;
; 0.504 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.352      ; 1.078      ;
; 0.506 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.352      ; 1.080      ;
; 0.513 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.352      ; 1.087      ;
; 0.514 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_datain_reg0                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.359      ; 1.095      ;
; 0.517 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_datain_reg0                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.358      ; 1.097      ;
; 0.517 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.352      ; 1.091      ;
; 0.519 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.352      ; 1.093      ;
; 0.520 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.352      ; 1.094      ;
; 0.521 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.352      ; 1.095      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                     ;
+-------+---------------------------------------+----------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                                                                                                                    ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+----------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 6.765 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[13]                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 4.817      ;
; 6.765 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_8BIT_WRITE_ENABLE_reg                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 4.817      ;
; 6.765 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_READ_reg                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 4.817      ;
; 6.774 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[8]                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 4.794      ;
; 6.774 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[10]                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 4.794      ;
; 6.774 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[9]                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 4.794      ;
; 6.774 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[1]                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 4.794      ;
; 6.803 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[14]                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 4.781      ;
; 6.803 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[15]                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 4.781      ;
; 6.818 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 4.770      ;
; 6.821 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[11]                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 4.768      ;
; 7.168 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[22]                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; 0.245      ; 4.823      ;
; 7.168 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[23]                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; 0.245      ; 4.823      ;
; 7.168 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[18]                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; 0.245      ; 4.823      ;
; 7.168 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[19]                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; 0.245      ; 4.823      ;
; 7.168 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[20]                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; 0.245      ; 4.823      ;
; 7.168 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[21]                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; 0.245      ; 4.823      ;
; 7.172 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[1]                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; 0.205      ; 4.779      ;
; 7.172 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[0]                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; 0.205      ; 4.779      ;
; 7.188 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[3]                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 4.401      ;
; 7.189 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[18]                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 4.400      ;
; 7.189 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[17]                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 4.400      ;
; 7.189 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[21]                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 4.400      ;
; 7.189 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[22]                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 4.400      ;
; 7.189 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[20]                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 4.400      ;
; 7.189 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[19]                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 4.400      ;
; 7.189 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[14]                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.171     ; 4.386      ;
; 7.189 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[8]                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.171     ; 4.386      ;
; 7.189 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[11]                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.171     ; 4.386      ;
; 7.189 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[10]                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.171     ; 4.386      ;
; 7.189 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[9]                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.171     ; 4.386      ;
; 7.189 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[15]                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.172     ; 4.385      ;
; 7.189 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[5]                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.172     ; 4.385      ;
; 7.189 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[13]                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.171     ; 4.386      ;
; 7.189 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[12]                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.171     ; 4.386      ;
; 7.189 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[3]                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.170     ; 4.387      ;
; 7.189 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[0]                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.170     ; 4.387      ;
; 7.189 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[2]                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.170     ; 4.387      ;
; 7.189 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[1]                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.170     ; 4.387      ;
; 7.189 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[16]                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.170     ; 4.387      ;
; 7.189 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[17]                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.170     ; 4.387      ;
; 7.190 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[6]                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 4.381      ;
; 7.190 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[11]                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.163     ; 4.393      ;
; 7.190 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[6]                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.171     ; 4.385      ;
; 7.190 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.163     ; 4.393      ;
; 7.190 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.163     ; 4.393      ;
; 7.190 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|memory_ready_reg                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.163     ; 4.393      ;
; 7.197 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[12]                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 4.387      ;
; 7.198 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[14]                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 4.390      ;
; 7.198 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[8]                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.170     ; 4.378      ;
; 7.198 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[9]                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.170     ; 4.378      ;
; 7.198 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[9]                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.170     ; 4.378      ;
; 7.202 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[25]                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 4.387      ;
; 7.202 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[7]                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 4.382      ;
; 7.204 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|delay_line:stimer_delay|shift_reg[1]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.166     ; 4.376      ;
; 7.204 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|delay_line:stimer_delay|shift_reg[0]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.166     ; 4.376      ;
; 7.204 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audctl_reg[4]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.166     ; 4.376      ;
; 7.204 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audctl_reg[6]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.166     ; 4.376      ;
; 7.204 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.166     ; 4.376      ;
; 7.204 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.166     ; 4.376      ;
; 7.204 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer1|delay_line:underflow0_delay|shift_reg[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.166     ; 4.376      ;
; 7.204 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer1|delay_line:underflow0_delay|shift_reg[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.166     ; 4.376      ;
; 7.204 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[1]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.155     ; 4.387      ;
; 7.204 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[0]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.155     ; 4.387      ;
; 7.204 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[0]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.154     ; 4.388      ;
; 7.204 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[1]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.154     ; 4.388      ;
; 7.204 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[2]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.155     ; 4.387      ;
; 7.204 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[2]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.154     ; 4.388      ;
; 7.204 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[3]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.155     ; 4.387      ;
; 7.204 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[3]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.154     ; 4.388      ;
; 7.204 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[6]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.155     ; 4.387      ;
; 7.204 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[4]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.155     ; 4.387      ;
; 7.204 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[4]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.154     ; 4.388      ;
; 7.204 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[5]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.155     ; 4.387      ;
; 7.204 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[5]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.154     ; 4.388      ;
; 7.204 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[6]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.154     ; 4.388      ;
; 7.204 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[7]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.155     ; 4.387      ;
; 7.204 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[7]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.154     ; 4.388      ;
; 7.204 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer2|delay_line:underflow0_delay|shift_reg[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.154     ; 4.388      ;
; 7.204 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer2|delay_line:underflow0_delay|shift_reg[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.154     ; 4.388      ;
; 7.204 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[0]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 4.386      ;
; 7.204 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[1]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 4.386      ;
; 7.204 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[2]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 4.386      ;
; 7.204 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[2]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 4.386      ;
; 7.204 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[3]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 4.386      ;
; 7.204 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[3]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 4.386      ;
; 7.204 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[6]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 4.386      ;
; 7.204 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[4]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 4.386      ;
; 7.204 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[4]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 4.386      ;
; 7.204 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[5]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 4.386      ;
; 7.204 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[5]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 4.386      ;
; 7.204 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[6]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 4.386      ;
; 7.204 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[7]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 4.386      ;
; 7.204 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[7]                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 4.386      ;
; 7.204 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer3|delay_line:underflow0_delay|shift_reg[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.154     ; 4.388      ;
; 7.204 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer3|delay_line:underflow0_delay|shift_reg[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.154     ; 4.388      ;
; 7.204 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|irqen_reg[1]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.155     ; 4.387      ;
; 7.204 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|irqst_reg[1]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.155     ; 4.387      ;
; 7.204 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|irqen_reg[5]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.155     ; 4.387      ;
; 7.204 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|irqen_reg[4]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.155     ; 4.387      ;
+-------+---------------------------------------+----------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                        ;
+-------+------------------------+----------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                      ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+----------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 7.798 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.262     ; 3.563      ;
; 7.866 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.184     ; 3.580      ;
; 7.866 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[11] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.184     ; 3.580      ;
; 7.868 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.183     ; 3.579      ;
; 7.868 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.183     ; 3.579      ;
; 7.870 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.185     ; 3.575      ;
; 7.871 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 3.573      ;
; 7.871 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 3.573      ;
; 7.885 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[8]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.322     ; 3.415      ;
; 7.886 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[14]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.311     ; 3.425      ;
; 7.886 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[15]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.311     ; 3.425      ;
; 7.886 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[13]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.311     ; 3.425      ;
; 7.887 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[9]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.329     ; 3.406      ;
; 7.891 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.171     ; 3.568      ;
; 7.891 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.171     ; 3.568      ;
; 7.891 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.172     ; 3.567      ;
; 7.892 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[10]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.324     ; 3.406      ;
; 7.892 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[12]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.324     ; 3.406      ;
; 7.892 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[11]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.324     ; 3.406      ;
; 7.893 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.211     ; 3.528      ;
; 7.894 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[0]    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 3.562      ;
; 7.894 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[1]    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 3.562      ;
; 7.894 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[0]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 3.562      ;
; 7.894 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 3.562      ;
; 7.894 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[13] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.200     ; 3.538      ;
; 7.894 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[14] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.200     ; 3.538      ;
; 7.894 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[15] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.200     ; 3.538      ;
; 7.894 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 3.562      ;
; 7.895 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[9]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.218     ; 3.519      ;
; 7.900 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.213     ; 3.519      ;
; 7.900 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[11] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.213     ; 3.519      ;
; 7.900 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[12] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.213     ; 3.519      ;
; 7.906 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.313     ; 3.403      ;
; 7.906 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.314     ; 3.402      ;
; 7.906 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.322     ; 3.394      ;
; 7.909 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[1]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.310     ; 3.403      ;
; 7.909 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[3]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.313     ; 3.400      ;
; 7.909 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[0]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.310     ; 3.403      ;
; 7.909 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[2]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.310     ; 3.403      ;
; 7.914 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.211     ; 3.507      ;
; 7.914 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.515      ;
; 7.914 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[6]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.202     ; 3.516      ;
; 7.917 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[0]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.199     ; 3.516      ;
; 7.917 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.199     ; 3.516      ;
; 7.917 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.199     ; 3.516      ;
; 7.917 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[3]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.202     ; 3.513      ;
; 8.013 ; sdram_reset_ctrl_n_reg ; ram_di_reg[11]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.184     ; 3.548      ;
; 8.015 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.187     ; 3.543      ;
; 8.033 ; sdram_reset_ctrl_n_reg ; ram_do_reg[19]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.173     ; 3.539      ;
; 8.033 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.173     ; 3.539      ;
; 8.033 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.173     ; 3.539      ;
; 8.033 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.173     ; 3.539      ;
; 8.033 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.173     ; 3.539      ;
; 8.033 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.173     ; 3.539      ;
; 8.033 ; sdram_reset_ctrl_n_reg ; ram_do_reg[20]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.173     ; 3.539      ;
; 8.117 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.183     ; 3.330      ;
; 8.140 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.172     ; 3.318      ;
; 8.140 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.172     ; 3.318      ;
; 8.140 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.172     ; 3.318      ;
; 8.140 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.172     ; 3.318      ;
; 8.140 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.172     ; 3.318      ;
; 8.378 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 3.192      ;
; 8.378 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 3.192      ;
; 8.378 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 3.192      ;
; 8.378 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 3.191      ;
; 8.378 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 3.191      ;
; 8.379 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 3.192      ;
; 8.379 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 3.192      ;
; 8.379 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 3.192      ;
; 8.379 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 3.192      ;
; 8.379 ; sdram_reset_ctrl_n_reg ; seq_reg[5]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 3.192      ;
; 8.379 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 3.192      ;
; 8.379 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 3.192      ;
; 8.379 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 3.191      ;
; 8.379 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 3.191      ;
; 8.379 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 3.191      ;
; 8.379 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 3.191      ;
; 8.379 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 3.191      ;
; 8.379 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 3.192      ;
; 8.379 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 3.192      ;
; 8.379 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.185     ; 3.181      ;
; 8.379 ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 3.180      ;
; 8.379 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.185     ; 3.181      ;
; 8.379 ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 3.180      ;
; 8.379 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 3.180      ;
; 8.379 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.185     ; 3.181      ;
; 8.379 ; sdram_reset_ctrl_n_reg ; ram_di_reg[12]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.185     ; 3.181      ;
; 8.379 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 3.180      ;
; 8.379 ; sdram_reset_ctrl_n_reg ; ram_di_reg[15]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 3.180      ;
; 8.379 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.171     ; 3.195      ;
; 8.380 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.185     ; 3.180      ;
; 8.380 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.185     ; 3.180      ;
; 8.380 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.185     ; 3.180      ;
; 8.380 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.185     ; 3.180      ;
; 8.380 ; sdram_reset_ctrl_n_reg ; ram_do_reg[14]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.185     ; 3.180      ;
; 8.380 ; sdram_reset_ctrl_n_reg ; ram_do_reg[11]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.185     ; 3.180      ;
; 8.380 ; sdram_reset_ctrl_n_reg ; ram_do_reg[15]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.185     ; 3.180      ;
; 8.380 ; sdram_reset_ctrl_n_reg ; ram_do_reg[12]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.185     ; 3.180      ;
; 8.380 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.185     ; 3.180      ;
; 8.380 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.185     ; 3.180      ;
+-------+------------------------+----------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: 'altera_reserved_tck'                                                                                                                                                                                                                                                                                                                           ;
+--------+--------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                        ; To Node                                                                                                                                                                        ; Launch Clock        ; Latch Clock         ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; 47.801 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.172      ; 2.369      ;
; 97.408 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.081     ; 2.509      ;
; 97.408 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.081     ; 2.509      ;
; 97.408 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.081     ; 2.509      ;
; 97.408 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.081     ; 2.509      ;
; 97.469 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.081     ; 2.448      ;
; 97.469 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.081     ; 2.448      ;
; 97.469 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.081     ; 2.448      ;
; 97.469 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.081     ; 2.448      ;
; 97.688 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.070     ; 2.240      ;
; 97.688 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.070     ; 2.240      ;
; 97.688 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.070     ; 2.240      ;
; 97.688 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.070     ; 2.240      ;
; 97.717 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.070     ; 2.211      ;
; 97.717 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.070     ; 2.211      ;
; 97.717 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.070     ; 2.211      ;
; 97.717 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.070     ; 2.211      ;
; 97.845 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg                  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 2.092      ;
; 97.867 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                 ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.062     ; 2.069      ;
; 98.047 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 1.890      ;
; 98.047 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 1.890      ;
; 98.047 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 1.890      ;
; 98.047 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 1.890      ;
; 98.047 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 1.890      ;
; 98.047 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 1.890      ;
; 98.047 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 1.890      ;
; 98.047 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 1.890      ;
; 98.047 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][4]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 1.890      ;
; 98.047 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.061     ; 1.890      ;
; 98.051 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.060     ; 1.887      ;
; 98.051 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.060     ; 1.887      ;
; 98.051 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                 ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.060     ; 1.887      ;
; 98.051 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.059     ; 1.888      ;
; 98.051 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.059     ; 1.888      ;
; 98.051 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][2]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.059     ; 1.888      ;
; 98.051 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.059     ; 1.888      ;
; 98.051 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][1]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.059     ; 1.888      ;
; 98.051 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.059     ; 1.888      ;
; 98.051 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.059     ; 1.888      ;
; 98.051 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.059     ; 1.888      ;
; 98.051 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][4]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.059     ; 1.888      ;
; 98.051 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.059     ; 1.888      ;
; 98.051 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0                                                                                                 ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.060     ; 1.887      ;
; 98.057 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                 ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.058     ; 1.883      ;
; 98.070 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.071     ; 1.857      ;
; 98.070 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.071     ; 1.857      ;
; 98.070 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.071     ; 1.857      ;
; 98.071 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2]                                                                                                  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 1.858      ;
; 98.130 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg                  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.070     ; 1.798      ;
; 98.159 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.071     ; 1.768      ;
; 98.159 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.071     ; 1.768      ;
; 98.159 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.071     ; 1.768      ;
; 98.169 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1]                                                                                                  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.070     ; 1.759      ;
; 98.169 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.070     ; 1.759      ;
; 98.169 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.070     ; 1.759      ;
; 98.169 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.070     ; 1.759      ;
; 98.169 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.070     ; 1.759      ;
; 98.169 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0]                                                                                                  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.070     ; 1.759      ;
; 98.169 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.070     ; 1.759      ;
; 98.178 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.072     ; 1.748      ;
; 98.178 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.072     ; 1.748      ;
; 98.178 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.072     ; 1.748      ;
; 98.178 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.072     ; 1.748      ;
; 98.178 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.072     ; 1.748      ;
; 98.178 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[6]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.072     ; 1.748      ;
; 98.178 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.072     ; 1.748      ;
; 98.178 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.072     ; 1.748      ;
; 98.178 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.072     ; 1.748      ;
; 98.199 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.072     ; 1.727      ;
; 98.199 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.072     ; 1.727      ;
; 98.199 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.072     ; 1.727      ;
; 98.199 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.072     ; 1.727      ;
; 98.199 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.072     ; 1.727      ;
; 98.199 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[6]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.072     ; 1.727      ;
; 98.199 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.072     ; 1.727      ;
; 98.199 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.072     ; 1.727      ;
; 98.199 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.072     ; 1.727      ;
; 98.284 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 1.645      ;
; 98.284 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 1.645      ;
; 98.284 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 1.645      ;
; 98.284 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 1.645      ;
; 98.284 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 1.645      ;
; 98.284 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 1.645      ;
; 98.284 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 1.645      ;
; 98.284 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 1.645      ;
; 98.284 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 1.645      ;
; 98.284 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 1.645      ;
; 98.284 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_dr_scan_reg                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 1.645      ;
; 98.284 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.069     ; 1.645      ;
+--------+--------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: 'mcc_pll3|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                             ;
+--------+--------------+-----------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node    ; To Node                                             ; Launch Clock                                         ; Latch Clock                                          ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------+-----------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+
; 63.166 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|dp1_last~_emulated ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.074     ; 3.414      ;
; 63.166 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|dm1_last~_emulated ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.074     ; 3.414      ;
; 63.561 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[2]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.077     ; 3.016      ;
; 63.561 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[0]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.077     ; 3.016      ;
; 63.561 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[1]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.077     ; 3.016      ;
; 63.561 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[3]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.077     ; 3.016      ;
; 63.561 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|synch              ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.077     ; 3.016      ;
; 63.561 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[6]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.077     ; 3.016      ;
; 63.561 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[6]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.077     ; 3.016      ;
; 63.561 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[2]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.077     ; 3.016      ;
; 63.561 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.077     ; 3.016      ;
; 63.561 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[3]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.077     ; 3.016      ;
; 63.561 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.077     ; 3.016      ;
; 63.561 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[4]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.077     ; 3.016      ;
; 63.561 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.077     ; 3.016      ;
; 63.561 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[5]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.077     ; 3.016      ;
; 63.561 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.077     ; 3.016      ;
; 63.561 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[0]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.077     ; 3.016      ;
; 63.561 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[0]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.077     ; 3.016      ;
; 63.561 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[1]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.077     ; 3.016      ;
; 63.561 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.077     ; 3.016      ;
; 63.561 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[7]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.077     ; 3.016      ;
; 63.561 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[7]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.077     ; 3.016      ;
; 63.561 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|read_byte_valid    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.077     ; 3.016      ;
; 63.562 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state2  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.074     ; 3.018      ;
; 63.562 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state4  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.074     ; 3.018      ;
; 63.562 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|stuffin1[0]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.074     ; 3.018      ;
; 63.562 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|stuffin1[1]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.074     ; 3.018      ;
; 63.562 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|stuffin1[2]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.074     ; 3.018      ;
; 63.562 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state1  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.074     ; 3.018      ;
; 63.562 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state3  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.074     ; 3.018      ;
; 66.028 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state3  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.397      ; 3.023      ;
; 66.028 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[0]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.395      ; 3.021      ;
; 66.028 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[4]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.395      ; 3.021      ;
; 66.028 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[2]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.395      ; 3.021      ;
; 66.028 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[3]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.395      ; 3.021      ;
; 66.028 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[5]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.395      ; 3.021      ;
; 66.028 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[1]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.395      ; 3.021      ;
; 66.028 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[7]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.395      ; 3.021      ;
; 66.028 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[6]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.395      ; 3.021      ;
; 66.028 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state4  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.397      ; 3.023      ;
; 66.029 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dp1_last~_emulated ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.397      ; 3.022      ;
; 66.029 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dm1_last~_emulated ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.397      ; 3.022      ;
; 66.038 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[0]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.409      ; 3.025      ;
; 66.038 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state1  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.408      ; 3.024      ;
; 66.038 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state2  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.408      ; 3.024      ;
; 66.038 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[2]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.409      ; 3.025      ;
; 66.038 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[3]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.409      ; 3.025      ;
; 66.038 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|synch              ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.409      ; 3.025      ;
; 66.038 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[0]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.408      ; 3.024      ;
; 66.038 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[4]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.409      ; 3.025      ;
; 66.038 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[2]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.408      ; 3.024      ;
; 66.038 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[3]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.408      ; 3.024      ;
; 66.038 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[5]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.409      ; 3.025      ;
; 66.038 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[1]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.408      ; 3.024      ;
; 66.038 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[7]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.409      ; 3.025      ;
; 66.038 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[6]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.409      ; 3.025      ;
; 66.038 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|stuffin1[0]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.408      ; 3.024      ;
; 66.038 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|stuffin1[2]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.408      ; 3.024      ;
; 66.038 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|stuffin1[1]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.408      ; 3.024      ;
; 66.038 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[1]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.409      ; 3.025      ;
; 66.038 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|read_byte_valid    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.409      ; 3.025      ;
+--------+--------------+-----------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: 'mcc_pll3|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                              ;
+--------+--------------+-----------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node    ; To Node                                             ; Launch Clock                                         ; Latch Clock                                          ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------+-----------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+
; -0.012 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state1  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.684      ; 2.858      ;
; -0.012 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state2  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.684      ; 2.858      ;
; -0.012 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[2]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.684      ; 2.858      ;
; -0.012 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[1]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.684      ; 2.858      ;
; -0.011 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[0]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.684      ; 2.859      ;
; -0.011 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[2]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.684      ; 2.859      ;
; -0.011 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[3]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.684      ; 2.859      ;
; -0.011 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|synch              ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.684      ; 2.859      ;
; -0.011 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[0]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.683      ; 2.858      ;
; -0.011 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[4]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.684      ; 2.859      ;
; -0.011 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[3]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.683      ; 2.858      ;
; -0.011 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[5]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.684      ; 2.859      ;
; -0.011 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[7]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.684      ; 2.859      ;
; -0.011 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[6]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.684      ; 2.859      ;
; -0.011 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|stuffin1[0]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.683      ; 2.858      ;
; -0.011 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|stuffin1[2]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.683      ; 2.858      ;
; -0.011 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|stuffin1[1]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.683      ; 2.858      ;
; -0.011 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[1]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.684      ; 2.859      ;
; -0.011 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|read_byte_valid    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.684      ; 2.859      ;
; -0.001 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state3  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.672      ; 2.857      ;
; -0.001 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dp1_last~_emulated ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.671      ; 2.856      ;
; -0.001 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dm1_last~_emulated ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.671      ; 2.856      ;
; -0.001 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state4  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.672      ; 2.857      ;
; 0.000  ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[0]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.670      ; 2.856      ;
; 0.000  ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[4]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.670      ; 2.856      ;
; 0.000  ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[2]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.670      ; 2.856      ;
; 0.000  ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[3]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.670      ; 2.856      ;
; 0.000  ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[5]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.670      ; 2.856      ;
; 0.000  ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[1]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.670      ; 2.856      ;
; 0.000  ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[7]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.670      ; 2.856      ;
; 0.000  ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[6]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.670      ; 2.856      ;
; 2.603  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state2  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.065      ; 2.854      ;
; 2.603  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state4  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.065      ; 2.854      ;
; 2.603  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|stuffin1[0]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.065      ; 2.854      ;
; 2.603  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|stuffin1[1]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.065      ; 2.854      ;
; 2.603  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|stuffin1[2]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.065      ; 2.854      ;
; 2.603  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state1  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.065      ; 2.854      ;
; 2.603  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state3  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.065      ; 2.854      ;
; 2.603  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|synch              ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 2.852      ;
; 2.603  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[2]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 2.852      ;
; 2.603  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[3]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 2.852      ;
; 2.603  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 2.852      ;
; 2.603  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[0]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 2.852      ;
; 2.603  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[0]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 2.852      ;
; 2.603  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[1]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 2.852      ;
; 2.603  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 2.852      ;
; 2.603  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|read_byte_valid    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 2.852      ;
; 2.604  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[2]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 2.852      ;
; 2.604  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[0]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 2.852      ;
; 2.604  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[1]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 2.852      ;
; 2.604  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[3]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 2.852      ;
; 2.604  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[6]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 2.852      ;
; 2.604  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[6]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 2.852      ;
; 2.604  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 2.852      ;
; 2.604  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[4]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 2.852      ;
; 2.604  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 2.852      ;
; 2.604  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[5]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 2.852      ;
; 2.604  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 2.852      ;
; 2.604  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[7]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 2.852      ;
; 2.604  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[7]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 2.852      ;
; 2.986  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|dp1_last~_emulated ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.065      ; 3.237      ;
; 2.986  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|dm1_last~_emulated ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.065      ; 3.237      ;
+--------+--------------+-----------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: 'altera_reserved_tck'                                                                                                                                                                                                                                                                                                                            ;
+--------+--------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                        ; To Node                                                                                                                                                                        ; Launch Clock        ; Latch Clock         ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; 1.254  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 1.509      ;
; 1.254  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 1.509      ;
; 1.254  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 1.509      ;
; 1.254  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 1.509      ;
; 1.254  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 1.509      ;
; 1.254  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 1.509      ;
; 1.254  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 1.509      ;
; 1.254  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 1.509      ;
; 1.254  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 1.509      ;
; 1.254  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 1.509      ;
; 1.254  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_dr_scan_reg                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 1.509      ;
; 1.254  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 1.509      ;
; 1.371  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.068      ; 1.625      ;
; 1.371  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.068      ; 1.625      ;
; 1.371  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.068      ; 1.625      ;
; 1.371  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.068      ; 1.625      ;
; 1.371  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.068      ; 1.625      ;
; 1.371  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[6]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.068      ; 1.625      ;
; 1.371  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.068      ; 1.625      ;
; 1.371  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.068      ; 1.625      ;
; 1.371  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.068      ; 1.625      ;
; 1.383  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1]                                                                                                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.068      ; 1.637      ;
; 1.383  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.068      ; 1.637      ;
; 1.383  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.068      ; 1.637      ;
; 1.383  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.068      ; 1.637      ;
; 1.383  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.068      ; 1.637      ;
; 1.383  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0]                                                                                                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.068      ; 1.637      ;
; 1.383  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.068      ; 1.637      ;
; 1.386  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.068      ; 1.640      ;
; 1.386  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.068      ; 1.640      ;
; 1.386  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.068      ; 1.640      ;
; 1.386  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.068      ; 1.640      ;
; 1.386  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.068      ; 1.640      ;
; 1.386  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[6]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.068      ; 1.640      ;
; 1.386  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.068      ; 1.640      ;
; 1.386  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.068      ; 1.640      ;
; 1.386  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.068      ; 1.640      ;
; 1.408  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.068      ; 1.662      ;
; 1.408  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.068      ; 1.662      ;
; 1.408  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.068      ; 1.662      ;
; 1.414  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.068      ; 1.668      ;
; 1.465  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                 ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.080      ; 1.731      ;
; 1.473  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2]                                                                                                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 1.728      ;
; 1.474  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 1.729      ;
; 1.474  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 1.729      ;
; 1.474  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 1.729      ;
; 1.479  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.078      ; 1.743      ;
; 1.479  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.078      ; 1.743      ;
; 1.479  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                 ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.078      ; 1.743      ;
; 1.479  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0                                                                                                 ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.078      ; 1.743      ;
; 1.481  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.080      ; 1.747      ;
; 1.481  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.080      ; 1.747      ;
; 1.481  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][2]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.080      ; 1.747      ;
; 1.481  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.080      ; 1.747      ;
; 1.481  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][1]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.080      ; 1.747      ;
; 1.481  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.080      ; 1.747      ;
; 1.481  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.080      ; 1.747      ;
; 1.481  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.080      ; 1.747      ;
; 1.481  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][4]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.080      ; 1.747      ;
; 1.481  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.080      ; 1.747      ;
; 1.486  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.078      ; 1.750      ;
; 1.486  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.078      ; 1.750      ;
; 1.486  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.078      ; 1.750      ;
; 1.486  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.078      ; 1.750      ;
; 1.486  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.078      ; 1.750      ;
; 1.486  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.078      ; 1.750      ;
; 1.486  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.078      ; 1.750      ;
; 1.486  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.078      ; 1.750      ;
; 1.486  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][4]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.078      ; 1.750      ;
; 1.486  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.078      ; 1.750      ;
; 1.684  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                 ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.076      ; 1.946      ;
; 1.697  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 1.952      ;
; 1.697  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 1.952      ;
; 1.697  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 1.952      ;
; 1.697  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 1.952      ;
; 1.700  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.077      ; 1.963      ;
; 1.841  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 2.096      ;
; 1.841  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 2.096      ;
; 1.841  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 2.096      ;
; 1.841  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 2.096      ;
; 2.097  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.058      ; 2.341      ;
; 2.097  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.058      ; 2.341      ;
; 2.097  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.058      ; 2.341      ;
; 2.097  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.058      ; 2.341      ;
; 2.124  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.058      ; 2.368      ;
; 2.124  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.058      ; 2.368      ;
; 2.124  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.058      ; 2.368      ;
; 2.124  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.058      ; 2.368      ;
; 51.715 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; -50.000      ; 0.314      ; 2.235      ;
+--------+--------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                           ; To Node                                                                                                                                                                                                                ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 1.451 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a55  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.024      ;
; 1.451 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a54  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.024      ;
; 1.451 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a53  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.024      ;
; 1.451 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a52  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.024      ;
; 1.451 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a51  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.024      ;
; 1.451 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a50  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.024      ;
; 1.451 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a49  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.024      ;
; 1.451 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a48  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.024      ;
; 1.451 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a47  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.024      ;
; 1.451 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a46  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.024      ;
; 1.451 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a45  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.024      ;
; 1.451 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a44  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.024      ;
; 1.451 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a43  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.024      ;
; 1.451 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a42  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.024      ;
; 1.451 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a41  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.024      ;
; 1.451 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a40  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.024      ;
; 1.451 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a39  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.024      ;
; 1.451 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a38  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.024      ;
; 1.451 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a37  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.024      ;
; 1.451 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a36  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.024      ;
; 1.451 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a23  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.024      ;
; 1.451 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a22  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.024      ;
; 1.451 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a21  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.024      ;
; 1.451 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a20  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.024      ;
; 1.451 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a19  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.024      ;
; 1.451 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a18  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.024      ;
; 1.451 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a17  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.024      ;
; 1.451 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a16  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.024      ;
; 1.451 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a7   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.024      ;
; 1.451 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a6   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.024      ;
; 1.451 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a5   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.024      ;
; 1.451 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a4   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.024      ;
; 1.451 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a3   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.024      ;
; 1.451 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a2   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.024      ;
; 1.451 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a1   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.024      ;
; 1.451 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.387      ; 2.024      ;
; 1.457 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a5 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.388      ; 2.031      ;
; 1.457 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a4 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.388      ; 2.031      ;
; 1.457 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a3 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.388      ; 2.031      ;
; 1.457 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a2 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.388      ; 2.031      ;
; 1.457 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.388      ; 2.031      ;
; 1.457 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.388      ; 2.031      ;
; 1.768 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a63  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.386      ; 2.340      ;
; 1.768 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a62  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.386      ; 2.340      ;
; 1.768 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a61  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.386      ; 2.340      ;
; 1.768 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a60  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.386      ; 2.340      ;
; 1.768 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a59  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.386      ; 2.340      ;
; 1.768 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a58  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.386      ; 2.340      ;
; 1.768 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a57  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.386      ; 2.340      ;
; 1.768 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a56  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.386      ; 2.340      ;
; 1.768 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a35  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.386      ; 2.340      ;
; 1.768 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a34  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.386      ; 2.340      ;
; 1.768 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a33  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.386      ; 2.340      ;
; 1.768 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a32  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.386      ; 2.340      ;
; 1.768 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a31  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.386      ; 2.340      ;
; 1.768 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a30  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.386      ; 2.340      ;
; 1.768 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a29  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.386      ; 2.340      ;
; 1.768 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a28  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.386      ; 2.340      ;
; 1.768 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a27  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.386      ; 2.340      ;
; 1.768 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a26  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.386      ; 2.340      ;
; 1.768 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a25  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.386      ; 2.340      ;
; 1.768 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a24  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.386      ; 2.340      ;
; 1.768 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a15  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.386      ; 2.340      ;
; 1.768 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a14  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.386      ; 2.340      ;
; 1.768 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a13  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.386      ; 2.340      ;
; 1.768 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a12  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.386      ; 2.340      ;
; 1.768 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a11  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.386      ; 2.340      ;
; 1.768 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a10  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.386      ; 2.340      ;
; 1.768 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a9   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.386      ; 2.340      ;
; 1.768 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a8   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.386      ; 2.340      ;
; 1.865 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a6 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.411      ; 2.462      ;
; 1.865 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a5 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.411      ; 2.462      ;
; 1.865 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a4 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.411      ; 2.462      ;
; 1.865 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a3 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.411      ; 2.462      ;
; 1.865 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a2 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.411      ; 2.462      ;
; 1.865 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.411      ; 2.462      ;
; 1.865 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.411      ; 2.462      ;
; 2.201 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a15   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.384      ; 2.771      ;
; 2.201 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a14   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.384      ; 2.771      ;
; 2.201 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a13   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.384      ; 2.771      ;
; 2.201 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a12   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.384      ; 2.771      ;
; 2.201 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a11   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.384      ; 2.771      ;
; 2.201 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a10   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.384      ; 2.771      ;
; 2.201 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a9    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.384      ; 2.771      ;
; 2.201 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a8    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.384      ; 2.771      ;
; 2.201 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a7    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.384      ; 2.771      ;
; 2.201 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a6    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.384      ; 2.771      ;
; 2.201 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a5    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.384      ; 2.771      ;
; 2.201 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a4    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.384      ; 2.771      ;
; 2.201 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a3    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.384      ; 2.771      ;
; 2.201 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a2    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.384      ; 2.771      ;
; 2.201 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a1    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.384      ; 2.771      ;
; 2.201 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.384      ; 2.771      ;
; 3.356 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[4]                                                                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.631      ; 4.194      ;
; 3.356 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[5]                                                                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.631      ; 4.194      ;
; 3.402 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]                                                                                                                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.609      ; 4.218      ;
; 3.402 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[8]                                                                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.609      ; 4.218      ;
; 3.402 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                                                                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.609      ; 4.218      ;
; 3.804 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serin_shift_reg[9]                                                                                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.187      ; 4.198      ;
; 3.804 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serin_shift_reg[8]                                                                                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.187      ; 4.198      ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                      ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                                   ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 2.199 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.600      ; 3.004      ;
; 2.620 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.981      ;
; 2.620 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.981      ;
; 2.620 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.981      ;
; 2.620 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.981      ;
; 2.620 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.981      ;
; 2.620 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.981      ;
; 2.620 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.981      ;
; 2.620 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.981      ;
; 2.620 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.981      ;
; 2.620 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.981      ;
; 2.620 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.981      ;
; 2.621 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 2.994      ;
; 2.621 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 2.994      ;
; 2.621 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 2.994      ;
; 2.621 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 2.994      ;
; 2.621 ; sdram_reset_ctrl_n_reg ; seq_reg[5]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 2.994      ;
; 2.621 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 2.994      ;
; 2.621 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 2.994      ;
; 2.621 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 2.993      ;
; 2.621 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 2.993      ;
; 2.621 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 2.993      ;
; 2.621 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 2.994      ;
; 2.621 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.168      ; 2.994      ;
; 2.621 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 2.992      ;
; 2.621 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 2.992      ;
; 2.621 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 3.004      ;
; 2.622 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 2.993      ;
; 2.622 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 2.993      ;
; 2.622 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 2.993      ;
; 2.622 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 2.993      ;
; 2.622 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 2.993      ;
; 2.622 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 2.984      ;
; 2.622 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 2.984      ;
; 2.622 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 2.984      ;
; 2.622 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 2.984      ;
; 2.622 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 2.984      ;
; 2.622 ; sdram_reset_ctrl_n_reg ; ram_do_reg[5]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 2.984      ;
; 2.622 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 2.984      ;
; 2.622 ; sdram_reset_ctrl_n_reg ; ram_do_reg[8]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 2.984      ;
; 2.622 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 2.984      ;
; 2.622 ; sdram_reset_ctrl_n_reg ; ram_do_reg[9]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 2.984      ;
; 2.622 ; sdram_reset_ctrl_n_reg ; ram_do_reg[25]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 2.984      ;
; 2.622 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 2.984      ;
; 2.622 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 2.984      ;
; 2.622 ; sdram_reset_ctrl_n_reg ; ram_do_reg[13]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 2.984      ;
; 2.622 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 2.984      ;
; 2.622 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.983      ;
; 2.622 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.983      ;
; 2.622 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.983      ;
; 2.622 ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.983      ;
; 2.622 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.170      ; 2.997      ;
; 2.622 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[1]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.983      ;
; 2.623 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 2.985      ;
; 2.623 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 2.985      ;
; 2.623 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 2.985      ;
; 2.623 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 2.985      ;
; 2.623 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 2.985      ;
; 2.623 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 2.983      ;
; 2.623 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.984      ;
; 2.623 ; sdram_reset_ctrl_n_reg ; ram_di_reg[6]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.984      ;
; 2.623 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.984      ;
; 2.623 ; sdram_reset_ctrl_n_reg ; ram_di_reg[14]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.984      ;
; 2.624 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.985      ;
; 2.624 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.985      ;
; 2.624 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.985      ;
; 2.624 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 2.986      ;
; 2.624 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 2.986      ;
; 2.624 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 2.986      ;
; 2.624 ; sdram_reset_ctrl_n_reg ; ram_di_reg[12]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 2.986      ;
; 2.624 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.985      ;
; 2.625 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.986      ;
; 2.625 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.986      ;
; 2.625 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.986      ;
; 2.625 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.986      ;
; 2.625 ; sdram_reset_ctrl_n_reg ; ram_do_reg[14]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.986      ;
; 2.625 ; sdram_reset_ctrl_n_reg ; ram_do_reg[11]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.986      ;
; 2.625 ; sdram_reset_ctrl_n_reg ; ram_do_reg[15]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.986      ;
; 2.625 ; sdram_reset_ctrl_n_reg ; ram_do_reg[12]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.986      ;
; 2.625 ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 2.985      ;
; 2.625 ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 2.985      ;
; 2.625 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 2.985      ;
; 2.625 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 2.985      ;
; 2.625 ; sdram_reset_ctrl_n_reg ; ram_di_reg[15]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 2.985      ;
; 2.625 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[0]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.986      ;
; 2.853 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.151      ; 3.133      ;
; 2.853 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.151      ; 3.133      ;
; 2.854 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.150      ; 3.133      ;
; 2.854 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.150      ; 3.133      ;
; 2.854 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.150      ; 3.133      ;
; 2.877 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.139      ; 3.145      ;
; 2.968 ; sdram_reset_ctrl_n_reg ; ram_do_reg[19]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 3.342      ;
; 2.968 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 3.342      ;
; 2.968 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 3.342      ;
; 2.968 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 3.342      ;
; 2.968 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 3.342      ;
; 2.968 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 3.342      ;
; 2.968 ; sdram_reset_ctrl_n_reg ; ram_do_reg[20]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.169      ; 3.342      ;
; 2.989 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.154      ; 3.348      ;
; 2.990 ; sdram_reset_ctrl_n_reg ; ram_di_reg[11]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 3.352      ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3]'                                                        ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+---------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                         ; Clock Edge ; Target                    ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+---------------------------+
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[2]              ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[3]              ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[4]              ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[5]              ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[6]              ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[7]              ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[8]              ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[9]              ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[0]         ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[1]         ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[2]         ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[3]         ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[4]         ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[5]         ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[6]         ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[7]         ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[8]         ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[9]         ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[0]   ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[1]   ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[2]   ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[3]   ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[4]   ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[5]   ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[6]   ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[7]   ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[8]   ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[9]   ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[0]   ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[1]   ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[2]   ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[3]   ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[4]   ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[5]   ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[6]   ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[7]   ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[8]   ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[9]   ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[0] ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[1] ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[2] ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[3] ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[4] ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[5] ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[6] ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[7] ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[8] ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[9] ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly1[0]       ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly1[1]       ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly1[2]       ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly1[3]       ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly1[4]       ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly1[5]       ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly1[6]       ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly1[7]       ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly2[0]       ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly2[1]       ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly2[2]       ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly2[3]       ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly2[4]       ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly2[5]       ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly2[6]       ;
; 4.128 ; 4.348        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly2[7]       ;
; 4.247 ; 4.400        ; 0.153          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[0]              ;
; 4.247 ; 4.400        ; 0.153          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[1]              ;
; 4.247 ; 4.400        ; 0.153          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[2]              ;
; 4.247 ; 4.400        ; 0.153          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[3]              ;
; 4.247 ; 4.400        ; 0.153          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[4]              ;
; 4.247 ; 4.400        ; 0.153          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[5]              ;
; 4.247 ; 4.400        ; 0.153          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[6]              ;
; 4.247 ; 4.400        ; 0.153          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[7]              ;
; 4.252 ; 4.410        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[0]              ;
; 4.252 ; 4.410        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[1]              ;
; 4.252 ; 4.410        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[2]              ;
; 4.252 ; 4.410        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[3]              ;
; 4.252 ; 4.410        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[4]              ;
; 4.252 ; 4.410        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[5]              ;
; 4.252 ; 4.410        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[6]              ;
; 4.252 ; 4.410        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[7]              ;
; 4.273 ; 4.461        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[2]              ;
; 4.273 ; 4.461        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[3]              ;
; 4.273 ; 4.461        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[4]              ;
; 4.273 ; 4.461        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[5]              ;
; 4.273 ; 4.461        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[6]              ;
; 4.273 ; 4.461        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[7]              ;
; 4.273 ; 4.461        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[8]              ;
; 4.273 ; 4.461        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[9]              ;
; 4.273 ; 4.461        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[0]         ;
; 4.273 ; 4.461        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[1]         ;
; 4.273 ; 4.461        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[2]         ;
; 4.273 ; 4.461        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[3]         ;
; 4.273 ; 4.461        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[4]         ;
; 4.273 ; 4.461        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[5]         ;
; 4.273 ; 4.461        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[6]         ;
; 4.273 ; 4.461        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[7]         ;
; 4.273 ; 4.461        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[8]         ;
; 4.273 ; 4.461        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[9]         ;
; 4.273 ; 4.461        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[3]   ;
; 4.273 ; 4.461        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[5]   ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+---------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                        ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                         ; Clock Edge ; Target                                                    ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; 5.598 ; 5.818        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[11]                                            ;
; 5.598 ; 5.818        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ;
; 5.598 ; 5.818        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ;
; 5.598 ; 5.818        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ;
; 5.598 ; 5.818        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ;
; 5.598 ; 5.818        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ;
; 5.598 ; 5.818        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ;
; 5.598 ; 5.818        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ;
; 5.598 ; 5.818        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ;
; 5.598 ; 5.818        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ;
; 5.598 ; 5.818        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ;
; 5.598 ; 5.818        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[1]                                           ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[10]                                            ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[14]                                            ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[1]                                             ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[2]                                             ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[6]                                             ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[9]                                             ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[0]                                             ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[10]                                            ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[13]                                            ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[16]                                            ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[17]                                            ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[18]                                            ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[19]                                            ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[1]                                             ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[20]                                            ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[21]                                            ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[22]                                            ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[23]                                            ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[24]                                            ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[25]                                            ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[26]                                            ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[27]                                            ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[29]                                            ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[2]                                             ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[31]                                            ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[5]                                             ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[8]                                             ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[9]                                             ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_act                      ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_req                    ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_act                      ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[0]                                                ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[0]                                           ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[0]                                             ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[12]                                            ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[13]                                            ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[15]                                            ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[3]                                             ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[4]                                             ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[5]                                             ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[7]                                             ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[8]                                             ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[11]                                            ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[12]                                            ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[14]                                            ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[15]                                            ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[3]                                             ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[4]                                             ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[6]                                             ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[7]                                             ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_reg                      ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_act                    ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ;
; 5.600 ; 5.820        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_reg                      ;
; 5.602 ; 5.822        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ;
; 5.602 ; 5.822        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[28]                                            ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[30]                                            ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel[0]                     ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|sdram_rdy                     ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_reg                                         ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[11]                                               ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[1]                                                ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[2]                                                ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[3]                                                ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[4]                                                ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[5]                                                ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[6]                                                ;
; 5.603 ; 5.823        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[7]                                                ;
; 5.604 ; 5.824        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[10]                                               ;
; 5.604 ; 5.824        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[8]                                                ;
; 5.604 ; 5.824        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[9]                                                ;
; 5.605 ; 5.825        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_complete_reg                                ;
; 5.654 ; 5.812        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[13]                  ;
; 5.654 ; 5.812        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[14]                  ;
; 5.654 ; 5.812        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[15]                  ;
; 5.656 ; 5.814        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[0]                   ;
; 5.656 ; 5.814        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[1]                   ;
; 5.656 ; 5.814        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[2]                   ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                            ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                         ; Clock Edge ; Target                                                                                                                       ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+------------------------------------------------------------------------------------------------------------------------------+
; 17.342 ; 17.562       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[11]                                                        ;
; 17.342 ; 17.562       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[12]                                                        ;
; 17.342 ; 17.562       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[13]                                                        ;
; 17.342 ; 17.562       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[14]                                                        ;
; 17.342 ; 17.562       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[15]                                                        ;
; 17.342 ; 17.562       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[17]                                                        ;
; 17.342 ; 17.562       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[8]                                                         ;
; 17.342 ; 17.562       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[0]                                                                            ;
; 17.342 ; 17.562       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[1]                                                                            ;
; 17.343 ; 17.563       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|skctl_reg[0]                                                            ;
; 17.343 ; 17.563       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|skctl_reg[1]                                                            ;
; 17.343 ; 17.563       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|syncreset_enable_divider:enable_64_div|count_reg[0]                     ;
; 17.343 ; 17.563       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|syncreset_enable_divider:enable_64_div|count_reg[1]                     ;
; 17.343 ; 17.563       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|syncreset_enable_divider:enable_64_div|count_reg[2]                     ;
; 17.343 ; 17.563       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|syncreset_enable_divider:enable_64_div|count_reg[3]                     ;
; 17.343 ; 17.563       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|syncreset_enable_divider:enable_64_div|count_reg[4]                     ;
; 17.343 ; 17.563       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[16]                                                        ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|syncreset_enable_divider:enable_15_div|count_reg[0]                     ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|syncreset_enable_divider:enable_15_div|count_reg[1]                     ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|syncreset_enable_divider:enable_15_div|count_reg[2]                     ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|syncreset_enable_divider:enable_15_div|count_reg[3]                     ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|syncreset_enable_divider:enable_15_div|count_reg[4]                     ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|syncreset_enable_divider:enable_15_div|count_reg[5]                     ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|syncreset_enable_divider:enable_15_div|count_reg[6]                     ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|syncreset_enable_divider:enable_15_div|enabled_out_reg                  ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|syncreset_enable_divider:enable_64_div|enabled_out_reg                  ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|count[10]                                                     ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|count[11]                                                     ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|count[12]                                                     ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|count[13]                                                     ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|count[14]                                                     ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|count[27]                                                     ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|count[28]                                                     ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|count[29]                                                     ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|count[30]                                                     ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|count[6]                                                      ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|count[8]                                                      ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|count[9]                                                      ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insn.dec_call                                                          ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insn.dec_dup_stk_b                                                     ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insn.dec_emulate                                                       ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insn.dec_pop_down                                                      ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insn.dec_push_sp_add                                                   ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insns[1].dec_call                                                      ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insns[1].dec_dup_stk_b                                                 ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insns[1].dec_pop_down                                                  ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insns[1].dec_push_sp_add                                               ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insns[2].dec_dup_stk_b                                                 ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insns[2].dec_pop_down                                                  ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insns[3].dec_call                                                      ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insns[3].dec_dup_stk_b                                                 ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insns[3].dec_pop_down                                                  ;
; 17.344 ; 17.564       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insns[3].dec_push_sp_add                                               ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[32][0]     ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[32][1]     ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[32][2]     ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[32][3]     ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[32][4]     ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[32][5]     ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[32][6]     ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[32][7]     ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[34][0]     ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[34][1]     ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[34][2]     ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[34][3]     ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[34][4]     ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[34][5]     ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[34][6]     ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[34][7]     ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[40][0]     ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[40][1]     ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[40][2]     ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[40][3]     ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[40][4]     ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[40][5]     ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[40][6]     ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[40][7]     ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[42][0]     ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[42][1]     ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[42][2]     ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[42][3]     ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[42][4]     ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[42][5]     ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[42][6]     ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[42][7]     ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|VOLUME_OUT_L_REG[0] ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|VOLUME_OUT_L_REG[1] ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|VOLUME_OUT_L_REG[5] ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|VOLUME_OUT_L_REG[6] ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|VOLUME_OUT_L_REG[9] ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|VOLUME_OUT_R_REG[6] ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p1[10]                                                                                            ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p1[11]                                                                                            ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p1[12]                                                                                            ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p1[2]                                                                                             ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p1[3]                                                                                             ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p1[4]                                                                                             ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p1[5]                                                                                             ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p1[6]                                                                                             ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_left|r_data_fwd_p1[7]                                                                                             ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                  ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                        ; Clock Edge ; Target                                                                                             ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------+
; 17.594 ; 17.594       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.594 ; 17.594       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.594 ; 17.594       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.594 ; 17.594       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3]                      ;
; 17.594 ; 17.594       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 17.599 ; 17.599       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.599 ; 17.599       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.604 ; 17.604       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.637 ; 17.637       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.642 ; 17.642       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.642 ; 17.642       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.646 ; 17.646       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.646 ; 17.646       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.646 ; 17.646       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.646 ; 17.646       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3]                      ;
; 17.646 ; 17.646       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'mcc_pll3|altpll_component|auto_generated|pll1|clk[0]'                                                                                            ;
+--------+--------------+----------------+------------------+------------------------------------------------------+------------+--------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                ; Clock Edge ; Target                                                       ;
+--------+--------------+----------------+------------------+------------------------------------------------------+------------+--------------------------------------------------------------+
; 33.028 ; 33.248       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dminus~en                   ;
; 33.028 ; 33.248       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dminus~reg0                 ;
; 33.028 ; 33.248       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dplus~en                    ;
; 33.028 ; 33.248       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dplus~reg0                  ;
; 33.028 ; 33.248       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rden_sig                    ;
; 33.028 ; 33.248       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|send_frame                  ;
; 33.028 ; 33.248       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.Idle           ;
; 33.028 ; 33.248       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.end_send1      ;
; 33.028 ; 33.248       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.end_send2      ;
; 33.028 ; 33.248       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.reset_released ;
; 33.028 ; 33.248       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.reset_start    ;
; 33.028 ; 33.248       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.send1          ;
; 33.028 ; 33.248       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.send2          ;
; 33.028 ; 33.248       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.send3          ;
; 33.028 ; 33.248       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.send_bit0      ;
; 33.028 ; 33.248       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.send_bit1      ;
; 33.028 ; 33.248       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.send_bit2      ;
; 33.028 ; 33.248       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.send_bit3      ;
; 33.028 ; 33.248       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.send_bit4      ;
; 33.028 ; 33.248       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.send_complete  ;
; 33.029 ; 33.249       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[0]              ;
; 33.029 ; 33.249       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[1]              ;
; 33.029 ; 33.249       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[2]              ;
; 33.029 ; 33.249       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[3]              ;
; 33.029 ; 33.249       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[4]              ;
; 33.029 ; 33.249       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[5]              ;
; 33.029 ; 33.249       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[6]              ;
; 33.029 ; 33.249       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[7]              ;
; 33.029 ; 33.249       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dm_previous                 ;
; 33.029 ; 33.249       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dp_previous                 ;
; 33.029 ; 33.249       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_byte_tosend[0]           ;
; 33.029 ; 33.249       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_byte_tosend[1]           ;
; 33.029 ; 33.249       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_byte_tosend[2]           ;
; 33.029 ; 33.249       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_byte_tosend[3]           ;
; 33.029 ; 33.249       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_byte_tosend[4]           ;
; 33.029 ; 33.249       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_byte_tosend[5]           ;
; 33.029 ; 33.249       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_byte_tosend[6]           ;
; 33.029 ; 33.249       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_byte_tosend[7]           ;
; 33.029 ; 33.249       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.send_bit5      ;
; 33.029 ; 33.249       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.send_bit6      ;
; 33.029 ; 33.249       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.send_bit7      ;
; 33.030 ; 33.250       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[0]                ;
; 33.030 ; 33.250       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[1]                ;
; 33.030 ; 33.250       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[2]                ;
; 33.030 ; 33.250       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[3]                ;
; 33.030 ; 33.250       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[4]                ;
; 33.030 ; 33.250       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[5]                ;
; 33.030 ; 33.250       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[6]                ;
; 33.030 ; 33.250       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[7]                ;
; 33.030 ; 33.250       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dminus_buf2                 ;
; 33.030 ; 33.250       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dp2_prev~_emulated          ;
; 33.030 ; 33.250       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|reg_10bits_receive[0]       ;
; 33.030 ; 33.250       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|reg_10bits_receive[1]       ;
; 33.030 ; 33.250       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|reg_10bits_receive[2]       ;
; 33.030 ; 33.250       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|reg_10bits_receive[3]       ;
; 33.030 ; 33.250       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|reg_10bits_receive[4]       ;
; 33.030 ; 33.250       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|reg_10bits_receive[5]       ;
; 33.030 ; 33.250       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|reg_10bits_receive[6]       ;
; 33.030 ; 33.250       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|reg_10bits_receive[7]       ;
; 33.030 ; 33.250       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|reg_10bits_receive[8]       ;
; 33.030 ; 33.250       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|reg_10bits_receive[9]       ;
; 33.030 ; 33.250       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state3           ;
; 33.030 ; 33.250       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state4           ;
; 33.030 ; 33.250       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|val                         ;
; 33.031 ; 33.251       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_rom[0]              ;
; 33.031 ; 33.251       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_rom[1]              ;
; 33.031 ; 33.251       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_rom[2]              ;
; 33.031 ; 33.251       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_rom[3]              ;
; 33.031 ; 33.251       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_rom[4]              ;
; 33.031 ; 33.251       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_rom[5]              ;
; 33.031 ; 33.251       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_rom[6]              ;
; 33.031 ; 33.251       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_rom[7]              ;
; 33.031 ; 33.251       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_rom[8]              ;
; 33.031 ; 33.251       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dm1_last~_emulated          ;
; 33.031 ; 33.251       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dp1_last~_emulated          ;
; 33.031 ; 33.251       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dplus_buf1                  ;
; 33.031 ; 33.251       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dplus_buf2                  ;
; 33.032 ; 33.252       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|joyleft_out[0]              ;
; 33.032 ; 33.252       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|joyleft_out[1]              ;
; 33.032 ; 33.252       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|joyleft_out[2]              ;
; 33.032 ; 33.252       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|joyleft_out[3]              ;
; 33.032 ; 33.252       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|joyright_out[3]             ;
; 33.035 ; 33.255       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[0]                ;
; 33.035 ; 33.255       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[1]                ;
; 33.035 ; 33.255       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[2]                ;
; 33.035 ; 33.255       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[3]                ;
; 33.035 ; 33.255       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[4]                ;
; 33.035 ; 33.255       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[5]                ;
; 33.035 ; 33.255       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[6]                ;
; 33.035 ; 33.255       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[7]                ;
; 33.035 ; 33.255       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dminus_buf1                 ;
; 33.035 ; 33.255       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[0]                  ;
; 33.035 ; 33.255       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[1]                  ;
; 33.035 ; 33.255       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[2]                  ;
; 33.035 ; 33.255       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[3]                  ;
; 33.035 ; 33.255       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|read_byte_valid             ;
; 33.035 ; 33.255       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|reg_10bits[0]               ;
; 33.035 ; 33.255       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|reg_10bits[1]               ;
; 33.035 ; 33.255       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|reg_10bits[2]               ;
; 33.035 ; 33.255       ; 0.220          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|reg_10bits[3]               ;
+--------+--------------+----------------+------------------+------------------------------------------------------+------------+--------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'altera_reserved_tck'                                                                                                                                                                                                                                                     ;
+--------+--------------+----------------+------------------+---------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock               ; Clock Edge ; Target                                                                                                                                                                                                                ;
+--------+--------------+----------------+------------------+---------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 49.479 ; 49.714       ; 0.235          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ;
; 49.479 ; 49.714       ; 0.235          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                           ;
; 49.479 ; 49.714       ; 0.235          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ;
; 49.479 ; 49.714       ; 0.235          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                           ;
; 49.482 ; 49.717       ; 0.235          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_datain_reg0                                      ;
; 49.482 ; 49.717       ; 0.235          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_datain_reg0                                      ;
; 49.539 ; 49.759       ; 0.220          ; High Pulse Width ; altera_reserved_tck ; Fall       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ;
; 49.588 ; 49.776       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                                                        ;
; 49.588 ; 49.776       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0]                                              ;
; 49.588 ; 49.776       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1]                                              ;
; 49.588 ; 49.776       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2]                                              ;
; 49.588 ; 49.776       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3]                                              ;
; 49.588 ; 49.776       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg                                                         ;
; 49.588 ; 49.776       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]                                                   ;
; 49.588 ; 49.776       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1]                                                   ;
; 49.588 ; 49.776       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2]                                                   ;
; 49.588 ; 49.776       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3]                                                   ;
; 49.588 ; 49.776       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4]                                                   ;
; 49.588 ; 49.776       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                        ;
; 49.588 ; 49.776       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]                                        ;
; 49.588 ; 49.776       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2]                                        ;
; 49.588 ; 49.776       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                                                        ;
; 49.588 ; 49.776       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]                                                   ;
; 49.588 ; 49.776       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]                                                   ;
; 49.588 ; 49.776       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]                                                   ;
; 49.588 ; 49.776       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]                                                   ;
; 49.588 ; 49.776       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]                                                   ;
; 49.588 ; 49.776       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5]                                                   ;
; 49.588 ; 49.776       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[6]                                                   ;
; 49.588 ; 49.776       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7]                                                   ;
; 49.588 ; 49.776       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8]                                                   ;
; 49.588 ; 49.776       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]                                                   ;
; 49.588 ; 49.776       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1]                                                   ;
; 49.588 ; 49.776       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2]                                                   ;
; 49.588 ; 49.776       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3]                                                   ;
; 49.588 ; 49.776       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4]                                                   ;
; 49.588 ; 49.776       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[5]                                                   ;
; 49.588 ; 49.776       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[6]                                                   ;
; 49.588 ; 49.776       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7]                                                   ;
; 49.588 ; 49.776       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                        ;
; 49.588 ; 49.776       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]                                        ;
; 49.588 ; 49.776       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2]                                        ;
; 49.588 ; 49.776       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                                                                                           ;
; 49.588 ; 49.776       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                           ;
; 49.588 ; 49.776       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                                                                                           ;
; 49.588 ; 49.776       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                                                                                           ;
; 49.588 ; 49.776       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                                                                                                                                           ;
; 49.588 ; 49.776       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                             ;
; 49.588 ; 49.776       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                             ;
; 49.588 ; 49.776       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0                                                                                                                                        ;
; 49.588 ; 49.776       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                        ;
; 49.588 ; 49.776       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|reset_ena_reg                                                                                                                                           ;
; 49.588 ; 49.776       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0]                                                                                                                                    ;
; 49.588 ; 49.776       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][1]                                                                                                                                    ;
; 49.588 ; 49.776       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][2]                                                                                                                                    ;
; 49.588 ; 49.776       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3]                                                                                                                                    ;
; 49.588 ; 49.776       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][4]                                                                                                                                    ;
; 49.588 ; 49.776       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                      ;
; 49.588 ; 49.776       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5]                                                                                                                      ;
; 49.588 ; 49.776       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6]                                                                                                                      ;
; 49.588 ; 49.776       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7]                                                                                                                      ;
; 49.588 ; 49.776       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8]                                                                                                                      ;
; 49.588 ; 49.776       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0]                                                                                                                    ;
; 49.588 ; 49.776       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1]                                                                                                                    ;
; 49.588 ; 49.776       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2]                                                                                                                    ;
; 49.589 ; 49.777       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]                                                   ;
; 49.589 ; 49.777       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]                                                   ;
; 49.589 ; 49.777       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]                                                   ;
; 49.589 ; 49.777       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]                                                   ;
; 49.589 ; 49.777       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]                                                   ;
; 49.589 ; 49.777       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5]                                                   ;
; 49.589 ; 49.777       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[6]                                                   ;
; 49.589 ; 49.777       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7]                                                   ;
; 49.589 ; 49.777       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8]                                                   ;
; 49.589 ; 49.777       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[5]                                                   ;
; 49.589 ; 49.777       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[6]                                                   ;
; 49.589 ; 49.777       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7]                                                   ;
; 49.589 ; 49.777       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[0]      ;
; 49.589 ; 49.777       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[1]      ;
; 49.589 ; 49.777       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[2]      ;
; 49.589 ; 49.777       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[3]      ;
; 49.589 ; 49.777       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[0] ;
; 49.589 ; 49.777       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[1] ;
; 49.589 ; 49.777       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[2] ;
; 49.589 ; 49.777       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[3] ;
; 49.589 ; 49.777       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                                                                                           ;
; 49.589 ; 49.777       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                                                                                           ;
; 49.589 ; 49.777       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2]                                                                                                                                           ;
; 49.589 ; 49.777       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                                                                                                                                           ;
; 49.589 ; 49.777       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                                                                                                                                           ;
; 49.589 ; 49.777       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0]                                                                                                                                    ;
; 49.589 ; 49.777       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1]                                                                                                                                    ;
; 49.589 ; 49.777       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2]                                                                                                                                    ;
; 49.589 ; 49.777       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3]                                                                                                                                    ;
; 49.589 ; 49.777       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][4]                                                                                                                                    ;
; 49.591 ; 49.779       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[0]      ;
; 49.591 ; 49.779       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[1]      ;
; 49.591 ; 49.779       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[2]      ;
; 49.591 ; 49.779       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[3]      ;
; 49.591 ; 49.779       ; 0.188          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[0] ;
+--------+--------------+----------------+------------------+---------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'FPGA_CLK'                                                                                                                       ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------+
; Slack   ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                                                 ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------+
; 99.796  ; 99.796       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 99.796  ; 99.796       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 99.798  ; 99.798       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                                   ;
; 99.798  ; 99.798       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|observablevcoout                         ;
; 99.818  ; 99.818       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                       ;
; 99.850  ; 99.850       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 99.852  ; 99.852       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|inclk[0]                                 ;
; 100.000 ; 100.000      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                       ;
; 100.000 ; 100.000      ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                       ;
; 100.147 ; 100.147      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|inclk[0]                                 ;
; 100.149 ; 100.149      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 100.182 ; 100.182      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                       ;
; 100.200 ; 100.200      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                                   ;
; 100.200 ; 100.200      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|observablevcoout                         ;
; 100.202 ; 100.202      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 100.202 ; 100.202      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 196.000 ; 200.000      ; 4.000          ; Port Rate        ; FPGA_CLK ; Rise       ; FPGA_CLK                                                                               ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                                            ;
+---------------------+---------------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port           ; Clock Port          ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+---------------------+---------------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]         ; FPGA_CLK            ; 2.724 ; 2.903 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]        ; FPGA_CLK            ; 2.705 ; 2.884 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]        ; FPGA_CLK            ; 2.705 ; 2.884 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]        ; FPGA_CLK            ; 2.705 ; 2.884 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]        ; FPGA_CLK            ; 2.708 ; 2.887 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]        ; FPGA_CLK            ; 2.717 ; 2.896 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]        ; FPGA_CLK            ; 2.709 ; 2.888 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]        ; FPGA_CLK            ; 2.708 ; 2.887 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]        ; FPGA_CLK            ; 2.656 ; 2.834 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]        ; FPGA_CLK            ; 2.717 ; 2.896 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]        ; FPGA_CLK            ; 2.724 ; 2.903 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]       ; FPGA_CLK            ; 2.719 ; 2.898 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]       ; FPGA_CLK            ; 2.719 ; 2.898 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]       ; FPGA_CLK            ; 2.719 ; 2.898 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]       ; FPGA_CLK            ; 2.706 ; 2.885 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]       ; FPGA_CLK            ; 2.706 ; 2.885 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]       ; FPGA_CLK            ; 2.706 ; 2.885 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_DAT0             ; FPGA_CLK            ; 3.609 ; 3.785 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; altera_reserved_tdi ; altera_reserved_tck ; 2.202 ; 2.384 ; Rise       ; altera_reserved_tck                                                           ;
; altera_reserved_tms ; altera_reserved_tck ; 7.467 ; 7.629 ; Rise       ; altera_reserved_tck                                                           ;
; dminus1             ; FPGA_CLK            ; 3.767 ; 4.210 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dminus2             ; FPGA_CLK            ; 1.134 ; 1.527 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1              ; FPGA_CLK            ; 4.452 ; 4.920 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2              ; FPGA_CLK            ; 1.160 ; 1.573 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1              ; FPGA_CLK            ; 5.018 ; 5.462 ; Fall       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2              ; FPGA_CLK            ; 1.342 ; 1.765 ; Fall       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
+---------------------+---------------------+-------+-------+------------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                               ;
+---------------------+---------------------+--------+--------+------------+-------------------------------------------------------------------------------+
; Data Port           ; Clock Port          ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                               ;
+---------------------+---------------------+--------+--------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]         ; FPGA_CLK            ; -1.783 ; -1.961 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]        ; FPGA_CLK            ; -1.828 ; -2.007 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]        ; FPGA_CLK            ; -1.828 ; -2.007 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]        ; FPGA_CLK            ; -1.828 ; -2.007 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]        ; FPGA_CLK            ; -1.831 ; -2.010 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]        ; FPGA_CLK            ; -1.840 ; -2.019 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]        ; FPGA_CLK            ; -1.832 ; -2.011 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]        ; FPGA_CLK            ; -1.831 ; -2.010 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]        ; FPGA_CLK            ; -1.783 ; -1.961 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]        ; FPGA_CLK            ; -1.840 ; -2.019 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]        ; FPGA_CLK            ; -1.847 ; -2.026 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]       ; FPGA_CLK            ; -1.842 ; -2.021 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]       ; FPGA_CLK            ; -1.842 ; -2.021 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]       ; FPGA_CLK            ; -1.842 ; -2.021 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]       ; FPGA_CLK            ; -1.829 ; -2.008 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]       ; FPGA_CLK            ; -1.829 ; -2.008 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]       ; FPGA_CLK            ; -1.829 ; -2.008 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_DAT0             ; FPGA_CLK            ; -2.655 ; -2.831 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; altera_reserved_tdi ; altera_reserved_tck ; 1.223  ; 1.081  ; Rise       ; altera_reserved_tck                                                           ;
; altera_reserved_tms ; altera_reserved_tck ; -1.318 ; -1.453 ; Rise       ; altera_reserved_tck                                                           ;
; dminus1             ; FPGA_CLK            ; -2.952 ; -3.380 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dminus2             ; FPGA_CLK            ; -0.224 ; -0.604 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1              ; FPGA_CLK            ; -3.645 ; -4.098 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2              ; FPGA_CLK            ; -0.281 ; -0.681 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1              ; FPGA_CLK            ; -3.731 ; -4.160 ; Fall       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2              ; FPGA_CLK            ; -0.272 ; -0.686 ; Fall       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
+---------------------+---------------------+--------+--------+------------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                                    ;
+---------------------+---------------------+--------+--------+------------+-------------------------------------------------------------------------------+
; Data Port           ; Clock Port          ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                               ;
+---------------------+---------------------+--------+--------+------------+-------------------------------------------------------------------------------+
; SDRAM_A[*]          ; FPGA_CLK            ; 5.688  ; 5.935  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]         ; FPGA_CLK            ; 3.084  ; 2.871  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]         ; FPGA_CLK            ; 3.084  ; 2.871  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]         ; FPGA_CLK            ; 3.087  ; 2.874  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]         ; FPGA_CLK            ; 3.087  ; 2.874  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]         ; FPGA_CLK            ; 3.074  ; 2.861  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]         ; FPGA_CLK            ; 3.074  ; 2.861  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]         ; FPGA_CLK            ; 3.072  ; 2.859  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]         ; FPGA_CLK            ; 2.251  ; 2.177  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]         ; FPGA_CLK            ; 5.688  ; 5.935  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]         ; FPGA_CLK            ; 3.073  ; 2.860  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]        ; FPGA_CLK            ; 3.084  ; 2.871  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]        ; FPGA_CLK            ; 3.073  ; 2.860  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]         ; FPGA_CLK            ; 5.701  ; 5.948  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]        ; FPGA_CLK            ; 5.701  ; 5.948  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]        ; FPGA_CLK            ; 2.264  ; 2.190  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N         ; FPGA_CLK            ; 2.265  ; 2.191  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N          ; FPGA_CLK            ; 3.085  ; 2.872  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]         ; FPGA_CLK            ; 5.026  ; 5.450  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]        ; FPGA_CLK            ; 3.455  ; 3.310  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]        ; FPGA_CLK            ; 3.455  ; 3.310  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]        ; FPGA_CLK            ; 3.455  ; 3.310  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]        ; FPGA_CLK            ; 5.024  ; 5.448  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]        ; FPGA_CLK            ; 5.015  ; 5.439  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]        ; FPGA_CLK            ; 2.410  ; 2.389  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]        ; FPGA_CLK            ; 3.272  ; 3.118  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]        ; FPGA_CLK            ; 3.086  ; 2.873  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]        ; FPGA_CLK            ; 3.443  ; 3.298  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]        ; FPGA_CLK            ; 5.008  ; 5.432  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]       ; FPGA_CLK            ; 3.441  ; 3.296  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]       ; FPGA_CLK            ; 3.441  ; 3.296  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]       ; FPGA_CLK            ; 3.441  ; 3.296  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]       ; FPGA_CLK            ; 5.026  ; 5.450  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]       ; FPGA_CLK            ; 3.454  ; 3.309  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]       ; FPGA_CLK            ; 3.454  ; 3.309  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH_n        ; FPGA_CLK            ; 3.074  ; 2.861  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML_n        ; FPGA_CLK            ; 3.086  ; 2.873  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N         ; FPGA_CLK            ; 3.085  ; 2.872  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N          ; FPGA_CLK            ; 5.703  ; 5.950  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L             ; FPGA_CLK            ; 5.983  ; 6.371  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R             ; FPGA_CLK            ; 3.057  ; 2.978  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK              ; FPGA_CLK            ; 4.937  ; 4.874  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD              ; FPGA_CLK            ; 4.416  ; 4.390  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3             ; FPGA_CLK            ; 4.720  ; 4.760  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK           ; FPGA_CLK            ; 11.898 ;        ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK           ; FPGA_CLK            ;        ; 12.246 ; Fall       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]            ; FPGA_CLK            ; 4.868  ; 5.254  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[0]           ; FPGA_CLK            ; 2.252  ; 2.178  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[1]           ; FPGA_CLK            ; 4.868  ; 5.254  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[2]           ; FPGA_CLK            ; 2.251  ; 2.177  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[3]           ; FPGA_CLK            ; 2.254  ; 2.180  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
; VGA_G[*]            ; FPGA_CLK            ; 4.870  ; 5.256  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[0]           ; FPGA_CLK            ; 2.253  ; 2.179  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[1]           ; FPGA_CLK            ; 2.253  ; 2.179  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[2]           ; FPGA_CLK            ; 2.253  ; 2.179  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[3]           ; FPGA_CLK            ; 4.870  ; 5.256  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
; altera_reserved_tdo ; altera_reserved_tck ; 12.491 ; 13.517 ; Fall       ; altera_reserved_tck                                                           ;
; dminus1             ; FPGA_CLK            ; 5.783  ; 5.760  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dminus2             ; FPGA_CLK            ; 7.734  ; 7.732  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1              ; FPGA_CLK            ; 8.753  ; 8.312  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2              ; FPGA_CLK            ; 7.773  ; 7.771  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
+---------------------+---------------------+--------+--------+------------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                                            ;
+---------------------+---------------------+--------+--------+------------+-------------------------------------------------------------------------------+
; Data Port           ; Clock Port          ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                               ;
+---------------------+---------------------+--------+--------+------------+-------------------------------------------------------------------------------+
; SDRAM_A[*]          ; FPGA_CLK            ; 1.524  ; 1.450  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]         ; FPGA_CLK            ; 2.324  ; 2.116  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]         ; FPGA_CLK            ; 2.324  ; 2.116  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]         ; FPGA_CLK            ; 2.327  ; 2.119  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]         ; FPGA_CLK            ; 2.327  ; 2.119  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]         ; FPGA_CLK            ; 2.315  ; 2.107  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]         ; FPGA_CLK            ; 2.315  ; 2.107  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]         ; FPGA_CLK            ; 2.313  ; 2.105  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]         ; FPGA_CLK            ; 1.524  ; 1.450  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]         ; FPGA_CLK            ; 4.929  ; 5.181  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]         ; FPGA_CLK            ; 2.314  ; 2.106  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]        ; FPGA_CLK            ; 2.324  ; 2.116  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]        ; FPGA_CLK            ; 2.314  ; 2.106  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]         ; FPGA_CLK            ; 1.536  ; 1.462  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]        ; FPGA_CLK            ; 4.941  ; 5.193  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]        ; FPGA_CLK            ; 1.536  ; 1.462  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N         ; FPGA_CLK            ; 1.538  ; 1.464  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N          ; FPGA_CLK            ; 2.326  ; 2.118  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]         ; FPGA_CLK            ; 1.683  ; 1.663  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]        ; FPGA_CLK            ; 2.694  ; 2.556  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]        ; FPGA_CLK            ; 2.694  ; 2.556  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]        ; FPGA_CLK            ; 2.694  ; 2.556  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]        ; FPGA_CLK            ; 4.297  ; 4.722  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]        ; FPGA_CLK            ; 4.288  ; 4.713  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]        ; FPGA_CLK            ; 1.683  ; 1.663  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]        ; FPGA_CLK            ; 2.511  ; 2.364  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]        ; FPGA_CLK            ; 2.326  ; 2.118  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]        ; FPGA_CLK            ; 2.682  ; 2.544  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]        ; FPGA_CLK            ; 4.281  ; 4.706  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]       ; FPGA_CLK            ; 2.680  ; 2.542  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]       ; FPGA_CLK            ; 2.680  ; 2.542  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]       ; FPGA_CLK            ; 2.680  ; 2.542  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]       ; FPGA_CLK            ; 4.299  ; 4.724  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]       ; FPGA_CLK            ; 2.693  ; 2.555  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]       ; FPGA_CLK            ; 2.693  ; 2.555  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH_n        ; FPGA_CLK            ; 2.315  ; 2.107  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML_n        ; FPGA_CLK            ; 2.326  ; 2.118  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N         ; FPGA_CLK            ; 2.326  ; 2.118  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N          ; FPGA_CLK            ; 4.943  ; 5.195  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L             ; FPGA_CLK            ; 5.128  ; 5.516  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R             ; FPGA_CLK            ; 2.213  ; 2.135  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK              ; FPGA_CLK            ; 4.019  ; 3.956  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD              ; FPGA_CLK            ; 3.520  ; 3.491  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3             ; FPGA_CLK            ; 3.808  ; 3.850  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK           ; FPGA_CLK            ; 11.109 ;        ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK           ; FPGA_CLK            ;        ; 11.459 ; Fall       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]            ; FPGA_CLK            ; 1.524  ; 1.450  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[0]           ; FPGA_CLK            ; 1.525  ; 1.451  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[1]           ; FPGA_CLK            ; 4.141  ; 4.527  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[2]           ; FPGA_CLK            ; 1.524  ; 1.450  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[3]           ; FPGA_CLK            ; 1.527  ; 1.453  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
; VGA_G[*]            ; FPGA_CLK            ; 1.526  ; 1.452  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[0]           ; FPGA_CLK            ; 1.526  ; 1.452  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[1]           ; FPGA_CLK            ; 1.526  ; 1.452  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[2]           ; FPGA_CLK            ; 1.526  ; 1.452  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[3]           ; FPGA_CLK            ; 4.143  ; 4.529  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
; altera_reserved_tdo ; altera_reserved_tck ; 10.170 ; 11.196 ; Fall       ; altera_reserved_tck                                                           ;
; dminus1             ; FPGA_CLK            ; 5.167  ; 5.144  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dminus2             ; FPGA_CLK            ; 7.032  ; 7.029  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1              ; FPGA_CLK            ; 8.132  ; 7.692  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2              ; FPGA_CLK            ; 7.069  ; 7.068  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
+---------------------+---------------------+--------+--------+------------+-------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 3.156 ; 3.080 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.814 ; 3.738 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.814 ; 3.738 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.814 ; 3.738 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 6.749 ; 7.110 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 7.099 ; 7.460 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 4.145 ; 4.059 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 4.151 ; 4.065 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 4.322 ; 4.174 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 4.113 ; 4.037 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 6.251 ; 6.612 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.489 ; 3.413 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.489 ; 3.413 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.489 ; 3.413 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 5.586 ; 5.947 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 3.156 ; 3.080 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 3.156 ; 3.080 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 4.658 ; 4.510 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 5.412 ; 5.336 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dminus2       ; FPGA_CLK   ; 7.768 ; 7.682 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1        ; FPGA_CLK   ; 7.919 ; 8.280 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2        ; FPGA_CLK   ; 7.951 ; 7.865 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                             ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.327 ; 2.251 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.958 ; 2.882 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.958 ; 2.882 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.958 ; 2.882 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 5.873 ; 6.234 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 6.209 ; 6.570 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.269 ; 3.183 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.275 ; 3.189 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.403 ; 3.255 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.245 ; 3.169 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 5.395 ; 5.756 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.646 ; 2.570 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.646 ; 2.570 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.646 ; 2.570 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 4.756 ; 5.117 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.327 ; 2.251 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.327 ; 2.251 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.725 ; 3.577 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 4.818 ; 4.742 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dminus2       ; FPGA_CLK   ; 7.073 ; 6.987 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1        ; FPGA_CLK   ; 7.322 ; 7.683 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2        ; FPGA_CLK   ; 7.248 ; 7.162 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                            ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 3.113     ; 3.189     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.771     ; 3.847     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.771     ; 3.847     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.771     ; 3.847     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 7.147     ; 6.786     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 7.484     ; 7.123     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 4.080     ; 4.166     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 4.110     ; 4.196     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 4.199     ; 4.347     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 4.060     ; 4.136     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 6.648     ; 6.287     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.450     ; 3.526     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.450     ; 3.526     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.450     ; 3.526     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 5.980     ; 5.619     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 3.113     ; 3.189     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 3.113     ; 3.189     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 4.593     ; 4.741     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 5.376     ; 5.452     ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dminus2       ; FPGA_CLK   ; 7.698     ; 7.784     ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1        ; FPGA_CLK   ; 8.337     ; 7.976     ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2        ; FPGA_CLK   ; 7.847     ; 7.933     ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                                    ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.282     ; 2.358     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.913     ; 2.989     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.913     ; 2.989     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.913     ; 2.989     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 6.269     ; 5.908     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 6.593     ; 6.232     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.203     ; 3.289     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.231     ; 3.317     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.279     ; 3.427     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.191     ; 3.267     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 5.790     ; 5.429     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.606     ; 2.682     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.606     ; 2.682     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.606     ; 2.682     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 5.149     ; 4.788     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.282     ; 2.358     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.282     ; 2.358     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.656     ; 3.804     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 4.781     ; 4.857     ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dminus2       ; FPGA_CLK   ; 7.001     ; 7.087     ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1        ; FPGA_CLK   ; 7.738     ; 7.377     ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2        ; FPGA_CLK   ; 7.145     ; 7.231     ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+


----------------------------------------------
; Slow 1200mV 85C Model Metastability Report ;
----------------------------------------------
No synchronizer chains to report.


+---------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Fmax Summary                                                                                   ;
+------------+-----------------+-------------------------------------------------------------------------------+------+
; Fmax       ; Restricted Fmax ; Clock Name                                                                    ; Note ;
+------------+-----------------+-------------------------------------------------------------------------------+------+
; 56.14 MHz  ; 56.14 MHz       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;      ;
; 74.34 MHz  ; 74.34 MHz       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;      ;
; 120.13 MHz ; 120.13 MHz      ; altera_reserved_tck                                                           ;      ;
; 125.38 MHz ; 125.38 MHz      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;      ;
; 248.32 MHz ; 248.32 MHz      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;      ;
+------------+-----------------+-------------------------------------------------------------------------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+--------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup Summary                                                                     ;
+-------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                         ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; -7.366 ; -824.594      ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.668  ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 4.783  ; 0.000         ;
; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ; 26.607 ; 0.000         ;
; altera_reserved_tck                                                           ; 45.838 ; 0.000         ;
+-------------------------------------------------------------------------------+--------+---------------+


+-------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold Summary                                                                     ;
+-------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                         ; Slack ; End Point TNS ;
+-------------------------------------------------------------------------------+-------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.329 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.350 ; 0.000         ;
; altera_reserved_tck                                                           ; 0.362 ; 0.000         ;
; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ; 0.363 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.364 ; 0.000         ;
+-------------------------------------------------------------------------------+-------+---------------+


+--------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery Summary                                                                  ;
+-------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                         ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 7.260  ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.197  ; 0.000         ;
; altera_reserved_tck                                                           ; 48.098 ; 0.000         ;
; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ; 63.499 ; 0.000         ;
+-------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal Summary                                                                   ;
+-------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                         ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------+--------+---------------+
; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ; -0.036 ; -0.981        ;
; altera_reserved_tck                                                           ; 1.150  ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 1.311  ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1.973  ; 0.000         ;
+-------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width Summary                                                       ;
+-------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                         ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 4.129  ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.583  ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.323 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]  ; 17.589 ; 0.000         ;
; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ; 32.979 ; 0.000         ;
; altera_reserved_tck                                                           ; 49.393 ; 0.000         ;
; FPGA_CLK                                                                      ; 99.778 ; 0.000         ;
+-------------------------------------------------------------------------------+--------+---------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                         ;
+--------+--------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                        ; To Node                                                                                                                 ; Launch Clock                                         ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; -7.366 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.732     ; 5.781      ;
; -7.322 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.733     ; 5.736      ;
; -7.221 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.732     ; 5.636      ;
; -7.047 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.722     ; 5.472      ;
; -7.043 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[38] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.733     ; 5.457      ;
; -6.985 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[27] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.733     ; 5.399      ;
; -6.928 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[5]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.722     ; 5.353      ;
; -6.927 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[2]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.105     ; 4.969      ;
; -6.892 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[2]   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.108     ; 4.931      ;
; -6.891 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[7] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[27]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.097     ; 4.941      ;
; -6.891 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[6]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[28]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.097     ; 4.941      ;
; -6.886 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[10]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.113     ; 4.920      ;
; -6.884 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[7]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[27]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.097     ; 4.934      ;
; -6.864 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[18] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.734     ; 5.277      ;
; -6.842 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.716     ; 5.273      ;
; -6.839 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[41] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.735     ; 5.251      ;
; -6.839 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[2]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.088     ; 4.898      ;
; -6.828 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[4] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.721     ; 5.254      ;
; -6.826 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.717     ; 5.256      ;
; -6.822 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[37] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.736     ; 5.233      ;
; -6.821 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[6]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[27]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.097     ; 4.871      ;
; -6.820 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[0]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.730     ; 5.237      ;
; -6.818 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[29] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.722     ; 5.243      ;
; -6.813 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[1]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.072     ; 4.888      ;
; -6.804 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[2]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.094     ; 4.857      ;
; -6.799 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[7] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[28]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.097     ; 4.849      ;
; -6.792 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[7]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[28]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.097     ; 4.842      ;
; -6.786 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[1]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.072     ; 4.861      ;
; -6.779 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|doReg[2]    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.763     ; 5.163      ;
; -6.768 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[6] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[28]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.097     ; 4.818      ;
; -6.761 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.721     ; 5.187      ;
; -6.743 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[2]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.732     ; 5.158      ;
; -6.734 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.716     ; 5.165      ;
; -6.720 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[7] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[29]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.095     ; 4.772      ;
; -6.719 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[39] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.735     ; 5.131      ;
; -6.718 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.717     ; 5.148      ;
; -6.713 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[7]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[29]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.095     ; 4.765      ;
; -6.705 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[1]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.072     ; 4.780      ;
; -6.695 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[1]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.078     ; 4.764      ;
; -6.692 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[6] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[27]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.097     ; 4.742      ;
; -6.678 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[1]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.072     ; 4.753      ;
; -6.677 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_reg[2]                   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.085     ; 4.739      ;
; -6.674 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.716     ; 5.105      ;
; -6.662 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[4] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.722     ; 5.087      ;
; -6.650 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[6]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[29]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.095     ; 4.702      ;
; -6.642 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[2]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.763     ; 5.026      ;
; -6.630 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[6]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[30]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.095     ; 4.682      ;
; -6.626 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[4] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[0]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.719     ; 5.054      ;
; -6.610 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[25] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.099     ; 4.658      ;
; -6.610 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[24] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.099     ; 4.658      ;
; -6.609 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[6]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.099     ; 4.657      ;
; -6.604 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[11] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.726     ; 5.025      ;
; -6.602 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[1]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.733     ; 5.016      ;
; -6.595 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.722     ; 5.020      ;
; -6.594 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[15] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.734     ; 5.007      ;
; -6.587 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[1]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.078     ; 4.656      ;
; -6.575 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[6]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[26]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.095     ; 4.627      ;
; -6.570 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[7] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[23]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.098     ; 4.619      ;
; -6.566 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.716     ; 4.997      ;
; -6.563 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[7]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[23]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.098     ; 4.612      ;
; -6.562 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[34] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.734     ; 4.975      ;
; -6.561 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[11] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.710     ; 4.998      ;
; -6.559 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[1]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.089     ; 4.617      ;
; -6.559 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[0]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.719     ; 4.987      ;
; -6.546 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[10] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.734     ; 4.959      ;
; -6.538 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[7] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[30]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.095     ; 4.590      ;
; -6.535 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[4] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[0]                                                                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.085     ; 4.597      ;
; -6.531 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[7]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[30]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.095     ; 4.583      ;
; -6.521 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[6] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[29]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.095     ; 4.573      ;
; -6.519 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[6]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[24]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.095     ; 4.571      ;
; -6.512 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[27] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.717     ; 4.942      ;
; -6.507 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[6] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[30]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.095     ; 4.559      ;
; -6.500 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[6]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[23]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.098     ; 4.549      ;
; -6.496 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[16] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.735     ; 4.908      ;
; -6.494 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[22] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.736     ; 4.905      ;
; -6.487 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[26] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.734     ; 4.900      ;
; -6.483 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[7] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[26]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.095     ; 4.535      ;
; -6.481 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[7] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[31]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.722     ; 4.906      ;
; -6.476 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[7]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[26]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.095     ; 4.528      ;
; -6.474 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[7]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[31]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.722     ; 4.899      ;
; -6.468 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.706     ; 4.909      ;
; -6.468 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[1] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[0]                                                                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.085     ; 4.530      ;
; -6.464 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[4] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[38] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.722     ; 4.889      ;
; -6.453 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[11] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.710     ; 4.890      ;
; -6.452 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[6] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[26]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.095     ; 4.504      ;
; -6.451 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[1]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.089     ; 4.509      ;
; -6.450 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[29] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.706     ; 4.891      ;
; -6.448 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[41] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.719     ; 4.876      ;
; -6.444 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[2]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.088     ; 4.503      ;
; -6.428 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[1]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.717     ; 4.858      ;
; -6.427 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[7] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[24]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.095     ; 4.479      ;
; -6.420 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[7]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[24]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.095     ; 4.472      ;
; -6.411 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[6]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[31]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.722     ; 4.836      ;
; -6.410 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[1]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.091     ; 4.466      ;
; -6.404 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[27] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.717     ; 4.834      ;
; -6.397 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[14] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.734     ; 4.810      ;
; -6.397 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[38] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.722     ; 4.822      ;
; -6.396 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[6] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[24]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -2.095     ; 4.448      ;
; -6.385 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[40] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.735     ; 4.797      ;
; -6.376 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[43] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.736     ; 4.787      ;
+--------+--------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                       ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                         ; To Node                                      ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 0.668 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.173     ; 10.793     ;
; 0.746 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.173     ; 10.715     ;
; 0.750 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.165     ; 10.719     ;
; 0.777 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.163     ; 10.694     ;
; 0.800 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.173     ; 10.661     ;
; 0.801 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.165     ; 10.668     ;
; 0.821 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.161     ; 10.652     ;
; 0.834 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[9]                             ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.154     ; 10.646     ;
; 0.850 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[11]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.154     ; 10.630     ;
; 0.878 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.173     ; 10.583     ;
; 0.882 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.165     ; 10.587     ;
; 0.899 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.161     ; 10.574     ;
; 0.903 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.153     ; 10.578     ;
; 0.909 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.163     ; 10.562     ;
; 0.912 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.154     ; 10.568     ;
; 0.915 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.163     ; 10.556     ;
; 0.925 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.165     ; 10.544     ;
; 0.930 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.151     ; 10.553     ;
; 0.933 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.165     ; 10.536     ;
; 0.935 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.165     ; 10.534     ;
; 0.954 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.153     ; 10.527     ;
; 0.966 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[9]                             ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.154     ; 10.514     ;
; 0.982 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[11]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.154     ; 10.498     ;
; 0.987 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[9]                             ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.142     ; 10.505     ;
; 0.992 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[12]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.154     ; 10.488     ;
; 0.998 ; sdram_reset_n_reg                                                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.159     ; 10.477     ;
; 1.003 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.165     ; 10.466     ;
; 1.003 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[11]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.142     ; 10.489     ;
; 1.007 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.157     ; 10.470     ;
; 1.012 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.173     ; 10.449     ;
; 1.032 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[13]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.154     ; 10.448     ;
; 1.034 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.155     ; 10.445     ;
; 1.043 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.173     ; 10.418     ;
; 1.044 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.154     ; 10.436     ;
; 1.047 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.163     ; 10.424     ;
; 1.058 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.157     ; 10.419     ;
; 1.065 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.142     ; 10.427     ;
; 1.067 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.165     ; 10.402     ;
; 1.068 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.151     ; 10.415     ;
; 1.072 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.164     ; 10.398     ;
; 1.088 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.153     ; 10.393     ;
; 1.091 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[9]                             ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.146     ; 10.397     ;
; 1.105 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[10]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.154     ; 10.375     ;
; 1.107 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[11]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.146     ; 10.381     ;
; 1.124 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[12]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.154     ; 10.356     ;
; 1.130 ; sdram_reset_n_reg                                                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.159     ; 10.345     ;
; 1.144 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.173     ; 10.317     ;
; 1.145 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[12]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.142     ; 10.347     ;
; 1.151 ; sdram_reset_n_reg                                                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.147     ; 10.336     ;
; 1.164 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[13]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.154     ; 10.316     ;
; 1.165 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.161     ; 10.308     ;
; 1.169 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[13]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.168     ; 10.297     ;
; 1.169 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.146     ; 10.319     ;
; 1.172 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.155     ; 10.307     ;
; 1.175 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.173     ; 10.286     ;
; 1.185 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[13]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.142     ; 10.307     ;
; 1.192 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.157     ; 10.285     ;
; 1.196 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.161     ; 10.277     ;
; 1.200 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[11]                                                                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.165     ; 10.269     ;
; 1.200 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.154     ; 10.280     ;
; 1.207 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.166     ; 10.261     ;
; 1.221 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.168     ; 10.245     ;
; 1.224 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.164     ; 10.246     ;
; 1.225 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.168     ; 10.241     ;
; 1.237 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[10]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.154     ; 10.243     ;
; 1.249 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[12]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.146     ; 10.239     ;
; 1.255 ; sdram_reset_n_reg                                                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.151     ; 10.228     ;
; 1.258 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[10]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.142     ; 10.234     ;
; 1.269 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.165     ; 10.200     ;
; 1.269 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.155     ; 10.210     ;
; 1.273 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.166     ; 10.195     ;
; 1.284 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                                                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.165     ; 10.185     ;
; 1.289 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[13]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.146     ; 10.199     ;
; 1.300 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 10.159     ;
; 1.300 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.165     ; 10.169     ;
; 1.301 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[13]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.168     ; 10.165     ;
; 1.319 ; sdram_reset_n_reg                                                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.160     ; 10.155     ;
; 1.322 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[13]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.156     ; 10.156     ;
; 1.331 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 10.129     ;
; 1.332 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[11]                                                                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.165     ; 10.137     ;
; 1.332 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.154     ; 10.148     ;
; 1.335 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.165     ; 10.134     ;
; 1.348 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[8]                             ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.173     ; 10.113     ;
; 1.353 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.168     ; 10.113     ;
; 1.353 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[11]                                                                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.153     ; 10.128     ;
; 1.353 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.142     ; 10.139     ;
; 1.357 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.168     ; 10.109     ;
; 1.357 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_READ_reg                                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.164     ; 10.113     ;
; 1.358 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.166     ; 10.110     ;
; 1.361 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[13]                                                                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.164     ; 10.109     ;
; 1.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[10]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.146     ; 10.126     ;
; 1.372 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.155     ; 10.107     ;
; 1.374 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.156     ; 10.104     ;
; 1.378 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.156     ; 10.100     ;
; 1.378 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 10.081     ;
; 1.409 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 10.051     ;
; 1.416 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                                                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.165     ; 10.053     ;
; 1.419 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[9]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.169     ; 10.046     ;
; 1.426 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[13]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.160     ; 10.048     ;
; 1.437 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                                                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.153     ; 10.044     ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3]'                                                                                                                                                  ;
+-------+-------------------------+-------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node               ; To Node           ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------+-------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 4.783 ; svideo_yout_dly2[4]     ; cvbs2_out[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.066     ; 3.848      ;
; 4.790 ; svideo_yout_dly2[6]     ; cvbs2_out[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.066     ; 3.841      ;
; 4.838 ; svideo_yout_dly2[3]     ; cvbs2_out[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.066     ; 3.793      ;
; 4.856 ; svideo_yout_dly2[2]     ; cvbs2_out[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.066     ; 3.775      ;
; 4.927 ; svideo_yout_dly2[4]     ; cvbs2_out[2]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.066     ; 3.704      ;
; 4.934 ; svideo_yout_dly2[6]     ; cvbs2_out[2]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.066     ; 3.697      ;
; 4.982 ; svideo_yout_dly2[3]     ; cvbs2_out[2]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.066     ; 3.649      ;
; 4.987 ; svideo_yout_dly2[2]     ; cvbs2_out[2]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.066     ; 3.644      ;
; 5.048 ; svideo_yout_dly2[4]     ; cvbs2_out[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.067     ; 3.582      ;
; 5.053 ; svideo_yout_dly2[5]     ; cvbs2_out[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.066     ; 3.578      ;
; 5.055 ; svideo_yout_dly2[6]     ; cvbs2_out[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.067     ; 3.575      ;
; 5.080 ; svideo_yout_dly2[7]     ; cvbs2_out[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.066     ; 3.551      ;
; 5.103 ; svideo_yout_dly2[3]     ; cvbs2_out[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.067     ; 3.527      ;
; 5.134 ; svideo_yout_dly2[4]     ; cvbs2_out[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.068     ; 3.495      ;
; 5.141 ; svideo_yout_dly2[1]     ; cvbs2_out[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.066     ; 3.490      ;
; 5.141 ; svideo_yout_dly2[6]     ; cvbs2_out[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.068     ; 3.488      ;
; 5.155 ; svideo_yout_dly2[4]     ; cvbs2_out[3]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.067     ; 3.475      ;
; 5.162 ; svideo_yout_dly2[6]     ; cvbs2_out[3]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.067     ; 3.468      ;
; 5.171 ; svideo_yout_dly2[2]     ; cvbs2_out[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.067     ; 3.459      ;
; 5.189 ; svideo_yout_dly2[3]     ; cvbs2_out[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.068     ; 3.440      ;
; 5.197 ; svideo_yout_dly2[5]     ; cvbs2_out[2]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.066     ; 3.434      ;
; 5.210 ; svideo_yout_dly2[3]     ; cvbs2_out[3]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.067     ; 3.420      ;
; 5.211 ; svideo_yout_dly2[7]     ; cvbs2_out[2]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.066     ; 3.420      ;
; 5.230 ; svideo_yout_dly2[2]     ; cvbs2_out[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.068     ; 3.399      ;
; 5.240 ; svideo_yout_dly2[2]     ; cvbs2_out[3]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.067     ; 3.390      ;
; 5.272 ; svideo_yout_dly2[4]     ; cvbs2_out[0]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.066     ; 3.359      ;
; 5.273 ; svideo_yout_dly2[6]     ; cvbs2_out[0]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.066     ; 3.358      ;
; 5.277 ; svideo_yout_dly2[4]     ; cvbs2_out[1]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.066     ; 3.354      ;
; 5.278 ; svideo_yout_dly2[6]     ; cvbs2_out[1]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.066     ; 3.353      ;
; 5.285 ; svideo_yout_dly2[1]     ; cvbs2_out[2]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.066     ; 3.346      ;
; 5.318 ; svideo_yout_dly2[5]     ; cvbs2_out[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.067     ; 3.312      ;
; 5.324 ; svideo_yout_dly2[2]     ; cvbs2_out[0]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.066     ; 3.307      ;
; 5.329 ; svideo_yout_dly2[2]     ; cvbs2_out[1]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.066     ; 3.302      ;
; 5.346 ; svideo_yout_dly2[3]     ; cvbs2_out[0]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.066     ; 3.285      ;
; 5.351 ; svideo_yout_dly2[3]     ; cvbs2_out[1]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.066     ; 3.280      ;
; 5.384 ; svideo_yout_dly2[7]     ; cvbs2_out[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.067     ; 3.246      ;
; 5.402 ; svideo_yout_dly2[0]     ; cvbs2_out[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.066     ; 3.229      ;
; 5.404 ; svideo_yout_dly2[5]     ; cvbs2_out[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.068     ; 3.225      ;
; 5.406 ; svideo_yout_dly2[1]     ; cvbs2_out[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.067     ; 3.224      ;
; 5.425 ; svideo_yout_dly2[5]     ; cvbs2_out[3]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.067     ; 3.205      ;
; 5.426 ; svideo_yout_dly2[4]     ; cvbs2_out[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.068     ; 3.203      ;
; 5.433 ; svideo_yout_dly2[6]     ; cvbs2_out[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.068     ; 3.196      ;
; 5.454 ; svideo_yout_dly2[7]     ; cvbs2_out[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.068     ; 3.175      ;
; 5.464 ; svideo_yout_dly2[7]     ; cvbs2_out[3]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.067     ; 3.166      ;
; 5.481 ; svideo_yout_dly2[3]     ; cvbs2_out[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.068     ; 3.148      ;
; 5.492 ; svideo_yout_dly2[1]     ; cvbs2_out[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.068     ; 3.137      ;
; 5.513 ; svideo_yout_dly2[1]     ; cvbs2_out[3]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.067     ; 3.117      ;
; 5.533 ; svideo_yout_dly2[0]     ; cvbs2_out[2]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.066     ; 3.098      ;
; 5.536 ; svideo_yout_dly2[2]     ; cvbs2_out[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.068     ; 3.093      ;
; 5.548 ; svideo_yout_dly2[7]     ; cvbs2_out[0]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.066     ; 3.083      ;
; 5.553 ; svideo_yout_dly2[7]     ; cvbs2_out[1]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.066     ; 3.078      ;
; 5.568 ; svideo_yout_dly2[5]     ; cvbs2_out[0]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.066     ; 3.063      ;
; 5.576 ; svideo_yout_dly2[5]     ; cvbs2_out[1]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.066     ; 3.055      ;
; 5.648 ; svideo_yout_dly2[1]     ; cvbs2_out[0]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.066     ; 2.983      ;
; 5.653 ; svideo_yout_dly2[1]     ; cvbs2_out[1]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.066     ; 2.978      ;
; 5.696 ; svideo_yout_dly2[5]     ; cvbs2_out[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.068     ; 2.933      ;
; 5.720 ; svideo_yout_dly2[0]     ; cvbs2_out[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.067     ; 2.910      ;
; 5.760 ; svideo_yout_dly2[7]     ; cvbs2_out[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.068     ; 2.869      ;
; 5.776 ; svideo_yout_dly2[0]     ; cvbs2_out[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.068     ; 2.853      ;
; 5.784 ; svideo_yout_dly2[1]     ; cvbs2_out[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.068     ; 2.845      ;
; 5.786 ; svideo_yout_dly2[0]     ; cvbs2_out[3]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.067     ; 2.844      ;
; 5.870 ; svideo_yout_dly2[0]     ; cvbs2_out[0]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.066     ; 2.761      ;
; 5.875 ; svideo_yout_dly2[0]     ; cvbs2_out[1]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.066     ; 2.756      ;
; 5.982 ; cvbs1_out[4]            ; cvbs2_out[2]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.065     ; 2.650      ;
; 5.992 ; cvbs1_out[9]            ; cvbs2_out[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.065     ; 2.640      ;
; 6.082 ; svideo_yout_dly2[0]     ; cvbs2_out[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.068     ; 2.547      ;
; 6.092 ; cvbs1_out[2]            ; cvbs2_out[0]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.065     ; 2.540      ;
; 6.126 ; cvbs1_out[3]            ; cvbs2_out[1]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.065     ; 2.506      ;
; 6.193 ; cvbs1_out[7]            ; cvbs2_out[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.067     ; 2.437      ;
; 6.280 ; svideo:svideo|chroma[0] ; cvbs1_out[9]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.165     ; 2.364      ;
; 6.300 ; svideo:svideo|chroma[1] ; cvbs1_out[8]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.165     ; 2.344      ;
; 6.329 ; svideo:svideo|chroma[1] ; cvbs1_out[9]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.165     ; 2.315      ;
; 6.356 ; svideo:svideo|chroma[2] ; cvbs1_out[9]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.165     ; 2.288      ;
; 6.380 ; cvbs1_out[5]            ; cvbs2_out[3]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.066     ; 2.251      ;
; 6.396 ; svideo:svideo|chroma[0] ; cvbs1_out[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.165     ; 2.248      ;
; 6.411 ; svideo:svideo|chroma[3] ; cvbs1_out[8]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.165     ; 2.233      ;
; 6.416 ; svideo:svideo|chroma[1] ; cvbs1_out[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.165     ; 2.228      ;
; 6.425 ; svideo:svideo|chroma[0] ; cvbs1_out[8]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.165     ; 2.219      ;
; 6.440 ; svideo:svideo|chroma[3] ; cvbs1_out[9]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.165     ; 2.204      ;
; 6.445 ; svideo:svideo|chroma[1] ; cvbs1_out[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.165     ; 2.199      ;
; 6.462 ; svideo:svideo|luma[3]   ; luma_saturated[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.164     ; 2.183      ;
; 6.472 ; svideo:svideo|chroma[2] ; cvbs1_out[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.165     ; 2.172      ;
; 6.486 ; svideo:svideo|chroma[4] ; cvbs1_out[9]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.165     ; 2.158      ;
; 6.486 ; cvbs1_out[8]            ; cvbs2_out[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.067     ; 2.144      ;
; 6.491 ; svideo:svideo|luma[3]   ; luma_saturated[9] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.164     ; 2.154      ;
; 6.501 ; svideo:svideo|chroma[2] ; cvbs1_out[8]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.165     ; 2.143      ;
; 6.512 ; svideo:svideo|chroma[0] ; cvbs1_out[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.165     ; 2.132      ;
; 6.527 ; svideo:svideo|chroma[3] ; cvbs1_out[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.165     ; 2.117      ;
; 6.532 ; svideo:svideo|chroma[1] ; cvbs1_out[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.165     ; 2.112      ;
; 6.541 ; svideo:svideo|chroma[0] ; cvbs1_out[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.165     ; 2.103      ;
; 6.556 ; svideo:svideo|chroma[3] ; cvbs1_out[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.165     ; 2.088      ;
; 6.561 ; svideo:svideo|chroma[1] ; cvbs1_out[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.165     ; 2.083      ;
; 6.563 ; svideo:svideo|chroma[5] ; cvbs1_out[8]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.165     ; 2.081      ;
; 6.566 ; luma_saturated[2]       ; cvbs1_out[9]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.063     ; 2.180      ;
; 6.578 ; svideo:svideo|luma[3]   ; luma_saturated[6] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.164     ; 2.067      ;
; 6.588 ; svideo:svideo|chroma[2] ; cvbs1_out[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.165     ; 2.056      ;
; 6.592 ; svideo:svideo|chroma[5] ; cvbs1_out[9]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.165     ; 2.052      ;
; 6.602 ; svideo:svideo|chroma[4] ; cvbs1_out[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.165     ; 2.042      ;
; 6.607 ; svideo:svideo|luma[3]   ; luma_saturated[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.164     ; 2.038      ;
; 6.617 ; svideo:svideo|chroma[2] ; cvbs1_out[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.165     ; 2.027      ;
+-------+-------------------------+-------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'mcc_pll3|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                ;
+--------+-----------------------------------------------+---------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                     ; To Node                                           ; Launch Clock                                         ; Latch Clock                                          ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------+---------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+
; 26.607 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[14] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.622      ;
; 26.611 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[14] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.618      ;
; 26.612 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[3]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.617      ;
; 26.616 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[7] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[14] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.613      ;
; 26.616 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[3]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.613      ;
; 26.621 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[7] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[3]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.608      ;
; 26.657 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[6]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.572      ;
; 26.658 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[11] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.571      ;
; 26.659 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[10] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.570      ;
; 26.661 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[6]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.568      ;
; 26.662 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[5]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.567      ;
; 26.662 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[11] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.567      ;
; 26.663 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[10] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.566      ;
; 26.664 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[7]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.565      ;
; 26.664 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[9]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.565      ;
; 26.666 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[7] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[6]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.563      ;
; 26.666 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[5]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.563      ;
; 26.667 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[7] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[11] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.562      ;
; 26.668 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[7] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[10] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.561      ;
; 26.668 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[7]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.561      ;
; 26.668 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[9]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.561      ;
; 26.671 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[7] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[5]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.558      ;
; 26.673 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[7] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[7]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.556      ;
; 26.673 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[7] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[9]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.556      ;
; 26.712 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[0]      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.084     ; 6.526      ;
; 26.712 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[1]      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.084     ; 6.526      ;
; 26.732 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[14] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.497      ;
; 26.737 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[3]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.492      ;
; 26.755 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[0]      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.084     ; 6.483      ;
; 26.755 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[1]      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.084     ; 6.483      ;
; 26.762 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[4]      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.084     ; 6.476      ;
; 26.762 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[6]      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.084     ; 6.476      ;
; 26.775 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[14] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.454      ;
; 26.780 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[3]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.449      ;
; 26.782 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[6]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.447      ;
; 26.783 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[11] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.446      ;
; 26.784 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[10] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.445      ;
; 26.787 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[5]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.442      ;
; 26.789 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[7]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.440      ;
; 26.789 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[9]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.440      ;
; 26.805 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[4]      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.084     ; 6.433      ;
; 26.805 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[6]      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.084     ; 6.433      ;
; 26.825 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[6]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.404      ;
; 26.826 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[11] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.403      ;
; 26.827 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[10] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.402      ;
; 26.830 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[5]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.399      ;
; 26.832 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[7]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.397      ;
; 26.832 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[9]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.397      ;
; 26.853 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[2]      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.086     ; 6.383      ;
; 26.853 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[14] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.376      ;
; 26.858 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[3]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.371      ;
; 26.896 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[0]      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.084     ; 6.342      ;
; 26.896 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[1]      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.084     ; 6.342      ;
; 26.903 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[6]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.326      ;
; 26.904 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[11] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.325      ;
; 26.905 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[10] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.324      ;
; 26.908 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[5]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.321      ;
; 26.909 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[2]      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.086     ; 6.327      ;
; 26.910 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[7]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.319      ;
; 26.910 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[9]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.319      ;
; 26.928 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[4]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.301      ;
; 26.931 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[8]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.298      ;
; 26.932 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[4]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.297      ;
; 26.935 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[8]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.294      ;
; 26.937 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[7] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[4]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.292      ;
; 26.939 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[1]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.290      ;
; 26.940 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[2]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.289      ;
; 26.940 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[7] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[8]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.289      ;
; 26.943 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[1]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.286      ;
; 26.944 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[2]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.285      ;
; 26.946 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[4]      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.084     ; 6.292      ;
; 26.946 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[6]      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.084     ; 6.292      ;
; 26.948 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[7] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[1]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.281      ;
; 26.949 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[7] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[2]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.280      ;
; 26.973 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[6] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[14] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.256      ;
; 26.978 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[6] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[3]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.251      ;
; 27.005 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[0]      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.084     ; 6.233      ;
; 27.005 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[1]      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.084     ; 6.233      ;
; 27.023 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[6] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[6]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.206      ;
; 27.024 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[6] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[11] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.205      ;
; 27.025 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[6] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[10] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.204      ;
; 27.028 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[6] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[5]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.201      ;
; 27.028 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[5] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[0]      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.148     ; 6.146      ;
; 27.028 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[5] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[1]      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.148     ; 6.146      ;
; 27.030 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[6] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[7]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.199      ;
; 27.030 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[6] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[9]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.199      ;
; 27.050 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[13] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.084     ; 6.188      ;
; 27.052 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[2]      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.086     ; 6.184      ;
; 27.053 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[4]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.176      ;
; 27.054 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[13] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.084     ; 6.184      ;
; 27.055 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[4]      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.084     ; 6.183      ;
; 27.055 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[6]      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.084     ; 6.183      ;
; 27.056 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[8]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.173      ;
; 27.059 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[7] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[13] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.084     ; 6.179      ;
; 27.064 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[1]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.165      ;
; 27.065 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[2]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.164      ;
; 27.096 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[4]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.133      ;
; 27.099 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[8]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.130      ;
; 27.107 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[1]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.122      ;
; 27.108 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[2]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.093     ; 6.121      ;
+--------+-----------------------------------------------+---------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'altera_reserved_tck'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                        ; To Node                                                                                                                                                                                                               ; Launch Clock        ; Latch Clock         ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; 45.838 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.250      ; 4.411      ;
; 46.045 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                                                   ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.249      ; 4.203      ;
; 46.215 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.250      ; 4.034      ;
; 46.330 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]                                              ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.251      ; 3.920      ;
; 46.379 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.250      ; 3.870      ;
; 46.605 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.260      ; 3.654      ;
; 46.622 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2]                                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.252      ; 3.629      ;
; 46.628 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.252      ; 3.623      ;
; 46.656 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.259      ; 3.602      ;
; 46.705 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]                                              ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.258      ; 3.552      ;
; 46.777 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.259      ; 3.481      ;
; 47.069 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.259      ; 3.189      ;
; 47.134 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.252      ; 3.117      ;
; 47.282 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.251      ; 2.968      ;
; 47.302 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                                                   ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.253      ; 2.950      ;
; 47.415 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.251      ; 2.835      ;
; 47.545 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.251      ; 2.705      ;
; 47.561 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.258      ; 2.696      ;
; 47.975 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.258      ; 2.282      ;
; 48.071 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.249      ; 2.177      ;
; 48.299 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[0]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.259      ; 1.959      ;
; 48.301 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg                                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.258      ; 1.956      ;
; 48.602 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[0]                                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.257      ; 1.654      ;
; 48.745 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[0]                                                                                                                               ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.257      ; 1.511      ;
; 95.603 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.311     ; 4.085      ;
; 95.626 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.310     ; 4.063      ;
; 95.633 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.311     ; 4.055      ;
; 95.651 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.311     ; 4.037      ;
; 95.710 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.311     ; 3.978      ;
; 95.736 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[5]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.311     ; 3.952      ;
; 95.739 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[5]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.311     ; 3.949      ;
; 95.758 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[6]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.311     ; 3.930      ;
; 95.777 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.311     ; 3.911      ;
; 95.793 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.311     ; 3.895      ;
; 95.810 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.057     ; 4.132      ;
; 95.810 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[6]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.057     ; 4.132      ;
; 95.810 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[5]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.057     ; 4.132      ;
; 95.810 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.057     ; 4.132      ;
; 95.810 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.057     ; 4.132      ;
; 95.810 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.057     ; 4.132      ;
; 95.810 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.057     ; 4.132      ;
; 95.860 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[6]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.311     ; 3.828      ;
; 95.902 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.315     ; 3.782      ;
; 95.910 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.055     ; 4.034      ;
; 95.910 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.055     ; 4.034      ;
; 95.910 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.055     ; 4.034      ;
; 95.910 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.055     ; 4.034      ;
; 95.910 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.055     ; 4.034      ;
; 95.945 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.315     ; 3.739      ;
; 95.995 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 3.941      ;
; 95.995 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 3.941      ;
; 95.995 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 3.941      ;
; 95.995 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 3.941      ;
; 95.995 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 3.941      ;
; 96.032 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.056     ; 3.911      ;
; 96.040 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.315     ; 3.644      ;
; 96.056 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3]                                                                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.071     ; 3.872      ;
; 96.056 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2]                                                                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.071     ; 3.872      ;
; 96.056 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1]                                                                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.071     ; 3.872      ;
; 96.056 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0]                                                                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.071     ; 3.872      ;
; 96.063 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.066     ; 3.870      ;
; 96.063 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0                                                                                                                                        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.066     ; 3.870      ;
; 96.065 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.057     ; 3.877      ;
; 96.065 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.057     ; 3.877      ;
; 96.065 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.057     ; 3.877      ;
; 96.065 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.057     ; 3.877      ;
; 96.065 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.057     ; 3.877      ;
; 96.071 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.065     ; 3.863      ;
; 96.071 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.065     ; 3.863      ;
; 96.071 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.065     ; 3.863      ;
; 96.071 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.065     ; 3.863      ;
; 96.073 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.072     ; 3.854      ;
; 96.073 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.072     ; 3.854      ;
; 96.073 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.072     ; 3.854      ;
; 96.073 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.072     ; 3.854      ;
; 96.073 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.072     ; 3.854      ;
; 96.075 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.315     ; 3.609      ;
; 96.092 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[3]      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.065     ; 3.842      ;
; 96.092 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[2]      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.065     ; 3.842      ;
; 96.092 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[1]      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.065     ; 3.842      ;
; 96.092 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[0]      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.065     ; 3.842      ;
; 96.174 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.055     ; 3.770      ;
; 96.174 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.055     ; 3.770      ;
; 96.174 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.055     ; 3.770      ;
; 96.174 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.055     ; 3.770      ;
; 96.174 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.055     ; 3.770      ;
; 96.186 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.068     ; 3.745      ;
; 96.186 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.068     ; 3.745      ;
; 96.186 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.068     ; 3.745      ;
; 96.186 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.068     ; 3.745      ;
; 96.186 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.068     ; 3.745      ;
; 96.186 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3]                                                                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.071     ; 3.742      ;
; 96.186 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2]                                                                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.071     ; 3.742      ;
; 96.186 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1]                                                                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.071     ; 3.742      ;
; 96.186 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0]                                                                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.071     ; 3.742      ;
; 96.200 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.315     ; 3.484      ;
; 96.220 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4]                                                                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.071     ; 3.708      ;
; 96.238 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[1]                                                                                                                 ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.073     ; 3.688      ;
; 96.238 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[2]                                                                                                                 ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.073     ; 3.688      ;
; 96.238 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[3]                                                                                                                 ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.073     ; 3.688      ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3]'                                                                                                                                                             ;
+-------+---------------------------+---------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                 ; To Node                   ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------+---------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 0.329 ; svideo:svideo|luma[8]     ; svideo:svideo|luma_1[8]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.142      ; 0.660      ;
; 0.329 ; svideo:svideo|luma[9]     ; svideo:svideo|luma_1[9]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.142      ; 0.660      ;
; 0.406 ; svideo_yout_dly1[1]       ; svideo_yout_dly2[1]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 0.639      ;
; 0.407 ; svideo_yout_dly1[4]       ; svideo_yout_dly2[4]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 0.640      ;
; 0.407 ; svideo_yout_dly1[3]       ; svideo_yout_dly2[3]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 0.640      ;
; 0.408 ; svideo:svideo|luma_1[9]   ; svideo:svideo|luma_2[9]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 0.641      ;
; 0.468 ; svideo:svideo|luma[5]     ; svideo:svideo|luma_1[5]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.139      ; 0.796      ;
; 0.481 ; svideo:svideo|luma[7]     ; svideo:svideo|luma_1[7]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.142      ; 0.812      ;
; 0.482 ; svideo:svideo|luma[4]     ; svideo:svideo|luma_1[4]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.142      ; 0.813      ;
; 0.485 ; svideo:svideo|luma[6]     ; svideo:svideo|luma_1[6]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.142      ; 0.816      ;
; 0.489 ; svideo:svideo|luma[9]     ; luma_saturated[9]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.142      ; 0.820      ;
; 0.503 ; svideo:svideo|luma[1]     ; svideo:svideo|luma_1[1]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.142      ; 0.834      ;
; 0.515 ; svideo:svideo|luma[2]     ; luma_saturated[2]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.142      ; 0.846      ;
; 0.519 ; svideo:svideo|luma[6]     ; luma_saturated[6]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.142      ; 0.850      ;
; 0.532 ; svideo:svideo|luma[1]     ; luma_saturated[1]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.142      ; 0.863      ;
; 0.533 ; svideo:svideo|luma[0]     ; luma_saturated[1]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.142      ; 0.864      ;
; 0.557 ; svideo:svideo|luma_1[8]   ; svideo:svideo|luma_2[8]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 0.790      ;
; 0.557 ; svideo_yout_dly1[5]       ; svideo_yout_dly2[5]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 0.790      ;
; 0.559 ; svideo:svideo|luma_1[3]   ; svideo:svideo|luma_2[3]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 0.792      ;
; 0.559 ; svideo_yout_dly1[6]       ; svideo_yout_dly2[6]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 0.792      ;
; 0.559 ; svideo_yout_dly1[2]       ; svideo_yout_dly2[2]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 0.792      ;
; 0.560 ; svideo:svideo|luma_acc[7] ; svideo_yout_dly1[5]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 0.793      ;
; 0.561 ; svideo_yout_dly1[7]       ; svideo_yout_dly2[7]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 0.794      ;
; 0.561 ; svideo_yout_dly1[0]       ; svideo_yout_dly2[0]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 0.794      ;
; 0.563 ; svideo:svideo|luma_1[0]   ; svideo:svideo|luma_2[0]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 0.796      ;
; 0.565 ; svideo:svideo|luma_1[4]   ; svideo:svideo|luma_2[4]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 0.798      ;
; 0.567 ; luma_saturated[9]         ; cvbs1_out[9]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.061      ; 0.799      ;
; 0.580 ; svideo:svideo|luma_1[7]   ; svideo:svideo|luma_2[7]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 0.813      ;
; 0.581 ; svideo:svideo|luma_1[6]   ; svideo:svideo|luma_2[6]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 0.814      ;
; 0.582 ; svideo:svideo|luma_acc[8] ; svideo_yout_dly1[6]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 0.815      ;
; 0.586 ; svideo:svideo|luma_1[2]   ; svideo:svideo|luma_2[2]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 0.819      ;
; 0.592 ; svideo:svideo|luma_2[6]   ; svideo:svideo|luma_acc[6] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 0.825      ;
; 0.593 ; svideo:svideo|luma_2[2]   ; svideo:svideo|luma_acc[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 0.826      ;
; 0.594 ; svideo:svideo|luma_acc[1] ; svideo:svideo|luma_acc[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 0.827      ;
; 0.594 ; svideo:svideo|luma_2[7]   ; svideo:svideo|luma_acc[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 0.827      ;
; 0.595 ; svideo:svideo|luma[0]     ; luma_saturated[0]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.142      ; 0.926      ;
; 0.595 ; svideo:svideo|luma_2[4]   ; svideo:svideo|luma_acc[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 0.828      ;
; 0.609 ; svideo:svideo|luma_acc[0] ; svideo:svideo|luma_acc[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 0.842      ;
; 0.614 ; svideo:svideo|luma_2[0]   ; svideo:svideo|luma_acc[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 0.847      ;
; 0.650 ; svideo:svideo|luma[0]     ; svideo:svideo|luma_1[0]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.142      ; 0.981      ;
; 0.663 ; svideo:svideo|luma[4]     ; luma_saturated[4]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.142      ; 0.994      ;
; 0.664 ; svideo:svideo|luma[5]     ; luma_saturated[5]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.139      ; 0.992      ;
; 0.674 ; svideo:svideo|luma[7]     ; luma_saturated[7]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.142      ; 1.005      ;
; 0.677 ; svideo:svideo|luma[8]     ; luma_saturated[8]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.142      ; 1.008      ;
; 0.681 ; svideo:svideo|luma[2]     ; svideo:svideo|luma_1[2]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.142      ; 1.012      ;
; 0.721 ; svideo:svideo|luma_acc[9] ; svideo_yout_dly1[7]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 0.954      ;
; 0.724 ; svideo:svideo|luma_acc[4] ; svideo_yout_dly1[2]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 0.957      ;
; 0.739 ; svideo:svideo|luma_acc[2] ; svideo_yout_dly1[0]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 0.972      ;
; 0.747 ; luma_saturated[6]         ; cvbs1_out[6]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.061      ; 0.979      ;
; 0.747 ; luma_saturated[4]         ; cvbs1_out[4]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.061      ; 0.979      ;
; 0.754 ; svideo:svideo|luma_2[3]   ; svideo:svideo|luma_acc[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 0.987      ;
; 0.755 ; luma_saturated[3]         ; cvbs1_out[3]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.061      ; 0.987      ;
; 0.756 ; svideo:svideo|luma_2[1]   ; svideo:svideo|luma_acc[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 0.989      ;
; 0.757 ; svideo:svideo|luma_acc[6] ; svideo_yout_dly1[4]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 0.990      ;
; 0.758 ; svideo:svideo|luma_1[1]   ; svideo:svideo|luma_2[1]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 0.991      ;
; 0.758 ; svideo:svideo|luma_acc[3] ; svideo_yout_dly1[1]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 0.991      ;
; 0.758 ; svideo:svideo|luma_acc[5] ; svideo_yout_dly1[3]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 0.991      ;
; 0.762 ; svideo:svideo|luma_1[5]   ; svideo:svideo|luma_2[5]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 0.995      ;
; 0.784 ; luma_saturated[7]         ; cvbs1_out[7]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.061      ; 1.016      ;
; 0.785 ; luma_saturated[5]         ; cvbs1_out[5]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.061      ; 1.017      ;
; 0.787 ; luma_saturated[8]         ; cvbs1_out[8]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.061      ; 1.019      ;
; 0.799 ; svideo:svideo|luma_2[8]   ; svideo:svideo|luma_acc[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 1.032      ;
; 0.800 ; svideo:svideo|luma_2[5]   ; svideo:svideo|luma_acc[5] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 1.033      ;
; 0.801 ; svideo:svideo|luma[0]     ; luma_saturated[2]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.142      ; 1.132      ;
; 0.802 ; svideo:svideo|luma[2]     ; luma_saturated[3]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.142      ; 1.133      ;
; 0.802 ; svideo:svideo|luma_2[9]   ; svideo:svideo|luma_acc[9] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 1.035      ;
; 0.804 ; svideo:svideo|luma[6]     ; luma_saturated[7]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.142      ; 1.135      ;
; 0.805 ; svideo:svideo|luma[1]     ; luma_saturated[2]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.142      ; 1.136      ;
; 0.812 ; svideo:svideo|luma[0]     ; luma_saturated[3]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.142      ; 1.143      ;
; 0.816 ; svideo:svideo|luma[1]     ; luma_saturated[3]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.142      ; 1.147      ;
; 0.879 ; svideo:svideo|luma_acc[1] ; svideo:svideo|luma_acc[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 1.112      ;
; 0.880 ; svideo:svideo|luma_2[6]   ; svideo:svideo|luma_acc[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 1.113      ;
; 0.881 ; svideo:svideo|luma_2[2]   ; svideo:svideo|luma_acc[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 1.114      ;
; 0.881 ; svideo:svideo|luma_2[7]   ; svideo:svideo|luma_acc[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 1.114      ;
; 0.882 ; svideo:svideo|luma_2[0]   ; svideo:svideo|luma_acc[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 1.115      ;
; 0.882 ; svideo:svideo|luma_acc[0] ; svideo:svideo|luma_acc[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 1.115      ;
; 0.883 ; svideo:svideo|luma_2[4]   ; svideo:svideo|luma_acc[5] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 1.116      ;
; 0.891 ; svideo:svideo|luma_2[6]   ; svideo:svideo|luma_acc[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 1.124      ;
; 0.892 ; svideo:svideo|luma_2[2]   ; svideo:svideo|luma_acc[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 1.125      ;
; 0.893 ; svideo:svideo|luma_2[0]   ; svideo:svideo|luma_acc[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 1.126      ;
; 0.893 ; svideo:svideo|luma_acc[0] ; svideo:svideo|luma_acc[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 1.126      ;
; 0.894 ; svideo:svideo|luma_2[4]   ; svideo:svideo|luma_acc[6] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.062      ; 1.127      ;
; 0.901 ; svideo:svideo|luma[2]     ; luma_saturated[4]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.142      ; 1.232      ;
; 0.903 ; svideo:svideo|luma[6]     ; luma_saturated[8]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.142      ; 1.234      ;
; 0.911 ; svideo:svideo|luma[0]     ; luma_saturated[4]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.142      ; 1.242      ;
; 0.912 ; svideo:svideo|luma[2]     ; luma_saturated[5]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.142      ; 1.243      ;
; 0.914 ; svideo:svideo|luma[6]     ; luma_saturated[9]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.142      ; 1.245      ;
; 0.915 ; svideo:svideo|luma[1]     ; luma_saturated[4]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.142      ; 1.246      ;
; 0.916 ; svideo:svideo|chroma[6]   ; cvbs1_out[6]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.138      ; 1.243      ;
; 0.922 ; svideo:svideo|luma[0]     ; luma_saturated[5]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.142      ; 1.253      ;
; 0.925 ; luma_saturated[2]         ; cvbs1_out[2]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.061      ; 1.157      ;
; 0.926 ; svideo:svideo|luma[1]     ; luma_saturated[5]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.142      ; 1.257      ;
; 0.932 ; svideo:svideo|luma[3]     ; svideo:svideo|luma_1[3]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.139      ; 1.260      ;
; 0.938 ; svideo:svideo|luma[5]     ; luma_saturated[6]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.139      ; 1.266      ;
; 0.946 ; svideo:svideo|chroma[5]   ; cvbs1_out[5]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.138      ; 1.273      ;
; 0.947 ; svideo:svideo|chroma[2]   ; cvbs1_out[2]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.138      ; 1.274      ;
; 0.949 ; svideo:svideo|chroma[4]   ; cvbs1_out[4]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.138      ; 1.276      ;
; 0.949 ; svideo:svideo|luma[4]     ; luma_saturated[5]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.142      ; 1.280      ;
; 0.956 ; svideo:svideo|luma[3]     ; luma_saturated[3]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.139      ; 1.284      ;
; 0.956 ; svideo:svideo|luma[7]     ; luma_saturated[8]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.142      ; 1.287      ;
+-------+---------------------------+---------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                     ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                             ; To Node                                                                                                                                               ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 0.350 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[2]                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[2]                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.076      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_add_sp2                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_add_sp2                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[22]                                                                                                      ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[22]                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_load2                                                                                  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_load2                                                                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|idim_r                                                                                          ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|idim_r                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[30]                                                                                                      ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[30]                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[14]                                                                                                      ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[14]                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[18]                                                                                                      ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[18]                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[21]                                                                                                      ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[21]                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[20]                                                                                                      ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[20]                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[19]                                                                                                      ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[19]                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[25]                                                                                                      ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[25]                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[5]                                                                                                       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[5]                                                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[6]                                                                                                       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[6]                                                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[2]                                                                                                       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[2]                                                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|skctl_reg[1]                                                                                     ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|skctl_reg[1]                                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[1]                                                                                     ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[1]                                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[7]                                                                                     ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[7]                                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[4]                                                                                     ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[4]                                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[5]                                                                                     ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[5]                                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[6]                                                                                     ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[6]                                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0]                            ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0]                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[1]                                                                                     ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[1]                                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[0]                                                                                     ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[0]                                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[2]                                                                                     ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[2]                                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[3]                                                                                     ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[3]                                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[6]                                                                                     ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[6]                                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[4]                                                                                     ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[4]                                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[5]                                                                                     ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[5]                                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[7]                                                                                     ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[7]                                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer2|delay_line:underflow0_delay|shift_reg[0]                            ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer2|delay_line:underflow0_delay|shift_reg[0]                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[2]                                                                                     ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[2]                                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[3]                                                                                     ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[3]                                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[6]                                                                                     ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[6]                                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[4]                                                                                     ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[4]                                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[5]                                                                                     ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[5]                                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[7]                                                                                     ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[7]                                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer3|delay_line:underflow0_delay|shift_reg[0]                            ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer3|delay_line:underflow0_delay|shift_reg[0]                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[8]                                                                                                       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[8]                                                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[26]                                                                                                      ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[26]                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[23]                                                                                                      ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[23]                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[6]                                                                                          ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[6]                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[17]                                                                                                      ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[17]                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[28]                                                                                                      ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[28]                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[10]                                                                                                      ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[10]                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[5]                                                                                          ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[5]                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[12]                                                                                                      ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[12]                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[9]                                                                                                       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[9]                                                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[15]                                                                                                      ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[15]                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[27]                                                                                                      ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[27]                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[24]                                                                                                      ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[24]                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_reg                                                                                                   ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_reg                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_config_regs:config_regs|spi_speed_reg[7]                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|spi_speed_reg[7]                                                                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|assert_data                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|assert_data                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|irqst_reg[1]                                                                                     ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|irqst_reg[1]                                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pot_reset_reg                                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pot_reset_reg                                                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[16]                                                                                                      ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[16]                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[7]                                                                                          ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[7]                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serial_ip_framing_reg                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serial_ip_framing_reg                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[31]                                                                                                      ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[31]                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_fetch                                                                                  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_fetch                                                                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|irqst_reg[5]                                                                                     ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|irqst_reg[5]                                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serial_ip_overrun_reg                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serial_ip_overrun_reg                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|irqst_reg[2]                                                                                     ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|irqst_reg[2]                                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[1]                                                                                          ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[1]                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|irqst_reg[0]                                                                                     ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|irqst_reg[0]                                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[0]                                                                                          ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[0]                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_loadb2                                                                                 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_loadb2                                                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[0]                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[0]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[1]                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[1]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[2]                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[2]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[3]                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[3]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[5]                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[5]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[6]                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[6]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[7]                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[7]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[4]                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[4]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[3]                                                                                                     ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[3]                                                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Vreg                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Vreg                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Dreg                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Dreg                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wsync_reg                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wsync_reg                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|nmi_pending_reg                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|nmi_pending_reg                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|first_line_of_instruction_reg                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|first_line_of_instruction_reg                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vscrol_last_enabled_reg                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vscrol_last_enabled_reg                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[6]                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[6]                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|use_status_as_ram_address           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|use_status_as_ram_address           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|serin_bitcount_reg[1]                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|serin_bitcount_reg[1]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|serin_bitcount_reg[3]                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|serin_bitcount_reg[3]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|serin_bitcount_reg[2]                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|serin_bitcount_reg[2]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|irqst_reg[5]                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|irqst_reg[5]                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cycleEnd                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cycleEnd                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[7]                                                                                                     ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[7]                                                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[7]                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[7]                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|irqst_reg[6]                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|irqst_reg[6]                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_keyboard_scanner:pokey_keyboard_scanner1|shift_pressed_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_keyboard_scanner:pokey_keyboard_scanner1|shift_pressed_reg ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|cfg_enable                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|cfg_enable                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|oss_bank[0]                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|oss_bank[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|oss_bank[1]                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|oss_bank[1]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[11]                                                                                                    ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[11]                                                                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[11]                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[11]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[5]                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[5]                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.063      ; 0.597      ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'altera_reserved_tck'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                             ; To Node                                                                                                                                                                                                               ; Launch Clock        ; Latch Clock         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; 0.362 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6]                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                             ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                                                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.064      ; 0.597      ;
; 0.363 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1]                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1]                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2]                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2]                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0]                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1]                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11]                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11]                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1]                                                                                                                                         ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1]                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2]                                                                                                                                         ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2]                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2]                                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]                                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2]                                        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]                                        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4]                                                                                                                                             ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4]                                                                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0]                                                                                                                                         ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0]                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg                                                         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg                                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg                                                         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg                                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                                                        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[1] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg                                                                                                                                          ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg                                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13]                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13]                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.597      ;
; 0.374 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0]                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0]                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.608      ;
; 0.374 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[0] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.608      ;
; 0.374 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[0] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.608      ;
; 0.394 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0]                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1]                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.628      ;
; 0.395 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3]                                                                                                                                          ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2]                                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.629      ;
; 0.396 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0]                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2]                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.630      ;
; 0.404 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][2]                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.638      ;
; 0.405 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[3]                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[2]                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.639      ;
; 0.405 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[2]                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[1]                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.639      ;
; 0.405 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2]                                                                                                                                         ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                                                                                                                                                 ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.639      ;
; 0.405 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3]                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.639      ;
; 0.405 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3]                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.639      ;
; 0.405 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1]                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.639      ;
; 0.405 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2]                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.639      ;
; 0.405 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0]                                                                                                                           ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[0]                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.639      ;
; 0.406 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[1]                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[0]                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.640      ;
; 0.406 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0]                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.640      ;
; 0.406 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0]                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.640      ;
; 0.406 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[1]      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[0]      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.640      ;
; 0.407 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][1]                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.641      ;
; 0.407 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]                                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.641      ;
; 0.408 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][4]                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.642      ;
; 0.408 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13]                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[14]                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.642      ;
; 0.409 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.643      ;
; 0.409 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.643      ;
; 0.410 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[3]                                                                                                                           ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[2]                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.644      ;
; 0.410 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0]                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.644      ;
; 0.410 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]                                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.644      ;
; 0.410 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.644      ;
; 0.411 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[12]                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13]                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.645      ;
; 0.412 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8]                                                                                                                                          ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7]                                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.646      ;
; 0.412 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2]                                                                                                                                          ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1]                                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.646      ;
; 0.413 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7]                                                                                                                                          ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6]                                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.647      ;
; 0.413 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[3]                                                                                                                           ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[3]                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.647      ;
; 0.413 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[2]                                                                                                                           ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1]                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.647      ;
; 0.413 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1]                                                                                                                           ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[1]                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.647      ;
; 0.413 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1]                                                                                                                           ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0]                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.647      ;
; 0.413 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[10]                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[12]                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.647      ;
; 0.413 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[14]                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11]                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.647      ;
; 0.414 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[2]                                                                                                                           ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[2]                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.648      ;
; 0.415 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6]                                                                                                                                          ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5]                                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.649      ;
; 0.418 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7]                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.064      ; 0.653      ;
; 0.420 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[4]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[4]                                                                                                                 ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.654      ;
; 0.423 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]                                        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.657      ;
; 0.425 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                                                                                           ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3]                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.659      ;
; 0.425 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                                                                                           ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1]                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.659      ;
; 0.425 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2]                                                                                                                                           ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2]                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.659      ;
; 0.425 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.659      ;
; 0.425 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.659      ;
; 0.425 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.659      ;
; 0.426 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                                                                                           ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0]                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.660      ;
; 0.427 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[6]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[5]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.661      ;
; 0.430 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[15]                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[2]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 0.664      ;
; 0.471 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_datain_reg0                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.321      ; 0.993      ;
; 0.475 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.311      ; 0.987      ;
; 0.475 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[6]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.311      ; 0.987      ;
; 0.476 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.311      ; 0.988      ;
; 0.477 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_datain_reg0                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.321      ; 0.999      ;
; 0.480 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.311      ; 0.992      ;
; 0.484 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.311      ; 0.996      ;
; 0.485 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_datain_reg0                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.317      ; 1.003      ;
; 0.491 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.311      ; 1.003      ;
; 0.493 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_datain_reg0                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.321      ; 1.015      ;
; 0.493 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_datain_reg0                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.321      ; 1.015      ;
; 0.496 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.311      ; 1.008      ;
; 0.496 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_datain_reg0                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.321      ; 1.018      ;
; 0.498 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.311      ; 1.010      ;
; 0.504 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.311      ; 1.016      ;
; 0.505 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_datain_reg0                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.317      ; 1.023      ;
; 0.506 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.311      ; 1.018      ;
; 0.508 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.311      ; 1.020      ;
; 0.509 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_datain_reg0                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.316      ; 1.026      ;
; 0.510 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.311      ; 1.022      ;
; 0.511 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.311      ; 1.023      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'mcc_pll3|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                        ;
+-------+---------------------------------------------------------------------+---------------------------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                           ; To Node                                                             ; Launch Clock                                         ; Latch Clock                                          ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------+---------------------------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[0]                     ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[0]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[6]                     ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[6]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[7]                     ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[7]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[3]                     ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[3]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[2]                     ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[2]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[1]                     ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[1]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[4]                     ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[4]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[5]                     ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[5]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|dp_previous                        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|dp_previous                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|dm_previous                        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|dm_previous                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; cntr_reset[1]                                                       ; cntr_reset[1]                                                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; cntr_reset[2]                                                       ; cntr_reset[2]                                                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; cntr_reset[5]                                                       ; cntr_reset[5]                                                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; cntr_reset[6]                                                       ; cntr_reset[6]                                                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; reset_usbdrv                                                        ; reset_usbdrv                                                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state2                  ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state2                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state4                  ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state4                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|stuffin1[1]                        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|stuffin1[1]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|stuffin1[2]                        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|stuffin1[2]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[2]                         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[2]                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state1                  ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state1                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state3                  ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state3                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[0]                         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[0]                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[1]                         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[1]                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[3]                         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[3]                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[6]                       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[6]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[2]                       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[2]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2]                       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[3]                       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[3]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3]                       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4]                       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5]                       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[0]                       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[0]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[1]                       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[1]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1]                       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[7]                       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[7]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|val                                ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|val                                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|read_byte_valid                    ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|read_byte_valid                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[0]                         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[0]                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state1                  ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state1                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state2                  ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state2                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[2]                         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[2]                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[3]                         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[3]                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[0]                       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[0]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[4]                       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[4]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[2]                       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[2]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[2]                       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[2]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[3]                       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[3]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[3]                       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[3]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[5]                       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[5]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[1]                       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[1]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[1]                       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[1]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[7]                       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[7]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[6]                       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[6]                       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|stuffin1[2]                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|stuffin1[2]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|stuffin1[1]                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|stuffin1[1]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[1]                         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[1]                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|read_byte_valid                    ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|read_byte_valid                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[4]                     ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[4]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[5]                     ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[5]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[0]                     ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[0]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[1]                     ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[1]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[3]                     ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[3]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[7]                     ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[7]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait2                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait2                   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.setaddress_sendpkt3_end ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.setaddress_sendpkt3_end ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.send_ack_end            ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.send_ack_end            ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.start_get_data          ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.start_get_data          ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte2         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte2         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte3         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte3         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte4         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte4         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte5         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte5         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte6         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte6         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte7         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte7         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte8         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte8         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte9         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte9         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte10        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte10        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|read_byte_valid_c                  ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|read_byte_valid_c                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte11        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte11        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.getreport_sendpkt1_end  ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.getreport_sendpkt1_end  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait30                  ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait30                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.setaddress_sendpkt1_end ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.setaddress_sendpkt1_end ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_valid                         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_valid                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte2         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte2         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte3         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte3         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte4         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte4         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte5         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte5         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte6         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte6         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte7         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte7         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte8         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte8         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.364 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_send_com.Idle                  ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_send_com.Idle                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.597      ;
; 0.364 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_send_com.reset_start           ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_send_com.reset_start           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.597      ;
; 0.364 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|send_frame                         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|send_frame                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.597      ;
; 0.364 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state3                  ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state3                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.597      ;
; 0.364 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state4                  ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state4                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.597      ;
; 0.364 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|val                                ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|val                                ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.597      ;
; 0.364 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.Idle                  ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.Idle                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.597      ;
; 0.364 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.reset_start           ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.reset_start           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.597      ;
; 0.364 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|send_frame                         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|send_frame                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.597      ;
; 0.364 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[2]                     ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[2]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.597      ;
+-------+---------------------------------------------------------------------+---------------------------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                               ;
+-------+-----------------------------------------------------------------------------------------------------------------+-------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                       ; To Node                                               ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------+-------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 0.364 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                                      ; sdram_ctrl:sdram_controller|r_init_tmr[10]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.597      ;
; 0.364 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[0]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.597      ;
; 0.364 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.597      ;
; 0.364 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.597      ;
; 0.364 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                           ; sdram_ctrl:sdram_controller|sdram_rdy                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.597      ;
; 0.364 ; sdram_ctrl:sdram_controller|r_wr_act                                                                            ; sdram_ctrl:sdram_controller|r_wr_act                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.597      ;
; 0.364 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                                                                        ; sdram_ctrl:sdram_controller|r_bst_stp[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.597      ;
; 0.364 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_rd_bctr[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.597      ;
; 0.364 ; sdram_ctrl:sdram_controller|r_rd_act                                                                            ; sdram_ctrl:sdram_controller|r_rd_act                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.597      ;
; 0.364 ; sdram_ctrl:sdram_controller|r_refr_act                                                                          ; sdram_ctrl:sdram_controller|r_refr_act                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.597      ;
; 0.375 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[0]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.608      ;
; 0.526 ; sdram_ctrl:sdram_controller|r_rd_act                                                                            ; sdram_ctrl:sdram_controller|ap1_rd_bst_act            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.759      ;
; 0.554 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_rd_act                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.787      ;
; 0.557 ; sdram_ctrl:sdram_controller|r_psel_dly[0]                                                                       ; sdram_ctrl:sdram_controller|ap1_rd_bst_act            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.790      ;
; 0.568 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[23] ; ram_di_reg[7]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.142      ; 0.900      ;
; 0.568 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[25] ; ram_di_reg[9]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.141      ; 0.899      ;
; 0.570 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[21] ; ram_di_reg[5]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.142      ; 0.902      ;
; 0.572 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[18] ; ram_di_reg[2]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.142      ; 0.904      ;
; 0.573 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[16] ; ram_di_reg[0]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.141      ; 0.904      ;
; 0.584 ; seq_reg[6]                                                                                                      ; seq_reg[7]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.817      ;
; 0.589 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.822      ;
; 0.589 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.822      ;
; 0.590 ; seq_reg[5]                                                                                                      ; seq_reg[6]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.823      ;
; 0.591 ; seq_reg[4]                                                                                                      ; seq_reg[5]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.824      ;
; 0.592 ; seq_reg[9]                                                                                                      ; seq_reg[10]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.825      ;
; 0.593 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.826      ;
; 0.593 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.826      ;
; 0.594 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.827      ;
; 0.594 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.827      ;
; 0.595 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.828      ;
; 0.595 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.828      ;
; 0.595 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                                                                        ; sdram_ctrl:sdram_controller|r_rd_bctr[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.828      ;
; 0.596 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_wr_act                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.829      ;
; 0.597 ; seq_reg[11]                                                                                                     ; sdram_ctrl:sdram_controller|r_init_fsm[0]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.830      ;
; 0.597 ; seq_reg[11]                                                                                                     ; sdram_ctrl:sdram_controller|r_init_fsm[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.830      ;
; 0.602 ; seq_reg[1]                                                                                                      ; seq_reg[2]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.835      ;
; 0.609 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.842      ;
; 0.610 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.843      ;
; 0.638 ; sdram_ctrl:sdram_controller|r_rd_act                                                                            ; sdram_ctrl:sdram_controller|r_rd_bctr[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.871      ;
; 0.677 ; sdram_ctrl:sdram_controller|r_refr_act                                                                          ; sdram_ctrl:sdram_controller|r_rd_reg                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.910      ;
; 0.684 ; sdram_ctrl:sdram_controller|r_refr_act                                                                          ; sdram_ctrl:sdram_controller|r_wr_reg                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.917      ;
; 0.687 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.920      ;
; 0.697 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[0]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.930      ;
; 0.711 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[24] ; ram_di_reg[8]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.141      ; 1.042      ;
; 0.729 ; seq_reg[10]                                                                                                     ; seq_reg[11]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.961      ;
; 0.738 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[1]  ; ram_di_reg[1]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.141      ; 1.069      ;
; 0.775 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[26] ; ram_di_reg[10]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.142      ; 1.107      ;
; 0.777 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[27] ; ram_di_reg[11]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.141      ; 1.108      ;
; 0.777 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[28] ; ram_di_reg[12]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.141      ; 1.108      ;
; 0.777 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[30] ; ram_di_reg[14]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.142      ; 1.109      ;
; 0.779 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[19] ; ram_di_reg[3]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.142      ; 1.111      ;
; 0.782 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[22] ; ram_di_reg[6]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.142      ; 1.114      ;
; 0.782 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[29] ; ram_di_reg[13]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.142      ; 1.114      ;
; 0.786 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[20] ; ram_di_reg[4]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.141      ; 1.117      ;
; 0.788 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[31] ; ram_di_reg[15]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.142      ; 1.120      ;
; 0.789 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[17] ; ram_di_reg[1]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.141      ; 1.120      ;
; 0.790 ; seq_reg[7]                                                                                                      ; seq_reg[8]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.024      ;
; 0.824 ; sdram_ctrl:sdram_controller|r_wr_act                                                                            ; sdram_ctrl:sdram_controller|r_wr_bctr[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.057      ;
; 0.827 ; seq_reg[11]                                                                                                     ; sdram_ctrl:sdram_controller|r_init_fsm[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.060      ;
; 0.827 ; seq_reg[10]                                                                                                     ; sdram_ctrl:sdram_controller|sdram_rdy                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 1.059      ;
; 0.836 ; sdram_ctrl:sdram_controller|r_rd_reg                                                                            ; sdram_ctrl:sdram_controller|r_rd_act                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.070      ;
; 0.871 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[2]  ; ram_di_reg[2]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.144      ; 1.205      ;
; 0.872 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[15] ; ram_di_reg[15]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.142      ; 1.204      ;
; 0.874 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[13] ; ram_di_reg[13]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.142      ; 1.206      ;
; 0.875 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.108      ;
; 0.875 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.108      ;
; 0.875 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[12] ; ram_di_reg[12]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.141      ; 1.206      ;
; 0.876 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[8]  ; ram_di_reg[8]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.141      ; 1.207      ;
; 0.878 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.111      ;
; 0.880 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.113      ;
; 0.880 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.113      ;
; 0.882 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.115      ;
; 0.882 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.115      ;
; 0.883 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.116      ;
; 0.883 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.116      ;
; 0.889 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.122      ;
; 0.893 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.126      ;
; 0.893 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.126      ;
; 0.894 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.127      ;
; 0.894 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.127      ;
; 0.932 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                                       ; sdram_ctrl:sdram_controller|sdram_rdy                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.165      ;
; 0.953 ; seq_reg[8]                                                                                                      ; seq_reg[9]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.186      ;
; 0.968 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg          ; sdram_ctrl:sdram_controller|r_refr_req                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.147      ; 1.305      ;
; 0.974 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.207      ;
; 0.976 ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1                                                           ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.209      ;
; 0.979 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.212      ;
; 0.979 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.212      ;
; 0.985 ; sdram_ctrl:sdram_controller|r_refr_req                                                                          ; sdram_ctrl:sdram_controller|r_rd_reg                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.219      ;
; 0.985 ; sdram_ctrl:sdram_controller|r_refr_req                                                                          ; sdram_ctrl:sdram_controller|r_wr_reg                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.219      ;
; 0.985 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.218      ;
; 0.988 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.221      ;
; 0.990 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.223      ;
; 0.990 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.223      ;
; 0.992 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.225      ;
; 0.993 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.226      ;
; 0.993 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.226      ;
; 0.999 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.232      ;
; 0.999 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.232      ;
; 1.003 ; seq_reg[2]                                                                                                      ; seq_reg[3]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.236      ;
; 1.003 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.236      ;
+-------+-----------------------------------------------------------------------------------------------------------------+-------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                          ;
+-------+---------------------------------------+------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                                                                                        ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 7.260 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[13]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 4.340      ;
; 7.260 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_8BIT_WRITE_ENABLE_reg                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 4.340      ;
; 7.260 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_READ_reg                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 4.340      ;
; 7.272 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[8]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 4.317      ;
; 7.272 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[10]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 4.317      ;
; 7.272 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[9]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 4.317      ;
; 7.272 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[1]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.158     ; 4.317      ;
; 7.300 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[14]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.146     ; 4.301      ;
; 7.300 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[15]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.146     ; 4.301      ;
; 7.314 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[11]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.140     ; 4.293      ;
; 7.318 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.139     ; 4.290      ;
; 7.632 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[22]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; 0.230      ; 4.345      ;
; 7.632 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[23]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; 0.230      ; 4.345      ;
; 7.632 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[18]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; 0.230      ; 4.345      ;
; 7.632 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[19]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; 0.230      ; 4.345      ;
; 7.632 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[20]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; 0.230      ; 4.345      ;
; 7.632 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[21]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; 0.230      ; 4.345      ;
; 7.636 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[3]                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.140     ; 3.971      ;
; 7.636 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[18]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.141     ; 3.970      ;
; 7.636 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[17]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.141     ; 3.970      ;
; 7.636 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[21]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.141     ; 3.970      ;
; 7.636 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[22]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.141     ; 3.970      ;
; 7.636 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[20]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.141     ; 3.970      ;
; 7.636 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[19]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.141     ; 3.970      ;
; 7.636 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[3]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.151     ; 3.960      ;
; 7.636 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[0]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.151     ; 3.960      ;
; 7.636 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[2]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.151     ; 3.960      ;
; 7.636 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[1]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.151     ; 3.960      ;
; 7.636 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[16]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.151     ; 3.960      ;
; 7.636 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[17]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.151     ; 3.960      ;
; 7.637 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[14]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.153     ; 3.957      ;
; 7.637 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[8]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.153     ; 3.957      ;
; 7.637 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[11]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.153     ; 3.957      ;
; 7.637 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[10]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.153     ; 3.957      ;
; 7.637 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[9]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.153     ; 3.957      ;
; 7.637 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[13]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.153     ; 3.957      ;
; 7.637 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[12]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.153     ; 3.957      ;
; 7.638 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[6]                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 3.952      ;
; 7.638 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[11]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 3.962      ;
; 7.638 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[15]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.153     ; 3.956      ;
; 7.638 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[6]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.152     ; 3.957      ;
; 7.638 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 3.962      ;
; 7.638 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[5]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.153     ; 3.956      ;
; 7.638 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 3.962      ;
; 7.638 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|memory_ready_reg                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 3.962      ;
; 7.640 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[1]                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; 0.192      ; 4.299      ;
; 7.640 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[0]                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; 0.192      ; 4.299      ;
; 7.647 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[8]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.148     ; 3.952      ;
; 7.647 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[12]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.144     ; 3.956      ;
; 7.647 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[9]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.148     ; 3.952      ;
; 7.647 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[9]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.148     ; 3.952      ;
; 7.649 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_clock_last_reg                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.151     ; 3.947      ;
; 7.649 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_holding_full_reg                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.152     ; 3.946      ;
; 7.649 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_shift_reg[9]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.152     ; 3.946      ;
; 7.649 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_shift_reg[8]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.152     ; 3.946      ;
; 7.649 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_shift_reg[7]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.152     ; 3.946      ;
; 7.649 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_shift_reg[6]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.152     ; 3.946      ;
; 7.649 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_shift_reg[5]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.152     ; 3.946      ;
; 7.649 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_shift_reg[4]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.152     ; 3.946      ;
; 7.649 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_shift_reg[3]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.152     ; 3.946      ;
; 7.649 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_shift_reg[2]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.152     ; 3.946      ;
; 7.649 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_shift_reg[1]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.152     ; 3.946      ;
; 7.649 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_active_reg                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.152     ; 3.946      ;
; 7.649 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serial_out_reg                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.152     ; 3.946      ;
; 7.649 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|twotone_reg                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.152     ; 3.946      ;
; 7.649 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|sio_out_reg                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.152     ; 3.946      ;
; 7.649 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|irqst_reg[4]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.151     ; 3.947      ;
; 7.650 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[18]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.139     ; 3.958      ;
; 7.650 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[0]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.151     ; 3.946      ;
; 7.650 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[2]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.151     ; 3.946      ;
; 7.650 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[3]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.151     ; 3.946      ;
; 7.650 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[1]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.151     ; 3.946      ;
; 7.650 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[0]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.151     ; 3.946      ;
; 7.650 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.141     ; 3.956      ;
; 7.650 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.141     ; 3.956      ;
; 7.650 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[2]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.141     ; 3.956      ;
; 7.650 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.141     ; 3.956      ;
; 7.650 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[3]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.141     ; 3.956      ;
; 7.650 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.141     ; 3.956      ;
; 7.650 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[6]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.141     ; 3.956      ;
; 7.650 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[4]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.141     ; 3.956      ;
; 7.650 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.141     ; 3.956      ;
; 7.650 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[5]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.141     ; 3.956      ;
; 7.650 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[5] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.141     ; 3.956      ;
; 7.650 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[6] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.141     ; 3.956      ;
; 7.650 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[7]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.141     ; 3.956      ;
; 7.650 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.141     ; 3.956      ;
; 7.650 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_holding_reg[2]                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.151     ; 3.946      ;
; 7.650 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_holding_reg[3]                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.151     ; 3.946      ;
; 7.650 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_holding_reg[4]                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.151     ; 3.946      ;
; 7.650 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_holding_reg[5]                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.151     ; 3.946      ;
; 7.650 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_holding_reg[6]                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.151     ; 3.946      ;
; 7.650 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_holding_reg[7]                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.151     ; 3.946      ;
; 7.650 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_holding_reg[1]                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.151     ; 3.946      ;
; 7.650 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_holding_reg[0]                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.151     ; 3.946      ;
; 7.650 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[26]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.139     ; 3.958      ;
; 7.650 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[10]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.139     ; 3.958      ;
; 7.650 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|ss_n[0]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 3.955      ;
; 7.650 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|state                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 3.955      ;
; 7.650 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|irqst_reg[3]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.151     ; 3.946      ;
+-------+---------------------------------------+------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                      ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                                   ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 8.197 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[7]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.240     ; 3.192      ;
; 8.259 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.167     ; 3.208      ;
; 8.259 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[11]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.167     ; 3.208      ;
; 8.261 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[4]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.166     ; 3.207      ;
; 8.261 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[5]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.166     ; 3.207      ;
; 8.261 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[6]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.168     ; 3.205      ;
; 8.261 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[7]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.168     ; 3.205      ;
; 8.261 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[8]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.168     ; 3.205      ;
; 8.271 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[8]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.295     ; 3.061      ;
; 8.271 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[9]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.302     ; 3.054      ;
; 8.273 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[14]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.287     ; 3.067      ;
; 8.273 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[15]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.287     ; 3.067      ;
; 8.273 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[13]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.287     ; 3.067      ;
; 8.275 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[10]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.298     ; 3.054      ;
; 8.275 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[12]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.298     ; 3.054      ;
; 8.275 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[11]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.298     ; 3.054      ;
; 8.281 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.158     ; 3.195      ;
; 8.281 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.158     ; 3.195      ;
; 8.281 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[0]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.158     ; 3.195      ;
; 8.281 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[1]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.158     ; 3.195      ;
; 8.281 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.158     ; 3.195      ;
; 8.283 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[2]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.154     ; 3.197      ;
; 8.283 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[3]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.154     ; 3.197      ;
; 8.284 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[7]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.155     ; 3.195      ;
; 8.287 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[8]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.188     ; 3.161      ;
; 8.287 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[9]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.195     ; 3.154      ;
; 8.288 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[4]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.296     ; 3.043      ;
; 8.289 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[13]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.180     ; 3.167      ;
; 8.289 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[14]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.180     ; 3.167      ;
; 8.289 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[15]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.180     ; 3.167      ;
; 8.290 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[5]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.289     ; 3.048      ;
; 8.291 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[1]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.284     ; 3.052      ;
; 8.291 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[6]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.287     ; 3.049      ;
; 8.291 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[0]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.284     ; 3.052      ;
; 8.291 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[2]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.284     ; 3.052      ;
; 8.291 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[10]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.191     ; 3.154      ;
; 8.291 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[11]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.191     ; 3.154      ;
; 8.291 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[12]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.191     ; 3.154      ;
; 8.294 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[3]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.287     ; 3.046      ;
; 8.304 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[4]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 3.143      ;
; 8.306 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[5]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 3.148      ;
; 8.307 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[0]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.177     ; 3.152      ;
; 8.307 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[1]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.177     ; 3.152      ;
; 8.307 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[2]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.177     ; 3.152      ;
; 8.307 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[6]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.180     ; 3.149      ;
; 8.310 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[3]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.180     ; 3.146      ;
; 8.387 ; sdram_reset_ctrl_n_reg ; ram_di_reg[11]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.166     ; 3.193      ;
; 8.390 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.167     ; 3.189      ;
; 8.403 ; sdram_reset_ctrl_n_reg ; ram_do_reg[19]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.156     ; 3.187      ;
; 8.403 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.156     ; 3.187      ;
; 8.403 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.156     ; 3.187      ;
; 8.403 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.156     ; 3.187      ;
; 8.403 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.156     ; 3.187      ;
; 8.403 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.156     ; 3.187      ;
; 8.403 ; sdram_reset_ctrl_n_reg ; ram_do_reg[20]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.156     ; 3.187      ;
; 8.467 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.166     ; 3.001      ;
; 8.489 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.155     ; 2.990      ;
; 8.489 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.155     ; 2.990      ;
; 8.490 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.155     ; 2.989      ;
; 8.490 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.155     ; 2.989      ;
; 8.490 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.155     ; 2.989      ;
; 8.739 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.157     ; 2.850      ;
; 8.739 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.157     ; 2.850      ;
; 8.739 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.157     ; 2.850      ;
; 8.739 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.157     ; 2.850      ;
; 8.739 ; sdram_reset_ctrl_n_reg ; seq_reg[5]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.157     ; 2.850      ;
; 8.739 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.157     ; 2.850      ;
; 8.739 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.157     ; 2.850      ;
; 8.739 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.157     ; 2.850      ;
; 8.739 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.157     ; 2.850      ;
; 8.739 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.157     ; 2.850      ;
; 8.739 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.157     ; 2.850      ;
; 8.739 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.157     ; 2.850      ;
; 8.739 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.164     ; 2.843      ;
; 8.739 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.164     ; 2.843      ;
; 8.739 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.157     ; 2.850      ;
; 8.739 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.164     ; 2.843      ;
; 8.739 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.164     ; 2.843      ;
; 8.739 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.164     ; 2.843      ;
; 8.739 ; sdram_reset_ctrl_n_reg ; ram_do_reg[5]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.164     ; 2.843      ;
; 8.739 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.164     ; 2.843      ;
; 8.739 ; sdram_reset_ctrl_n_reg ; ram_do_reg[8]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.164     ; 2.843      ;
; 8.739 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.157     ; 2.850      ;
; 8.739 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.164     ; 2.843      ;
; 8.739 ; sdram_reset_ctrl_n_reg ; ram_do_reg[9]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.164     ; 2.843      ;
; 8.739 ; sdram_reset_ctrl_n_reg ; ram_do_reg[25]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.164     ; 2.843      ;
; 8.739 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.164     ; 2.843      ;
; 8.739 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.164     ; 2.843      ;
; 8.739 ; sdram_reset_ctrl_n_reg ; ram_do_reg[13]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.164     ; 2.843      ;
; 8.739 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.164     ; 2.843      ;
; 8.739 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.158     ; 2.849      ;
; 8.739 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.165     ; 2.842      ;
; 8.739 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.165     ; 2.842      ;
; 8.739 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.158     ; 2.849      ;
; 8.739 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.165     ; 2.842      ;
; 8.739 ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.165     ; 2.842      ;
; 8.739 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.155     ; 2.852      ;
; 8.739 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[1]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.165     ; 2.842      ;
; 8.739 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.149     ; 2.858      ;
; 8.740 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.156     ; 2.850      ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: 'altera_reserved_tck'                                                                                                                                                                                                                                                                                                                            ;
+--------+--------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                        ; To Node                                                                                                                                                                        ; Launch Clock        ; Latch Clock         ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; 48.098 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.249      ; 2.150      ;
; 97.660 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.072     ; 2.267      ;
; 97.660 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.072     ; 2.267      ;
; 97.660 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.072     ; 2.267      ;
; 97.660 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.072     ; 2.267      ;
; 97.692 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.072     ; 2.235      ;
; 97.692 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.072     ; 2.235      ;
; 97.692 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.072     ; 2.235      ;
; 97.692 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.072     ; 2.235      ;
; 97.916 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.064     ; 2.019      ;
; 97.916 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.064     ; 2.019      ;
; 97.916 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.064     ; 2.019      ;
; 97.916 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.064     ; 2.019      ;
; 97.947 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.064     ; 1.988      ;
; 97.947 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.064     ; 1.988      ;
; 97.947 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.064     ; 1.988      ;
; 97.947 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.064     ; 1.988      ;
; 98.056 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg                  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.058     ; 1.885      ;
; 98.074 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                 ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.058     ; 1.867      ;
; 98.232 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2]                                                                                                  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 1.704      ;
; 98.240 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.057     ; 1.702      ;
; 98.240 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.057     ; 1.702      ;
; 98.240 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.057     ; 1.702      ;
; 98.240 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.057     ; 1.702      ;
; 98.240 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.057     ; 1.702      ;
; 98.240 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.057     ; 1.702      ;
; 98.240 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.057     ; 1.702      ;
; 98.240 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.057     ; 1.702      ;
; 98.240 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][4]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.057     ; 1.702      ;
; 98.240 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.057     ; 1.702      ;
; 98.241 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.057     ; 1.701      ;
; 98.241 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.057     ; 1.701      ;
; 98.241 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                 ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.057     ; 1.701      ;
; 98.241 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0                                                                                                 ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.057     ; 1.701      ;
; 98.246 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.055     ; 1.698      ;
; 98.246 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.055     ; 1.698      ;
; 98.246 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][2]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.055     ; 1.698      ;
; 98.246 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.055     ; 1.698      ;
; 98.246 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][1]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.055     ; 1.698      ;
; 98.246 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.055     ; 1.698      ;
; 98.246 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.055     ; 1.698      ;
; 98.246 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.055     ; 1.698      ;
; 98.246 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][4]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.055     ; 1.698      ;
; 98.246 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.055     ; 1.698      ;
; 98.248 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                 ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.055     ; 1.696      ;
; 98.267 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.064     ; 1.668      ;
; 98.267 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.064     ; 1.668      ;
; 98.267 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.064     ; 1.668      ;
; 98.320 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg                  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.064     ; 1.615      ;
; 98.347 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.064     ; 1.588      ;
; 98.347 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.064     ; 1.588      ;
; 98.347 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.064     ; 1.588      ;
; 98.353 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1]                                                                                                  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.064     ; 1.582      ;
; 98.353 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.064     ; 1.582      ;
; 98.353 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.064     ; 1.582      ;
; 98.353 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.064     ; 1.582      ;
; 98.353 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.064     ; 1.582      ;
; 98.353 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0]                                                                                                  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.064     ; 1.582      ;
; 98.353 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.064     ; 1.582      ;
; 98.361 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.065     ; 1.573      ;
; 98.361 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.065     ; 1.573      ;
; 98.361 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.065     ; 1.573      ;
; 98.361 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.065     ; 1.573      ;
; 98.361 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.065     ; 1.573      ;
; 98.361 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[6]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.065     ; 1.573      ;
; 98.361 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.065     ; 1.573      ;
; 98.361 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.065     ; 1.573      ;
; 98.361 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.065     ; 1.573      ;
; 98.380 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.065     ; 1.554      ;
; 98.380 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.065     ; 1.554      ;
; 98.380 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.065     ; 1.554      ;
; 98.380 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.065     ; 1.554      ;
; 98.380 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.065     ; 1.554      ;
; 98.380 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[6]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.065     ; 1.554      ;
; 98.380 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.065     ; 1.554      ;
; 98.380 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.065     ; 1.554      ;
; 98.380 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.065     ; 1.554      ;
; 98.450 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 1.486      ;
; 98.450 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 1.486      ;
; 98.450 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 1.486      ;
; 98.450 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 1.486      ;
; 98.450 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 1.486      ;
; 98.450 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 1.486      ;
; 98.450 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 1.486      ;
; 98.450 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 1.486      ;
; 98.450 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 1.486      ;
; 98.450 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 1.486      ;
; 98.450 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_dr_scan_reg                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 1.486      ;
; 98.450 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.063     ; 1.486      ;
+--------+--------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: 'mcc_pll3|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                              ;
+--------+--------------+-----------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node    ; To Node                                             ; Launch Clock                                         ; Latch Clock                                          ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------+-----------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+
; 63.499 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|dp1_last~_emulated ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.068     ; 3.088      ;
; 63.499 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|dm1_last~_emulated ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.068     ; 3.088      ;
; 63.863 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[2]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.070     ; 2.722      ;
; 63.863 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[0]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.070     ; 2.722      ;
; 63.863 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[1]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.070     ; 2.722      ;
; 63.863 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[3]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.070     ; 2.722      ;
; 63.863 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|synch              ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.070     ; 2.722      ;
; 63.863 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[6]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.070     ; 2.722      ;
; 63.863 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[6]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.070     ; 2.722      ;
; 63.863 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[2]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.070     ; 2.722      ;
; 63.863 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.070     ; 2.722      ;
; 63.863 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[3]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.070     ; 2.722      ;
; 63.863 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.070     ; 2.722      ;
; 63.863 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[4]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.070     ; 2.722      ;
; 63.863 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.070     ; 2.722      ;
; 63.863 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[5]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.070     ; 2.722      ;
; 63.863 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.070     ; 2.722      ;
; 63.863 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[0]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.070     ; 2.722      ;
; 63.863 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[0]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.070     ; 2.722      ;
; 63.863 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[1]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.070     ; 2.722      ;
; 63.863 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.070     ; 2.722      ;
; 63.863 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[7]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.070     ; 2.722      ;
; 63.863 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[7]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.070     ; 2.722      ;
; 63.863 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|read_byte_valid    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.070     ; 2.722      ;
; 63.866 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state2  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.067     ; 2.722      ;
; 63.866 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state4  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.067     ; 2.722      ;
; 63.866 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|stuffin1[0]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.067     ; 2.722      ;
; 63.866 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|stuffin1[1]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.067     ; 2.722      ;
; 63.866 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|stuffin1[2]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.067     ; 2.722      ;
; 63.866 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state1  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.067     ; 2.722      ;
; 63.866 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state3  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.067     ; 2.722      ;
; 66.092 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[0]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.161      ; 2.724      ;
; 66.092 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[4]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.161      ; 2.724      ;
; 66.092 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[2]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.161      ; 2.724      ;
; 66.092 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[3]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.161      ; 2.724      ;
; 66.092 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[5]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.161      ; 2.724      ;
; 66.092 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[1]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.161      ; 2.724      ;
; 66.092 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[7]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.161      ; 2.724      ;
; 66.092 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[6]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.161      ; 2.724      ;
; 66.093 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state3  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.164      ; 2.726      ;
; 66.093 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dp1_last~_emulated ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.163      ; 2.725      ;
; 66.093 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dm1_last~_emulated ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.163      ; 2.725      ;
; 66.093 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state4  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.164      ; 2.726      ;
; 66.101 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[0]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.176      ; 2.730      ;
; 66.101 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[2]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.176      ; 2.730      ;
; 66.101 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[3]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.176      ; 2.730      ;
; 66.101 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[0]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.175      ; 2.729      ;
; 66.101 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[3]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.175      ; 2.729      ;
; 66.101 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|stuffin1[0]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.175      ; 2.729      ;
; 66.101 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|stuffin1[2]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.175      ; 2.729      ;
; 66.101 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|stuffin1[1]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.175      ; 2.729      ;
; 66.101 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[1]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.176      ; 2.730      ;
; 66.102 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state1  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.176      ; 2.729      ;
; 66.102 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state2  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.176      ; 2.729      ;
; 66.102 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|synch              ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.176      ; 2.729      ;
; 66.102 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[4]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.176      ; 2.729      ;
; 66.102 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[2]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.176      ; 2.729      ;
; 66.102 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[5]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.176      ; 2.729      ;
; 66.102 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[1]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.176      ; 2.729      ;
; 66.102 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[7]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.176      ; 2.729      ;
; 66.102 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[6]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.176      ; 2.729      ;
; 66.102 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|read_byte_valid    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 2.176      ; 2.729      ;
+--------+--------------+-----------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: 'mcc_pll3|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                               ;
+--------+--------------+-----------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node    ; To Node                                             ; Launch Clock                                         ; Latch Clock                                          ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------+-----------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+
; -0.036 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[0]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.424      ; 2.559      ;
; -0.036 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state1  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.424      ; 2.559      ;
; -0.036 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state2  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.424      ; 2.559      ;
; -0.036 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[2]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.424      ; 2.559      ;
; -0.036 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[3]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.424      ; 2.559      ;
; -0.036 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|synch              ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.424      ; 2.559      ;
; -0.036 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[4]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.424      ; 2.559      ;
; -0.036 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[2]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.424      ; 2.559      ;
; -0.036 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[5]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.424      ; 2.559      ;
; -0.036 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[1]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.424      ; 2.559      ;
; -0.036 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[7]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.424      ; 2.559      ;
; -0.036 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[6]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.424      ; 2.559      ;
; -0.036 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[1]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.424      ; 2.559      ;
; -0.036 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|read_byte_valid    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.424      ; 2.559      ;
; -0.035 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[0]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.423      ; 2.559      ;
; -0.035 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[3]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.423      ; 2.559      ;
; -0.035 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|stuffin1[0]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.423      ; 2.559      ;
; -0.035 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|stuffin1[2]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.423      ; 2.559      ;
; -0.035 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|stuffin1[1]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.423      ; 2.559      ;
; -0.026 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dp1_last~_emulated ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.411      ; 2.556      ;
; -0.026 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dm1_last~_emulated ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.411      ; 2.556      ;
; -0.025 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state3  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.411      ; 2.557      ;
; -0.025 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[0]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.409      ; 2.555      ;
; -0.025 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[4]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.409      ; 2.555      ;
; -0.025 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[2]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.409      ; 2.555      ;
; -0.025 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[3]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.409      ; 2.555      ;
; -0.025 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[5]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.409      ; 2.555      ;
; -0.025 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[1]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.409      ; 2.555      ;
; -0.025 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[7]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.409      ; 2.555      ;
; -0.025 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[6]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.409      ; 2.555      ;
; -0.025 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state4  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 2.411      ; 2.557      ;
; 2.323  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state2  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.059      ; 2.553      ;
; 2.323  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state4  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.059      ; 2.553      ;
; 2.323  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|stuffin1[0]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.059      ; 2.553      ;
; 2.323  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|stuffin1[1]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.059      ; 2.553      ;
; 2.323  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|stuffin1[2]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.059      ; 2.553      ;
; 2.323  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state1  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.059      ; 2.553      ;
; 2.323  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state3  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.059      ; 2.553      ;
; 2.324  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[2]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.056      ; 2.551      ;
; 2.324  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[0]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.056      ; 2.551      ;
; 2.324  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[1]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.056      ; 2.551      ;
; 2.324  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[3]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.056      ; 2.551      ;
; 2.324  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|synch              ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.056      ; 2.551      ;
; 2.324  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[6]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.056      ; 2.551      ;
; 2.324  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[6]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.056      ; 2.551      ;
; 2.324  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[2]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.056      ; 2.551      ;
; 2.324  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.056      ; 2.551      ;
; 2.324  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[3]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.056      ; 2.551      ;
; 2.324  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.056      ; 2.551      ;
; 2.324  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[4]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.056      ; 2.551      ;
; 2.324  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.056      ; 2.551      ;
; 2.324  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[5]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.056      ; 2.551      ;
; 2.324  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.056      ; 2.551      ;
; 2.324  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[0]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.056      ; 2.551      ;
; 2.324  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[0]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.056      ; 2.551      ;
; 2.324  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[1]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.056      ; 2.551      ;
; 2.324  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.056      ; 2.551      ;
; 2.324  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[7]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.056      ; 2.551      ;
; 2.324  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[7]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.056      ; 2.551      ;
; 2.324  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|read_byte_valid    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.056      ; 2.551      ;
; 2.657  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|dp1_last~_emulated ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.058      ; 2.886      ;
; 2.657  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|dm1_last~_emulated ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.058      ; 2.886      ;
+--------+--------------+-----------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: 'altera_reserved_tck'                                                                                                                                                                                                                                                                                                                             ;
+--------+--------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                        ; To Node                                                                                                                                                                        ; Launch Clock        ; Latch Clock         ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; 1.150  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 1.384      ;
; 1.150  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 1.384      ;
; 1.150  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 1.384      ;
; 1.150  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 1.384      ;
; 1.150  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 1.384      ;
; 1.150  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 1.384      ;
; 1.150  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 1.384      ;
; 1.150  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 1.384      ;
; 1.150  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 1.384      ;
; 1.150  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 1.384      ;
; 1.150  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_dr_scan_reg                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 1.384      ;
; 1.150  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 1.384      ;
; 1.255  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 1.487      ;
; 1.255  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 1.487      ;
; 1.255  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 1.487      ;
; 1.255  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 1.487      ;
; 1.255  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 1.487      ;
; 1.255  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[6]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 1.487      ;
; 1.255  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 1.487      ;
; 1.255  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 1.487      ;
; 1.255  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 1.487      ;
; 1.268  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1]                                                                                                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 1.501      ;
; 1.268  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 1.501      ;
; 1.268  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 1.501      ;
; 1.268  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 1.501      ;
; 1.268  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 1.501      ;
; 1.268  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0]                                                                                                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 1.501      ;
; 1.268  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 1.501      ;
; 1.272  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 1.504      ;
; 1.272  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 1.504      ;
; 1.272  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 1.504      ;
; 1.272  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 1.504      ;
; 1.272  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 1.504      ;
; 1.272  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[6]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 1.504      ;
; 1.272  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 1.504      ;
; 1.272  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 1.504      ;
; 1.272  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.061      ; 1.504      ;
; 1.287  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 1.520      ;
; 1.287  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 1.520      ;
; 1.287  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 1.520      ;
; 1.301  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 1.534      ;
; 1.331  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2]                                                                                                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.063      ; 1.565      ;
; 1.348  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                 ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.072      ; 1.591      ;
; 1.352  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 1.585      ;
; 1.352  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 1.585      ;
; 1.352  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 1.585      ;
; 1.360  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.070      ; 1.601      ;
; 1.360  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.070      ; 1.601      ;
; 1.360  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                 ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.070      ; 1.601      ;
; 1.360  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0                                                                                                 ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.070      ; 1.601      ;
; 1.361  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.071      ; 1.603      ;
; 1.361  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.071      ; 1.603      ;
; 1.361  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][2]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.071      ; 1.603      ;
; 1.361  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.071      ; 1.603      ;
; 1.361  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][1]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.071      ; 1.603      ;
; 1.361  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.071      ; 1.603      ;
; 1.361  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.071      ; 1.603      ;
; 1.361  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.071      ; 1.603      ;
; 1.361  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][4]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.071      ; 1.603      ;
; 1.361  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.071      ; 1.603      ;
; 1.368  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 1.608      ;
; 1.368  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 1.608      ;
; 1.368  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 1.608      ;
; 1.368  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 1.608      ;
; 1.368  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 1.608      ;
; 1.368  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 1.608      ;
; 1.368  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 1.608      ;
; 1.368  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 1.608      ;
; 1.368  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][4]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 1.608      ;
; 1.368  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.069      ; 1.608      ;
; 1.545  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                 ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.068      ; 1.784      ;
; 1.547  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 1.780      ;
; 1.547  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 1.780      ;
; 1.547  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 1.780      ;
; 1.547  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 1.780      ;
; 1.564  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.068      ; 1.803      ;
; 1.690  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 1.923      ;
; 1.690  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 1.923      ;
; 1.690  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 1.923      ;
; 1.690  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.062      ; 1.923      ;
; 1.886  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.054      ; 2.111      ;
; 1.886  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.054      ; 2.111      ;
; 1.886  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.054      ; 2.111      ;
; 1.886  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.054      ; 2.111      ;
; 1.941  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.054      ; 2.166      ;
; 1.941  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.054      ; 2.166      ;
; 1.941  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.054      ; 2.166      ;
; 1.941  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.054      ; 2.166      ;
; 51.467 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; -50.000      ; 0.383      ; 2.041      ;
+--------+--------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                           ; To Node                                                                                                                                                                                                                ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 1.311 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a55  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 1.824      ;
; 1.311 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a54  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 1.824      ;
; 1.311 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a53  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 1.824      ;
; 1.311 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a52  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 1.824      ;
; 1.311 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a51  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 1.824      ;
; 1.311 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a50  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 1.824      ;
; 1.311 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a49  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 1.824      ;
; 1.311 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a48  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 1.824      ;
; 1.311 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a47  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 1.824      ;
; 1.311 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a46  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 1.824      ;
; 1.311 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a45  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 1.824      ;
; 1.311 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a44  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 1.824      ;
; 1.311 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a43  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 1.824      ;
; 1.311 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a42  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 1.824      ;
; 1.311 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a41  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 1.824      ;
; 1.311 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a40  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 1.824      ;
; 1.311 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a39  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 1.824      ;
; 1.311 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a38  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 1.824      ;
; 1.311 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a37  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 1.824      ;
; 1.311 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a36  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 1.824      ;
; 1.311 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a23  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 1.824      ;
; 1.311 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a22  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 1.824      ;
; 1.311 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a21  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 1.824      ;
; 1.311 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a20  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 1.824      ;
; 1.311 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a19  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 1.824      ;
; 1.311 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a18  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 1.824      ;
; 1.311 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a17  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 1.824      ;
; 1.311 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a16  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 1.824      ;
; 1.311 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a7   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 1.824      ;
; 1.311 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a6   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 1.824      ;
; 1.311 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a5   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 1.824      ;
; 1.311 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a4   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 1.824      ;
; 1.311 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a3   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 1.824      ;
; 1.311 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a2   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 1.824      ;
; 1.311 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a1   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 1.824      ;
; 1.311 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.345      ; 1.824      ;
; 1.317 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a5 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.346      ; 1.831      ;
; 1.317 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a4 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.346      ; 1.831      ;
; 1.317 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a3 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.346      ; 1.831      ;
; 1.317 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a2 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.346      ; 1.831      ;
; 1.317 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.346      ; 1.831      ;
; 1.317 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.346      ; 1.831      ;
; 1.597 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a63  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.109      ;
; 1.597 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a62  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.109      ;
; 1.597 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a61  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.109      ;
; 1.597 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a60  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.109      ;
; 1.597 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a59  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.109      ;
; 1.597 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a58  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.109      ;
; 1.597 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a57  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.109      ;
; 1.597 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a56  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.109      ;
; 1.597 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a35  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.109      ;
; 1.597 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a34  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.109      ;
; 1.597 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a33  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.109      ;
; 1.597 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a32  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.109      ;
; 1.597 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a31  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.109      ;
; 1.597 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a30  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.109      ;
; 1.597 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a29  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.109      ;
; 1.597 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a28  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.109      ;
; 1.597 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a27  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.109      ;
; 1.597 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a26  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.109      ;
; 1.597 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a25  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.109      ;
; 1.597 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a24  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.109      ;
; 1.597 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a15  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.109      ;
; 1.597 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a14  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.109      ;
; 1.597 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a13  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.109      ;
; 1.597 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a12  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.109      ;
; 1.597 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a11  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.109      ;
; 1.597 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a10  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.109      ;
; 1.597 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a9   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.109      ;
; 1.597 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a8   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.109      ;
; 1.687 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a6 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.367      ; 2.222      ;
; 1.687 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a5 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.367      ; 2.222      ;
; 1.687 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a4 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.367      ; 2.222      ;
; 1.687 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a3 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.367      ; 2.222      ;
; 1.687 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a2 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.367      ; 2.222      ;
; 1.687 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.367      ; 2.222      ;
; 1.687 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.367      ; 2.222      ;
; 1.981 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a15   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.493      ;
; 1.981 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a14   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.493      ;
; 1.981 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a13   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.493      ;
; 1.981 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a12   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.493      ;
; 1.981 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a11   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.493      ;
; 1.981 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a10   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.493      ;
; 1.981 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a9    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.493      ;
; 1.981 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a8    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.493      ;
; 1.981 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a7    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.493      ;
; 1.981 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a6    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.493      ;
; 1.981 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a5    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.493      ;
; 1.981 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a4    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.493      ;
; 1.981 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a3    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.493      ;
; 1.981 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a2    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.493      ;
; 1.981 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a1    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.493      ;
; 1.981 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.344      ; 2.493      ;
; 3.005 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[4]                                                                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.578      ; 3.775      ;
; 3.005 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[5]                                                                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.578      ; 3.775      ;
; 3.038 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]                                                                                                                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.562      ; 3.792      ;
; 3.038 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[8]                                                                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.562      ; 3.792      ;
; 3.038 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                                                                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.562      ; 3.792      ;
; 3.418 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[1]                                                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.158      ; 3.768      ;
; 3.418 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[2]                                                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.158      ; 3.768      ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                       ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                                   ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 1.973 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.544      ; 2.707      ;
; 2.360 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.140      ; 2.690      ;
; 2.360 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.140      ; 2.690      ;
; 2.360 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.140      ; 2.690      ;
; 2.360 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.140      ; 2.690      ;
; 2.360 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.140      ; 2.690      ;
; 2.360 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.139      ; 2.689      ;
; 2.360 ; sdram_reset_ctrl_n_reg ; ram_di_reg[6]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.139      ; 2.689      ;
; 2.360 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.139      ; 2.689      ;
; 2.360 ; sdram_reset_ctrl_n_reg ; ram_di_reg[14]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.139      ; 2.689      ;
; 2.361 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.139      ; 2.690      ;
; 2.361 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.139      ; 2.690      ;
; 2.361 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.138      ; 2.689      ;
; 2.361 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.139      ; 2.690      ;
; 2.361 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.140      ; 2.691      ;
; 2.361 ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.139      ; 2.690      ;
; 2.361 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.140      ; 2.691      ;
; 2.361 ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.139      ; 2.690      ;
; 2.361 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.139      ; 2.690      ;
; 2.361 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.140      ; 2.691      ;
; 2.361 ; sdram_reset_ctrl_n_reg ; ram_di_reg[12]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.140      ; 2.691      ;
; 2.361 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.139      ; 2.690      ;
; 2.361 ; sdram_reset_ctrl_n_reg ; ram_di_reg[15]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.139      ; 2.690      ;
; 2.361 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.139      ; 2.690      ;
; 2.362 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 2.698      ;
; 2.362 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 2.698      ;
; 2.362 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 2.698      ;
; 2.362 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.134      ; 2.686      ;
; 2.362 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.134      ; 2.686      ;
; 2.362 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.134      ; 2.686      ;
; 2.362 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.134      ; 2.686      ;
; 2.362 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.134      ; 2.686      ;
; 2.362 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.134      ; 2.686      ;
; 2.362 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.134      ; 2.686      ;
; 2.362 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.134      ; 2.686      ;
; 2.362 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.134      ; 2.686      ;
; 2.362 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.134      ; 2.686      ;
; 2.362 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.134      ; 2.686      ;
; 2.362 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.139      ; 2.691      ;
; 2.362 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.139      ; 2.691      ;
; 2.362 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.139      ; 2.691      ;
; 2.362 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.139      ; 2.691      ;
; 2.362 ; sdram_reset_ctrl_n_reg ; ram_do_reg[14]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.139      ; 2.691      ;
; 2.362 ; sdram_reset_ctrl_n_reg ; ram_do_reg[11]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.139      ; 2.691      ;
; 2.362 ; sdram_reset_ctrl_n_reg ; ram_do_reg[15]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.139      ; 2.691      ;
; 2.362 ; sdram_reset_ctrl_n_reg ; ram_do_reg[12]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.139      ; 2.691      ;
; 2.362 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.145      ; 2.697      ;
; 2.362 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.145      ; 2.697      ;
; 2.362 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.148      ; 2.700      ;
; 2.362 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[0]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.139      ; 2.691      ;
; 2.362 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.154      ; 2.706      ;
; 2.363 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.145      ; 2.698      ;
; 2.363 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.145      ; 2.698      ;
; 2.363 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.145      ; 2.698      ;
; 2.363 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.145      ; 2.698      ;
; 2.363 ; sdram_reset_ctrl_n_reg ; seq_reg[5]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.145      ; 2.698      ;
; 2.363 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.145      ; 2.698      ;
; 2.363 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.145      ; 2.698      ;
; 2.363 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.145      ; 2.698      ;
; 2.363 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.145      ; 2.698      ;
; 2.363 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.145      ; 2.698      ;
; 2.363 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.145      ; 2.698      ;
; 2.363 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.145      ; 2.698      ;
; 2.363 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.138      ; 2.691      ;
; 2.363 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.138      ; 2.691      ;
; 2.363 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.145      ; 2.698      ;
; 2.363 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.138      ; 2.691      ;
; 2.363 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.138      ; 2.691      ;
; 2.363 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.138      ; 2.691      ;
; 2.363 ; sdram_reset_ctrl_n_reg ; ram_do_reg[5]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.138      ; 2.691      ;
; 2.363 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.138      ; 2.691      ;
; 2.363 ; sdram_reset_ctrl_n_reg ; ram_do_reg[8]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.138      ; 2.691      ;
; 2.363 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.145      ; 2.698      ;
; 2.363 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.138      ; 2.691      ;
; 2.363 ; sdram_reset_ctrl_n_reg ; ram_do_reg[9]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.138      ; 2.691      ;
; 2.363 ; sdram_reset_ctrl_n_reg ; ram_do_reg[25]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.138      ; 2.691      ;
; 2.363 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.138      ; 2.691      ;
; 2.363 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.138      ; 2.691      ;
; 2.363 ; sdram_reset_ctrl_n_reg ; ram_do_reg[13]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.138      ; 2.691      ;
; 2.363 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.138      ; 2.691      ;
; 2.364 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.137      ; 2.691      ;
; 2.364 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.137      ; 2.691      ;
; 2.364 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.137      ; 2.691      ;
; 2.364 ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.137      ; 2.691      ;
; 2.364 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[1]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.137      ; 2.691      ;
; 2.573 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.129      ; 2.818      ;
; 2.573 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.129      ; 2.818      ;
; 2.573 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.129      ; 2.818      ;
; 2.574 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.129      ; 2.819      ;
; 2.574 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.129      ; 2.819      ;
; 2.596 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.118      ; 2.830      ;
; 2.663 ; sdram_reset_ctrl_n_reg ; ram_do_reg[19]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 2.999      ;
; 2.663 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 2.999      ;
; 2.663 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 2.999      ;
; 2.663 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 2.999      ;
; 2.663 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 2.999      ;
; 2.663 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 2.999      ;
; 2.663 ; sdram_reset_ctrl_n_reg ; ram_do_reg[20]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 2.999      ;
; 2.677 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.135      ; 3.002      ;
; 2.679 ; sdram_reset_ctrl_n_reg ; ram_di_reg[11]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.136      ; 3.005      ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3]'                                                         ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+---------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                         ; Clock Edge ; Target                    ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+---------------------------+
; 4.129 ; 4.347        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[2]              ;
; 4.129 ; 4.347        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[3]              ;
; 4.129 ; 4.347        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[4]              ;
; 4.129 ; 4.347        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[5]              ;
; 4.129 ; 4.347        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[6]              ;
; 4.129 ; 4.347        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[7]              ;
; 4.129 ; 4.347        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[8]              ;
; 4.129 ; 4.347        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[9]              ;
; 4.129 ; 4.347        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[0]         ;
; 4.129 ; 4.347        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[1]         ;
; 4.129 ; 4.347        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[2]         ;
; 4.129 ; 4.347        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[3]         ;
; 4.129 ; 4.347        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[4]         ;
; 4.129 ; 4.347        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[5]         ;
; 4.129 ; 4.347        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[6]         ;
; 4.129 ; 4.347        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[7]         ;
; 4.129 ; 4.347        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[8]         ;
; 4.129 ; 4.347        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[9]         ;
; 4.129 ; 4.347        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[0]   ;
; 4.129 ; 4.347        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[1]   ;
; 4.129 ; 4.347        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[2]   ;
; 4.129 ; 4.347        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[3]   ;
; 4.129 ; 4.347        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[4]   ;
; 4.129 ; 4.347        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[5]   ;
; 4.129 ; 4.347        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[6]   ;
; 4.129 ; 4.347        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[7]   ;
; 4.129 ; 4.347        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[8]   ;
; 4.129 ; 4.347        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[9]   ;
; 4.129 ; 4.347        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[3]   ;
; 4.129 ; 4.347        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[5]   ;
; 4.129 ; 4.347        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[8]   ;
; 4.129 ; 4.347        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[9]   ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[0]   ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[1]   ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[2]   ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[4]   ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[6]   ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[7]   ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[0] ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[1] ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[2] ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[3] ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[4] ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[5] ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[6] ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[7] ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[8] ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[9] ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly1[0]       ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly1[1]       ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly1[2]       ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly1[3]       ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly1[4]       ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly1[5]       ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly1[6]       ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly1[7]       ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly2[0]       ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly2[1]       ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly2[2]       ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly2[3]       ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly2[4]       ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly2[5]       ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly2[6]       ;
; 4.130 ; 4.348        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly2[7]       ;
; 4.242 ; 4.393        ; 0.151          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[0]              ;
; 4.242 ; 4.393        ; 0.151          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[1]              ;
; 4.242 ; 4.393        ; 0.151          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[2]              ;
; 4.242 ; 4.393        ; 0.151          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[3]              ;
; 4.242 ; 4.393        ; 0.151          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[7]              ;
; 4.243 ; 4.394        ; 0.151          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[4]              ;
; 4.243 ; 4.394        ; 0.151          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[5]              ;
; 4.243 ; 4.394        ; 0.151          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[6]              ;
; 4.260 ; 4.416        ; 0.156          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[3]              ;
; 4.260 ; 4.416        ; 0.156          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[4]              ;
; 4.260 ; 4.416        ; 0.156          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[5]              ;
; 4.260 ; 4.416        ; 0.156          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[6]              ;
; 4.260 ; 4.416        ; 0.156          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[7]              ;
; 4.261 ; 4.417        ; 0.156          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[0]              ;
; 4.261 ; 4.417        ; 0.156          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[1]              ;
; 4.261 ; 4.417        ; 0.156          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs2_out[2]              ;
; 4.274 ; 4.460        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[2]              ;
; 4.274 ; 4.460        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[3]              ;
; 4.274 ; 4.460        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[4]              ;
; 4.274 ; 4.460        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[5]              ;
; 4.274 ; 4.460        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[6]              ;
; 4.274 ; 4.460        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[7]              ;
; 4.274 ; 4.460        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[8]              ;
; 4.274 ; 4.460        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[9]              ;
; 4.274 ; 4.460        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[0]   ;
; 4.274 ; 4.460        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[1]   ;
; 4.274 ; 4.460        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[2]   ;
; 4.274 ; 4.460        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[4]   ;
; 4.274 ; 4.460        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[6]   ;
; 4.274 ; 4.460        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[7]   ;
; 4.274 ; 4.460        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[8]   ;
; 4.274 ; 4.460        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[9]   ;
; 4.274 ; 4.460        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[0]   ;
; 4.274 ; 4.460        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[1]   ;
; 4.274 ; 4.460        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[2]   ;
; 4.274 ; 4.460        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[3]   ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+---------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                         ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                         ; Clock Edge ; Target                                                    ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; 5.583 ; 5.801        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_complete_reg                                ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_req                    ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[0]                                           ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[0]                                             ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[10]                                            ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[12]                                            ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[13]                                            ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[14]                                            ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[15]                                            ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[2]                                             ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[3]                                             ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[4]                                             ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[5]                                             ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[6]                                             ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[7]                                             ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[8]                                             ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[0]                                             ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[10]                                            ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[11]                                            ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[12]                                            ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[13]                                            ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[14]                                            ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[15]                                            ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[17]                                            ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[18]                                            ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[1]                                             ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[21]                                            ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[24]                                            ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[25]                                            ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[26]                                            ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[29]                                            ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[2]                                             ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[3]                                             ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[4]                                             ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[5]                                             ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[6]                                             ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[7]                                             ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[8]                                             ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[9]                                             ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_act                      ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_reg                      ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_act                    ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_reg                      ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[0]                                                ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[1]                                           ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[11]                                            ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[1]                                             ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[9]                                             ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_act                      ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ;
; 5.600 ; 5.818        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[16]                                            ;
; 5.600 ; 5.818        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[19]                                            ;
; 5.600 ; 5.818        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[20]                                            ;
; 5.600 ; 5.818        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[22]                                            ;
; 5.600 ; 5.818        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[23]                                            ;
; 5.600 ; 5.818        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[27]                                            ;
; 5.600 ; 5.818        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[31]                                            ;
; 5.600 ; 5.818        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel[0]                     ;
; 5.600 ; 5.818        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ;
; 5.600 ; 5.818        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_reg                                         ;
; 5.600 ; 5.818        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[10]                                               ;
; 5.600 ; 5.818        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[8]                                                ;
; 5.600 ; 5.818        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[9]                                                ;
; 5.601 ; 5.819        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ;
; 5.601 ; 5.819        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ;
; 5.601 ; 5.819        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ;
; 5.601 ; 5.819        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ;
; 5.601 ; 5.819        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|sdram_rdy                     ;
; 5.601 ; 5.819        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[11]                                               ;
; 5.602 ; 5.820        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[28]                                            ;
; 5.602 ; 5.820        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[30]                                            ;
; 5.602 ; 5.820        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[1]                                                ;
; 5.602 ; 5.820        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[2]                                                ;
; 5.602 ; 5.820        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[3]                                                ;
; 5.602 ; 5.820        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[4]                                                ;
; 5.602 ; 5.820        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[5]                                                ;
; 5.602 ; 5.820        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[6]                                                ;
; 5.602 ; 5.820        ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[7]                                                ;
; 5.667 ; 5.823        ; 0.156          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[13]                  ;
; 5.667 ; 5.823        ; 0.156          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[14]                  ;
; 5.667 ; 5.823        ; 0.156          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[15]                  ;
; 5.669 ; 5.825        ; 0.156          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[8]                   ;
; 5.669 ; 5.825        ; 0.156          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[9]                   ;
; 5.670 ; 5.826        ; 0.156          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[0]                   ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                      ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                         ; Clock Edge ; Target                                                                                                                                ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+
; 17.323 ; 17.541       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[0]                                                                                     ;
; 17.323 ; 17.541       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[1]                                                                                     ;
; 17.324 ; 17.542       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[4]                                                                                     ;
; 17.324 ; 17.542       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[5]                                                                                     ;
; 17.325 ; 17.543       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                               ;
; 17.325 ; 17.543       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[7]                               ;
; 17.325 ; 17.543       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[2]                      ;
; 17.325 ; 17.543       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|doReg[2]                  ;
; 17.325 ; 17.543       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[11]                                                                 ;
; 17.325 ; 17.543       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[12]                                                                 ;
; 17.325 ; 17.543       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[13]                                                                 ;
; 17.325 ; 17.543       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[14]                                                                 ;
; 17.325 ; 17.543       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[15]                                                                 ;
; 17.325 ; 17.543       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[17]                                                                 ;
; 17.325 ; 17.543       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[8]                                                                  ;
; 17.326 ; 17.544       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[16]                                                                 ;
; 17.328 ; 17.546       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[0]                ;
; 17.328 ; 17.546       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[16]               ;
; 17.328 ; 17.546       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[39]               ;
; 17.328 ; 17.546       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[40]               ;
; 17.328 ; 17.546       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[41]               ;
; 17.328 ; 17.546       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[4]                                  ;
; 17.328 ; 17.546       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]                                                                                    ;
; 17.328 ; 17.546       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[18]                                                                                    ;
; 17.328 ; 17.546       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[19]                                                                                    ;
; 17.328 ; 17.546       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[20]                                                                                    ;
; 17.328 ; 17.546       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[21]                                                                                    ;
; 17.328 ; 17.546       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[22]                                                                                    ;
; 17.328 ; 17.546       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[23]                                                                                    ;
; 17.328 ; 17.546       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[8]                                                                                     ;
; 17.328 ; 17.546       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                                                                                     ;
; 17.329 ; 17.547       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[22]               ;
; 17.329 ; 17.547       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[37]               ;
; 17.329 ; 17.547       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[43]               ;
; 17.329 ; 17.547       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|porta_direction_reg[7]                               ;
; 17.329 ; 17.547       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|porta_output_reg[0]                                  ;
; 17.329 ; 17.547       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|porta_output_reg[1]                                  ;
; 17.329 ; 17.547       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|porta_output_reg[2]                                  ;
; 17.329 ; 17.547       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|porta_output_reg[3]                                  ;
; 17.330 ; 17.548       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[7]                ;
; 17.331 ; 17.549       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[27]               ;
; 17.331 ; 17.549       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]               ;
; 17.331 ; 17.549       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[33]               ;
; 17.331 ; 17.549       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[38]               ;
; 17.331 ; 17.549       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[2]                                                                  ;
; 17.331 ; 17.549       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[3]                                                                  ;
; 17.331 ; 17.549       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[4]                                                                  ;
; 17.332 ; 17.550       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                ;
; 17.332 ; 17.550       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[16]                                                                         ;
; 17.332 ; 17.550       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[19]                                                                         ;
; 17.332 ; 17.550       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[31]                                                                         ;
; 17.332 ; 17.550       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|fetched_w_r[25]                                                                 ;
; 17.332 ; 17.550       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|fetched_w_r[27]                                                                 ;
; 17.332 ; 17.550       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|fetched_w_r[28]                                                                 ;
; 17.333 ; 17.551       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[11]               ;
; 17.333 ; 17.551       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[20]               ;
; 17.333 ; 17.551       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[28]               ;
; 17.333 ; 17.551       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[2]                ;
; 17.333 ; 17.551       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[31]               ;
; 17.333 ; 17.551       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[35]               ;
; 17.333 ; 17.551       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[42]               ;
; 17.333 ; 17.551       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]                ;
; 17.334 ; 17.552       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[19]               ;
; 17.334 ; 17.552       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[1]                ;
; 17.334 ; 17.552       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[21]               ;
; 17.334 ; 17.552       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[30]               ;
; 17.334 ; 17.552       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[3]                ;
; 17.335 ; 17.553       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[10]               ;
; 17.335 ; 17.553       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[14]               ;
; 17.335 ; 17.553       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[15]               ;
; 17.335 ; 17.553       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[18]               ;
; 17.335 ; 17.553       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[26]               ;
; 17.335 ; 17.553       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[34]               ;
; 17.339 ; 17.557       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[23]               ;
; 17.339 ; 17.557       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[29]               ;
; 17.339 ; 17.557       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36]               ;
; 17.339 ; 17.557       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[5]                ;
; 17.344 ; 17.562       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[6]                              ;
; 17.344 ; 17.562       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|HRCOLOUR_REG[0]                                    ;
; 17.344 ; 17.562       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|HRCOLOUR_REG[1]                                    ;
; 17.344 ; 17.562       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|HRCOLOUR_REG[2]                                    ;
; 17.344 ; 17.562       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|HRCOLOUR_REG[3]                                    ;
; 17.344 ; 17.562       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_hr_reg[0]                                   ;
; 17.344 ; 17.562       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_hr_reg[1]                                   ;
; 17.344 ; 17.562       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|an_prev2_reg[0]                                    ;
; 17.344 ; 17.562       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|an_prev2_reg[1]                                    ;
; 17.344 ; 17.562       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|an_prev_reg[1]                                     ;
; 17.344 ; 17.562       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_priority:priority_rules|SF2_reg               ;
; 17.344 ; 17.562       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_priority:priority_rules|SF3_reg               ;
; 17.344 ; 17.562       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_priority:priority_rules|SP0_reg               ;
; 17.344 ; 17.562       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_priority:priority_rules|SP1_reg               ;
; 17.344 ; 17.562       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_priority:priority_rules|SP2_reg               ;
; 17.344 ; 17.562       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_priority:priority_rules|SP3_reg               ;
; 17.344 ; 17.562       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:colpf1_delay|shift_reg[0][0]       ;
; 17.344 ; 17.562       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:colpf1_delay|shift_reg[0][2]       ;
; 17.344 ; 17.562       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:colpf1_delay|shift_reg[1][0]       ;
; 17.344 ; 17.562       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:prior_longer_delay|shift_reg[1][0] ;
; 17.344 ; 17.562       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:prior_longer_delay|shift_reg[2][0] ;
; 17.344 ; 17.562       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:prior_longer_delay|shift_reg[3][0] ;
; 17.344 ; 17.562       ; 0.218          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:prior_short_delay|shift_reg[0][1]  ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                   ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                        ; Clock Edge ; Target                                                                                             ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------+
; 17.589 ; 17.589       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.589 ; 17.589       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.589 ; 17.589       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.589 ; 17.589       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3]                      ;
; 17.589 ; 17.589       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 17.596 ; 17.596       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.596 ; 17.596       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.605 ; 17.605       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.637 ; 17.637       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.645 ; 17.645       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.645 ; 17.645       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.652 ; 17.652       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.652 ; 17.652       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.652 ; 17.652       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.652 ; 17.652       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3]                      ;
; 17.652 ; 17.652       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'mcc_pll3|altpll_component|auto_generated|pll1|clk[0]'                                                                                             ;
+--------+--------------+----------------+------------------+------------------------------------------------------+------------+--------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                ; Clock Edge ; Target                                                       ;
+--------+--------------+----------------+------------------+------------------------------------------------------+------------+--------------------------------------------------------------+
; 32.979 ; 33.197       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dminus_buf1                 ;
; 32.994 ; 33.212       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[0]              ;
; 32.994 ; 33.212       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[1]              ;
; 32.994 ; 33.212       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[3]              ;
; 32.994 ; 33.212       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[4]              ;
; 32.994 ; 33.212       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[5]              ;
; 32.994 ; 33.212       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[7]              ;
; 32.994 ; 33.212       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dm_previous                 ;
; 32.994 ; 33.212       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dp_previous                 ;
; 32.994 ; 33.212       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_byte_tosend[0]           ;
; 32.994 ; 33.212       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_byte_tosend[1]           ;
; 32.994 ; 33.212       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_byte_tosend[2]           ;
; 32.994 ; 33.212       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_byte_tosend[3]           ;
; 32.994 ; 33.212       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_byte_tosend[4]           ;
; 32.994 ; 33.212       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_byte_tosend[5]           ;
; 32.994 ; 33.212       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_byte_tosend[6]           ;
; 32.994 ; 33.212       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_byte_tosend[7]           ;
; 32.994 ; 33.212       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.send_bit5      ;
; 32.994 ; 33.212       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.send_bit6      ;
; 32.994 ; 33.212       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.send_bit7      ;
; 32.995 ; 33.213       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[2]              ;
; 32.995 ; 33.213       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_tosend[6]              ;
; 32.995 ; 33.213       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dminus~en                   ;
; 32.995 ; 33.213       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dminus~reg0                 ;
; 32.995 ; 33.213       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dplus~en                    ;
; 32.995 ; 33.213       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dplus~reg0                  ;
; 32.995 ; 33.213       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.send_bit1      ;
; 32.995 ; 33.213       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.send_bit2      ;
; 32.995 ; 33.213       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.send_bit3      ;
; 32.995 ; 33.213       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.send_bit4      ;
; 32.996 ; 33.214       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_rom[0]              ;
; 32.996 ; 33.214       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_rom[1]              ;
; 32.996 ; 33.214       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_rom[2]              ;
; 32.996 ; 33.214       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_rom[3]              ;
; 32.996 ; 33.214       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_rom[4]              ;
; 32.996 ; 33.214       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_rom[5]              ;
; 32.996 ; 33.214       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_rom[6]              ;
; 32.996 ; 33.214       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_rom[7]              ;
; 32.996 ; 33.214       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_rom[8]              ;
; 32.996 ; 33.214       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[0]                ;
; 32.996 ; 33.214       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[1]                ;
; 32.996 ; 33.214       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[2]                ;
; 32.996 ; 33.214       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[3]                ;
; 32.996 ; 33.214       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[4]                ;
; 32.996 ; 33.214       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[5]                ;
; 32.996 ; 33.214       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[6]                ;
; 32.996 ; 33.214       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[7]                ;
; 32.996 ; 33.214       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dm1_last~_emulated          ;
; 32.996 ; 33.214       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dp1_last~_emulated          ;
; 32.996 ; 33.214       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dplus_buf1                  ;
; 32.996 ; 33.214       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.Idle           ;
; 32.996 ; 33.214       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.end_send1      ;
; 32.996 ; 33.214       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.end_send2      ;
; 32.996 ; 33.214       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.reset_released ;
; 32.996 ; 33.214       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.reset_start    ;
; 32.996 ; 33.214       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.send2          ;
; 32.996 ; 33.214       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.send3          ;
; 32.996 ; 33.214       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.send_bit0      ;
; 32.996 ; 33.214       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.send_complete  ;
; 32.997 ; 33.215       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dminus_buf2                 ;
; 32.997 ; 33.215       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dp2_prev~_emulated          ;
; 32.997 ; 33.215       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dplus_buf2                  ;
; 32.997 ; 33.215       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|joyleft_out[0]              ;
; 32.997 ; 33.215       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|joyleft_out[1]              ;
; 32.997 ; 33.215       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|joyleft_out[2]              ;
; 32.997 ; 33.215       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|joyleft_out[3]              ;
; 32.997 ; 33.215       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|joyright_out[3]             ;
; 32.997 ; 33.215       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rden_sig                    ;
; 32.997 ; 33.215       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|reg_10bits_receive[0]       ;
; 32.997 ; 33.215       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|reg_10bits_receive[1]       ;
; 32.997 ; 33.215       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|reg_10bits_receive[2]       ;
; 32.997 ; 33.215       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|reg_10bits_receive[3]       ;
; 32.997 ; 33.215       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|reg_10bits_receive[4]       ;
; 32.997 ; 33.215       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|reg_10bits_receive[5]       ;
; 32.997 ; 33.215       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|reg_10bits_receive[6]       ;
; 32.997 ; 33.215       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|reg_10bits_receive[7]       ;
; 32.997 ; 33.215       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|reg_10bits_receive[8]       ;
; 32.997 ; 33.215       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|reg_10bits_receive[9]       ;
; 32.997 ; 33.215       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|send_frame                  ;
; 32.997 ; 33.215       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state3           ;
; 32.997 ; 33.215       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state4           ;
; 32.997 ; 33.215       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_send_com.send1          ;
; 32.997 ; 33.215       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|val                         ;
; 32.999 ; 33.217       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[0]                ;
; 32.999 ; 33.217       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[1]                ;
; 32.999 ; 33.217       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[2]                ;
; 32.999 ; 33.217       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[3]                ;
; 32.999 ; 33.217       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[4]                ;
; 32.999 ; 33.217       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[5]                ;
; 32.999 ; 33.217       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[6]                ;
; 32.999 ; 33.217       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[7]                ;
; 32.999 ; 33.217       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[0]                  ;
; 32.999 ; 33.217       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[1]                  ;
; 32.999 ; 33.217       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[2]                  ;
; 32.999 ; 33.217       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[3]                  ;
; 32.999 ; 33.217       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|read_byte_valid             ;
; 32.999 ; 33.217       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|reg_10bits[0]               ;
; 32.999 ; 33.217       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|reg_10bits[1]               ;
; 32.999 ; 33.217       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|reg_10bits[2]               ;
; 32.999 ; 33.217       ; 0.218          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|reg_10bits[3]               ;
+--------+--------------+----------------+------------------+------------------------------------------------------+------------+--------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'altera_reserved_tck'                                                                                                                                                                                                                                                      ;
+--------+--------------+----------------+------------------+---------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock               ; Clock Edge ; Target                                                                                                                                                                                                                ;
+--------+--------------+----------------+------------------+---------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 49.393 ; 49.626       ; 0.233          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ;
; 49.393 ; 49.626       ; 0.233          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                           ;
; 49.393 ; 49.626       ; 0.233          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ;
; 49.393 ; 49.626       ; 0.233          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                           ;
; 49.395 ; 49.628       ; 0.233          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_datain_reg0                                      ;
; 49.395 ; 49.628       ; 0.233          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_datain_reg0                                      ;
; 49.471 ; 49.689       ; 0.218          ; High Pulse Width ; altera_reserved_tck ; Fall       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ;
; 49.511 ; 49.697       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]                                                   ;
; 49.511 ; 49.697       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1]                                                   ;
; 49.511 ; 49.697       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2]                                                   ;
; 49.511 ; 49.697       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3]                                                   ;
; 49.511 ; 49.697       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4]                                                   ;
; 49.511 ; 49.697       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0]                                                                                                                    ;
; 49.511 ; 49.697       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1]                                                                                                                    ;
; 49.511 ; 49.697       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2]                                                                                                                    ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0]                                              ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1]                                              ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2]                                              ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3]                                              ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg                                                         ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]                                                   ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]                                                   ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]                                                   ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]                                                   ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]                                                   ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5]                                                   ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[6]                                                   ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7]                                                   ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8]                                                   ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[5]                                                   ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[6]                                                   ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7]                                                   ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[0]      ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[1]      ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[2]      ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[3]      ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[0] ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[1] ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[2] ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[3] ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]                                                   ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]                                                   ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]                                                   ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]                                                   ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]                                                   ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5]                                                   ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[6]                                                   ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7]                                                   ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8]                                                   ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]                                                   ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1]                                                   ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2]                                                   ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3]                                                   ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4]                                                   ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[5]                                                   ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[6]                                                   ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7]                                                   ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                        ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]                                        ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2]                                        ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                                                                                           ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                                                                                           ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2]                                                                                                                                           ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                                                                                                                                           ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                                                                                                                                           ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                                                                                           ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                           ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                                                                                           ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                                                                                           ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                                                                                                                                           ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0]                                                                                                                                    ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1]                                                                                                                                    ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2]                                                                                                                                    ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3]                                                                                                                                    ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][4]                                                                                                                                    ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0]                                                                                                                                    ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][1]                                                                                                                                    ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][2]                                                                                                                                    ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3]                                                                                                                                    ;
; 49.512 ; 49.698       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][4]                                                                                                                                    ;
; 49.513 ; 49.699       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                                                        ;
; 49.513 ; 49.699       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                        ;
; 49.513 ; 49.699       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]                                        ;
; 49.513 ; 49.699       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2]                                        ;
; 49.513 ; 49.699       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                                                        ;
; 49.513 ; 49.699       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0]                                              ;
; 49.513 ; 49.699       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1]                                              ;
; 49.513 ; 49.699       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2]                                              ;
; 49.513 ; 49.699       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3]                                              ;
; 49.513 ; 49.699       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg                                                         ;
; 49.513 ; 49.699       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[0]      ;
; 49.513 ; 49.699       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[1]      ;
; 49.513 ; 49.699       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[2]      ;
; 49.513 ; 49.699       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[3]      ;
; 49.513 ; 49.699       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[0] ;
; 49.513 ; 49.699       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[1] ;
; 49.513 ; 49.699       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[2] ;
; 49.513 ; 49.699       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[3] ;
; 49.513 ; 49.699       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                                                                                                                                                 ;
; 49.513 ; 49.699       ; 0.186          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0]                                                                                                                                         ;
+--------+--------------+----------------+------------------+---------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'                                                                                                                        ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------+
; Slack   ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                                                 ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------+
; 99.778  ; 99.778       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                                   ;
; 99.778  ; 99.778       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|observablevcoout                         ;
; 99.779  ; 99.779       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 99.779  ; 99.779       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 99.828  ; 99.828       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                       ;
; 99.856  ; 99.856       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|inclk[0]                                 ;
; 99.857  ; 99.857       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 100.000 ; 100.000      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                       ;
; 100.000 ; 100.000      ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                       ;
; 100.142 ; 100.142      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 100.143 ; 100.143      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|inclk[0]                                 ;
; 100.172 ; 100.172      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                       ;
; 100.218 ; 100.218      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 100.218 ; 100.218      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 100.219 ; 100.219      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                                   ;
; 100.219 ; 100.219      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|observablevcoout                         ;
; 196.000 ; 200.000      ; 4.000          ; Port Rate        ; FPGA_CLK ; Rise       ; FPGA_CLK                                                                               ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                                            ;
+---------------------+---------------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port           ; Clock Port          ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+---------------------+---------------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]         ; FPGA_CLK            ; 2.399 ; 2.570 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]        ; FPGA_CLK            ; 2.381 ; 2.552 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]        ; FPGA_CLK            ; 2.381 ; 2.552 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]        ; FPGA_CLK            ; 2.381 ; 2.552 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]        ; FPGA_CLK            ; 2.384 ; 2.555 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]        ; FPGA_CLK            ; 2.393 ; 2.564 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]        ; FPGA_CLK            ; 2.386 ; 2.557 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]        ; FPGA_CLK            ; 2.384 ; 2.555 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]        ; FPGA_CLK            ; 2.334 ; 2.504 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]        ; FPGA_CLK            ; 2.392 ; 2.563 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]        ; FPGA_CLK            ; 2.399 ; 2.570 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]       ; FPGA_CLK            ; 2.395 ; 2.566 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]       ; FPGA_CLK            ; 2.395 ; 2.566 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]       ; FPGA_CLK            ; 2.395 ; 2.566 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]       ; FPGA_CLK            ; 2.384 ; 2.555 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]       ; FPGA_CLK            ; 2.384 ; 2.555 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]       ; FPGA_CLK            ; 2.384 ; 2.555 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_DAT0             ; FPGA_CLK            ; 3.179 ; 3.389 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; altera_reserved_tdi ; altera_reserved_tck ; 2.250 ; 2.475 ; Rise       ; altera_reserved_tck                                                           ;
; altera_reserved_tms ; altera_reserved_tck ; 7.297 ; 7.524 ; Rise       ; altera_reserved_tck                                                           ;
; dminus1             ; FPGA_CLK            ; 3.255 ; 3.609 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dminus2             ; FPGA_CLK            ; 0.878 ; 1.184 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1              ; FPGA_CLK            ; 3.902 ; 4.252 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2              ; FPGA_CLK            ; 0.903 ; 1.236 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1              ; FPGA_CLK            ; 4.425 ; 4.742 ; Fall       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2              ; FPGA_CLK            ; 1.117 ; 1.441 ; Fall       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
+---------------------+---------------------+-------+-------+------------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                               ;
+---------------------+---------------------+--------+--------+------------+-------------------------------------------------------------------------------+
; Data Port           ; Clock Port          ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                               ;
+---------------------+---------------------+--------+--------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]         ; FPGA_CLK            ; -1.561 ; -1.731 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]        ; FPGA_CLK            ; -1.603 ; -1.774 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]        ; FPGA_CLK            ; -1.603 ; -1.774 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]        ; FPGA_CLK            ; -1.603 ; -1.774 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]        ; FPGA_CLK            ; -1.606 ; -1.777 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]        ; FPGA_CLK            ; -1.615 ; -1.786 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]        ; FPGA_CLK            ; -1.608 ; -1.779 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]        ; FPGA_CLK            ; -1.606 ; -1.777 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]        ; FPGA_CLK            ; -1.561 ; -1.731 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]        ; FPGA_CLK            ; -1.615 ; -1.786 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]        ; FPGA_CLK            ; -1.622 ; -1.793 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]       ; FPGA_CLK            ; -1.617 ; -1.788 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]       ; FPGA_CLK            ; -1.617 ; -1.788 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]       ; FPGA_CLK            ; -1.617 ; -1.788 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]       ; FPGA_CLK            ; -1.606 ; -1.777 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]       ; FPGA_CLK            ; -1.606 ; -1.777 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]       ; FPGA_CLK            ; -1.606 ; -1.777 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_DAT0             ; FPGA_CLK            ; -2.334 ; -2.543 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; altera_reserved_tdi ; altera_reserved_tck ; 0.978  ; 0.812  ; Rise       ; altera_reserved_tck                                                           ;
; altera_reserved_tms ; altera_reserved_tck ; -1.485 ; -1.674 ; Rise       ; altera_reserved_tck                                                           ;
; dminus1             ; FPGA_CLK            ; -2.533 ; -2.874 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dminus2             ; FPGA_CLK            ; -0.070 ; -0.365 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1              ; FPGA_CLK            ; -3.186 ; -3.524 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2              ; FPGA_CLK            ; -0.125 ; -0.447 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1              ; FPGA_CLK            ; -3.280 ; -3.579 ; Fall       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2              ; FPGA_CLK            ; -0.160 ; -0.485 ; Fall       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
+---------------------+---------------------+--------+--------+------------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                                    ;
+---------------------+---------------------+--------+--------+------------+-------------------------------------------------------------------------------+
; Data Port           ; Clock Port          ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                               ;
+---------------------+---------------------+--------+--------+------------+-------------------------------------------------------------------------------+
; SDRAM_A[*]          ; FPGA_CLK            ; 4.957  ; 5.132  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]         ; FPGA_CLK            ; 2.750  ; 2.600  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]         ; FPGA_CLK            ; 2.750  ; 2.600  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]         ; FPGA_CLK            ; 2.754  ; 2.604  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]         ; FPGA_CLK            ; 2.754  ; 2.604  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]         ; FPGA_CLK            ; 2.742  ; 2.592  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]         ; FPGA_CLK            ; 2.742  ; 2.592  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]         ; FPGA_CLK            ; 2.740  ; 2.590  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]         ; FPGA_CLK            ; 2.049  ; 1.992  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]         ; FPGA_CLK            ; 4.957  ; 5.132  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]         ; FPGA_CLK            ; 2.741  ; 2.591  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]        ; FPGA_CLK            ; 2.750  ; 2.600  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]        ; FPGA_CLK            ; 2.741  ; 2.591  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]         ; FPGA_CLK            ; 4.968  ; 5.143  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]        ; FPGA_CLK            ; 4.968  ; 5.143  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]        ; FPGA_CLK            ; 2.060  ; 2.003  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N         ; FPGA_CLK            ; 2.063  ; 2.006  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N          ; FPGA_CLK            ; 2.753  ; 2.603  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]         ; FPGA_CLK            ; 4.398  ; 4.731  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]        ; FPGA_CLK            ; 3.061  ; 2.998  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]        ; FPGA_CLK            ; 3.061  ; 2.998  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]        ; FPGA_CLK            ; 3.061  ; 2.998  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]        ; FPGA_CLK            ; 4.398  ; 4.731  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]        ; FPGA_CLK            ; 4.389  ; 4.722  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]        ; FPGA_CLK            ; 2.206  ; 2.169  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]        ; FPGA_CLK            ; 2.930  ; 2.809  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]        ; FPGA_CLK            ; 2.753  ; 2.603  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]        ; FPGA_CLK            ; 3.049  ; 2.986  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]        ; FPGA_CLK            ; 4.382  ; 4.715  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]       ; FPGA_CLK            ; 3.047  ; 2.984  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]       ; FPGA_CLK            ; 3.047  ; 2.984  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]       ; FPGA_CLK            ; 3.047  ; 2.984  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]       ; FPGA_CLK            ; 4.398  ; 4.731  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]       ; FPGA_CLK            ; 3.058  ; 2.995  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]       ; FPGA_CLK            ; 3.058  ; 2.995  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH_n        ; FPGA_CLK            ; 2.742  ; 2.592  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML_n        ; FPGA_CLK            ; 2.753  ; 2.603  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N         ; FPGA_CLK            ; 2.753  ; 2.603  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N          ; FPGA_CLK            ; 4.971  ; 5.146  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L             ; FPGA_CLK            ; 5.339  ; 5.550  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R             ; FPGA_CLK            ; 2.825  ; 2.725  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK              ; FPGA_CLK            ; 4.594  ; 4.422  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD              ; FPGA_CLK            ; 4.096  ; 3.988  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3             ; FPGA_CLK            ; 4.284  ; 4.418  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK           ; FPGA_CLK            ; 11.357 ;        ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK           ; FPGA_CLK            ;        ; 11.555 ; Fall       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]            ; FPGA_CLK            ; 4.267  ; 4.535  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[0]           ; FPGA_CLK            ; 2.050  ; 1.993  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[1]           ; FPGA_CLK            ; 4.267  ; 4.535  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[2]           ; FPGA_CLK            ; 2.049  ; 1.992  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[3]           ; FPGA_CLK            ; 2.052  ; 1.995  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
; VGA_G[*]            ; FPGA_CLK            ; 4.269  ; 4.537  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[0]           ; FPGA_CLK            ; 2.051  ; 1.994  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[1]           ; FPGA_CLK            ; 2.051  ; 1.994  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[2]           ; FPGA_CLK            ; 2.051  ; 1.994  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[3]           ; FPGA_CLK            ; 4.269  ; 4.537  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
; altera_reserved_tdo ; altera_reserved_tck ; 11.640 ; 12.477 ; Fall       ; altera_reserved_tck                                                           ;
; dminus1             ; FPGA_CLK            ; 5.295  ; 5.200  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dminus2             ; FPGA_CLK            ; 7.049  ; 6.969  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1              ; FPGA_CLK            ; 7.689  ; 7.428  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2              ; FPGA_CLK            ; 7.010  ; 7.083  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
+---------------------+---------------------+--------+--------+------------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                                            ;
+---------------------+---------------------+--------+--------+------------+-------------------------------------------------------------------------------+
; Data Port           ; Clock Port          ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                               ;
+---------------------+---------------------+--------+--------+------------+-------------------------------------------------------------------------------+
; SDRAM_A[*]          ; FPGA_CLK            ; 1.411  ; 1.354  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]         ; FPGA_CLK            ; 2.084  ; 1.937  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]         ; FPGA_CLK            ; 2.084  ; 1.937  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]         ; FPGA_CLK            ; 2.088  ; 1.941  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]         ; FPGA_CLK            ; 2.088  ; 1.941  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]         ; FPGA_CLK            ; 2.076  ; 1.929  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]         ; FPGA_CLK            ; 2.076  ; 1.929  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]         ; FPGA_CLK            ; 2.074  ; 1.927  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]         ; FPGA_CLK            ; 1.411  ; 1.354  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]         ; FPGA_CLK            ; 4.292  ; 4.470  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]         ; FPGA_CLK            ; 2.075  ; 1.928  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]        ; FPGA_CLK            ; 2.084  ; 1.937  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]        ; FPGA_CLK            ; 2.075  ; 1.928  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]         ; FPGA_CLK            ; 1.421  ; 1.364  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]        ; FPGA_CLK            ; 4.302  ; 4.480  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]        ; FPGA_CLK            ; 1.421  ; 1.364  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N         ; FPGA_CLK            ; 1.424  ; 1.367  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N          ; FPGA_CLK            ; 2.087  ; 1.940  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]         ; FPGA_CLK            ; 1.567  ; 1.529  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]        ; FPGA_CLK            ; 2.394  ; 2.333  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]        ; FPGA_CLK            ; 2.394  ; 2.333  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]        ; FPGA_CLK            ; 2.394  ; 2.333  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]        ; FPGA_CLK            ; 3.759  ; 4.091  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]        ; FPGA_CLK            ; 3.750  ; 4.082  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]        ; FPGA_CLK            ; 1.567  ; 1.529  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]        ; FPGA_CLK            ; 2.263  ; 2.144  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]        ; FPGA_CLK            ; 2.087  ; 1.940  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]        ; FPGA_CLK            ; 2.383  ; 2.322  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]        ; FPGA_CLK            ; 3.744  ; 4.076  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]       ; FPGA_CLK            ; 2.380  ; 2.319  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]       ; FPGA_CLK            ; 2.380  ; 2.319  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]       ; FPGA_CLK            ; 2.380  ; 2.319  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]       ; FPGA_CLK            ; 3.759  ; 4.091  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]       ; FPGA_CLK            ; 2.391  ; 2.330  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]       ; FPGA_CLK            ; 2.391  ; 2.330  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH_n        ; FPGA_CLK            ; 2.076  ; 1.929  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML_n        ; FPGA_CLK            ; 2.087  ; 1.940  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N         ; FPGA_CLK            ; 2.087  ; 1.940  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N          ; FPGA_CLK            ; 4.305  ; 4.483  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L             ; FPGA_CLK            ; 4.566  ; 4.778  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R             ; FPGA_CLK            ; 2.064  ; 1.965  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK              ; FPGA_CLK            ; 3.763  ; 3.595  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD              ; FPGA_CLK            ; 3.285  ; 3.178  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3             ; FPGA_CLK            ; 3.463  ; 3.594  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK           ; FPGA_CLK            ; 10.646 ;        ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK           ; FPGA_CLK            ;        ; 10.846 ; Fall       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]            ; FPGA_CLK            ; 1.411  ; 1.354  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[0]           ; FPGA_CLK            ; 1.412  ; 1.355  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[1]           ; FPGA_CLK            ; 3.629  ; 3.897  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[2]           ; FPGA_CLK            ; 1.411  ; 1.354  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[3]           ; FPGA_CLK            ; 1.413  ; 1.356  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
; VGA_G[*]            ; FPGA_CLK            ; 1.413  ; 1.356  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[0]           ; FPGA_CLK            ; 1.413  ; 1.356  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[1]           ; FPGA_CLK            ; 1.413  ; 1.356  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[2]           ; FPGA_CLK            ; 1.413  ; 1.356  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[3]           ; FPGA_CLK            ; 3.630  ; 3.898  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
; altera_reserved_tdo ; altera_reserved_tck ; 9.351  ; 10.188 ; Fall       ; altera_reserved_tck                                                           ;
; dminus1             ; FPGA_CLK            ; 4.731  ; 4.640  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dminus2             ; FPGA_CLK            ; 6.411  ; 6.332  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1              ; FPGA_CLK            ; 7.125  ; 6.862  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2              ; FPGA_CLK            ; 6.371  ; 6.443  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
+---------------------+---------------------+--------+--------+------------+-------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.852 ; 2.803 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.462 ; 3.413 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.462 ; 3.413 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.462 ; 3.413 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 6.005 ; 6.268 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 6.334 ; 6.597 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.832 ; 3.722 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.831 ; 3.721 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.985 ; 3.857 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.747 ; 3.698 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 5.530 ; 5.793 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.159 ; 3.110 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.159 ; 3.110 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.159 ; 3.110 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 4.913 ; 5.176 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.852 ; 2.803 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.852 ; 2.803 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 4.293 ; 4.165 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 4.893 ; 4.844 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dminus2       ; FPGA_CLK   ; 7.060 ; 6.950 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1        ; FPGA_CLK   ; 7.018 ; 7.281 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2        ; FPGA_CLK   ; 7.240 ; 7.130 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                             ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.119 ; 2.070 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.704 ; 2.655 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.704 ; 2.655 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.704 ; 2.655 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 5.228 ; 5.491 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 5.544 ; 5.807 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.055 ; 2.945 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.054 ; 2.944 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.160 ; 3.032 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.978 ; 2.929 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 4.772 ; 5.035 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.414 ; 2.365 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.414 ; 2.365 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.414 ; 2.365 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 4.179 ; 4.442 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.119 ; 2.070 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.119 ; 2.070 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.458 ; 3.330 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 4.364 ; 4.315 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dminus2       ; FPGA_CLK   ; 6.440 ; 6.330 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1        ; FPGA_CLK   ; 6.487 ; 6.750 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2        ; FPGA_CLK   ; 6.613 ; 6.503 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                            ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.816     ; 2.865     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.409     ; 3.458     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.409     ; 3.458     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.409     ; 3.458     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 6.226     ; 5.963     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 6.533     ; 6.270     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.663     ; 3.773     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.689     ; 3.799     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.796     ; 3.924     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.669     ; 3.718     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 5.792     ; 5.529     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.120     ; 3.169     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.120     ; 3.169     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.120     ; 3.169     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 5.189     ; 4.926     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.816     ; 2.865     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.816     ; 2.865     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 4.161     ; 4.289     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 4.828     ; 4.877     ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dminus2       ; FPGA_CLK   ; 6.912     ; 7.022     ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1        ; FPGA_CLK   ; 7.291     ; 7.028     ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2        ; FPGA_CLK   ; 7.049     ; 7.159     ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                                    ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.082     ; 2.131     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.652     ; 2.701     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.652     ; 2.701     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.652     ; 2.701     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 5.451     ; 5.188     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 5.745     ; 5.482     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.887     ; 2.997     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.912     ; 3.022     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.974     ; 3.102     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.901     ; 2.950     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 5.034     ; 4.771     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.374     ; 2.423     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.374     ; 2.423     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.374     ; 2.423     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 4.455     ; 4.192     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.082     ; 2.131     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.082     ; 2.131     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.326     ; 3.454     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 4.300     ; 4.349     ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dminus2       ; FPGA_CLK   ; 6.294     ; 6.404     ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1        ; FPGA_CLK   ; 6.760     ; 6.497     ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2        ; FPGA_CLK   ; 6.425     ; 6.535     ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+


---------------------------------------------
; Slow 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+--------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup Summary                                                                     ;
+-------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                         ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; -3.915 ; -445.217      ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.587  ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 6.602  ; 0.000         ;
; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ; 29.519 ; 0.000         ;
; altera_reserved_tck                                                           ; 47.974 ; 0.000         ;
+-------------------------------------------------------------------------------+--------+---------------+


+-------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold Summary                                                                     ;
+-------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                         ; Slack ; End Point TNS ;
+-------------------------------------------------------------------------------+-------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.141 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.159 ; 0.000         ;
; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ; 0.185 ; 0.000         ;
; altera_reserved_tck                                                           ; 0.187 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.188 ; 0.000         ;
+-------------------------------------------------------------------------------+-------+---------------+


+--------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery Summary                                                                  ;
+-------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                         ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 9.208  ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 9.725  ; 0.000         ;
; altera_reserved_tck                                                           ; 49.197 ; 0.000         ;
; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ; 64.844 ; 0.000         ;
+-------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal Summary                                                                   ;
+-------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                         ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------+--------+---------------+
; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ; -0.015 ; -0.358        ;
; altera_reserved_tck                                                           ; 0.585  ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.694  ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1.107  ; 0.000         ;
+-------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width Summary                                                       ;
+-------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                         ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 4.188  ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.655  ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.369 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]  ; 17.601 ; 0.000         ;
; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ; 33.024 ; 0.000         ;
; altera_reserved_tck                                                           ; 49.295 ; 0.000         ;
; FPGA_CLK                                                                      ; 99.418 ; 0.000         ;
+-------------------------------------------------------------------------------+--------+---------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                         ;
+--------+--------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                        ; To Node                                                                                                                 ; Launch Clock                                         ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; -3.915 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.057     ; 2.993      ;
; -3.899 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.056     ; 2.978      ;
; -3.811 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[6]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[28]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.242     ; 2.704      ;
; -3.783 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.055     ; 2.863      ;
; -3.764 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[6]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[27]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.242     ; 2.657      ;
; -3.755 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.050     ; 2.840      ;
; -3.738 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[6] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[28]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.242     ; 2.631      ;
; -3.735 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[7] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[28]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.242     ; 2.628      ;
; -3.728 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[38] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.057     ; 2.806      ;
; -3.728 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[7]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[28]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.242     ; 2.621      ;
; -3.723 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[7]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[27]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.242     ; 2.616      ;
; -3.719 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[7] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[27]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.242     ; 2.612      ;
; -3.706 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[2]   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.249     ; 2.592      ;
; -3.691 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[18] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.059     ; 2.767      ;
; -3.691 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[6] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[27]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.242     ; 2.584      ;
; -3.687 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[10]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.254     ; 2.568      ;
; -3.684 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[5]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.050     ; 2.769      ;
; -3.680 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[2]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.246     ; 2.569      ;
; -3.670 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.048     ; 2.757      ;
; -3.668 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[6]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[29]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.241     ; 2.562      ;
; -3.666 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[41] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.060     ; 2.741      ;
; -3.662 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[27] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.057     ; 2.740      ;
; -3.661 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[6]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[30]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.241     ; 2.555      ;
; -3.654 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.046     ; 2.743      ;
; -3.653 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[4] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.048     ; 2.740      ;
; -3.651 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[29] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.050     ; 2.736      ;
; -3.643 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[1]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.223     ; 2.555      ;
; -3.641 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[37] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.061     ; 2.715      ;
; -3.632 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|doReg[2]    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.073     ; 2.694      ;
; -3.627 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[7]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[29]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.241     ; 2.521      ;
; -3.623 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.044     ; 2.714      ;
; -3.623 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[7] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[29]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.241     ; 2.517      ;
; -3.622 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[1]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.224     ; 2.533      ;
; -3.620 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[2]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.234     ; 2.521      ;
; -3.619 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[2]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.239     ; 2.515      ;
; -3.618 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[1] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[0]                                                                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.231     ; 2.522      ;
; -3.608 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[6]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[26]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.241     ; 2.502      ;
; -3.605 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.045     ; 2.695      ;
; -3.601 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[4] ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[0]                                                                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.231     ; 2.505      ;
; -3.599 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.046     ; 2.688      ;
; -3.595 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[6] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[29]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.241     ; 2.489      ;
; -3.591 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[39] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.060     ; 2.666      ;
; -3.590 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[2]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.073     ; 2.652      ;
; -3.588 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[6]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[23]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.243     ; 2.480      ;
; -3.588 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[6] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[30]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.241     ; 2.482      ;
; -3.588 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[1]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.223     ; 2.500      ;
; -3.586 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[2]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.055     ; 2.666      ;
; -3.585 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[7] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[30]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.241     ; 2.479      ;
; -3.580 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[6]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[24]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.241     ; 2.474      ;
; -3.578 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[7]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[30]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.241     ; 2.472      ;
; -3.570 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[1]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.228     ; 2.477      ;
; -3.568 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.044     ; 2.659      ;
; -3.567 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[1]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.224     ; 2.478      ;
; -3.560 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[6]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[31]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.053     ; 2.642      ;
; -3.557 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[0]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.056     ; 2.636      ;
; -3.552 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_reg[2]                   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.231     ; 2.456      ;
; -3.550 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.045     ; 2.640      ;
; -3.547 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[7]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[23]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.243     ; 2.439      ;
; -3.543 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[7] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[23]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.243     ; 2.435      ;
; -3.537 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[11] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.051     ; 2.621      ;
; -3.535 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[6] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[26]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.241     ; 2.429      ;
; -3.534 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[10] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.059     ; 2.610      ;
; -3.532 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[7] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[26]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.241     ; 2.426      ;
; -3.526 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[11] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.040     ; 2.621      ;
; -3.525 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[7]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[26]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.241     ; 2.419      ;
; -3.520 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[15] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.059     ; 2.596      ;
; -3.519 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[7]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[31]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.053     ; 2.601      ;
; -3.515 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.049     ; 2.601      ;
; -3.515 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[6] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[23]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.243     ; 2.407      ;
; -3.515 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[1]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.228     ; 2.422      ;
; -3.515 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[7] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[31]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.053     ; 2.597      ;
; -3.514 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[29] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.039     ; 2.610      ;
; -3.508 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[34] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.059     ; 2.584      ;
; -3.507 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[6] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[24]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.241     ; 2.401      ;
; -3.504 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[7] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[24]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.241     ; 2.398      ;
; -3.499 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[1]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.056     ; 2.578      ;
; -3.497 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[25] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.240     ; 2.392      ;
; -3.497 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[24] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.240     ; 2.392      ;
; -3.497 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[1]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.235     ; 2.397      ;
; -3.497 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[27] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.046     ; 2.586      ;
; -3.497 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[7]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[24]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.241     ; 2.391      ;
; -3.496 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[6]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.240     ; 2.391      ;
; -3.495 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[6]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[20]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.243     ; 2.387      ;
; -3.495 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[4] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.049     ; 2.581      ;
; -3.487 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[6] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[31]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.053     ; 2.569      ;
; -3.485 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[0]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.048     ; 2.572      ;
; -3.482 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[41] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.049     ; 2.568      ;
; -3.480 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[22] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.061     ; 2.554      ;
; -3.476 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[16] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.060     ; 2.551      ;
; -3.473 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[26] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.059     ; 2.549      ;
; -3.471 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[11] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.040     ; 2.566      ;
; -3.465 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[4] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[0]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.048     ; 2.552      ;
; -3.463 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[6]  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[25]                                                           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.242     ; 2.356      ;
; -3.459 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[29] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.039     ; 2.555      ;
; -3.454 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.039     ; 2.550      ;
; -3.450 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[1]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.045     ; 2.540      ;
; -3.444 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[38] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.049     ; 2.530      ;
; -3.442 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[1]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.235     ; 2.342      ;
; -3.442 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyleft_out[4]  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[27] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.046     ; 2.531      ;
; -3.438 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|joyright_out[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[39] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.298        ; -1.052     ; 2.521      ;
+--------+--------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                       ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                         ; To Node                                      ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 5.587 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.096     ; 6.003      ;
; 5.595 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 5.988      ;
; 5.625 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 5.958      ;
; 5.637 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.096     ; 5.953      ;
; 5.645 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 5.938      ;
; 5.648 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.089     ; 5.949      ;
; 5.653 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.098     ; 5.935      ;
; 5.656 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.096     ; 5.934      ;
; 5.662 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.096     ; 5.928      ;
; 5.675 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 5.908      ;
; 5.686 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.096     ; 5.904      ;
; 5.703 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.098     ; 5.885      ;
; 5.706 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.091     ; 5.889      ;
; 5.712 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.096     ; 5.878      ;
; 5.713 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[9]                             ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.089     ; 5.884      ;
; 5.714 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.091     ; 5.881      ;
; 5.716 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.092     ; 5.878      ;
; 5.719 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.098     ; 5.869      ;
; 5.723 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.089     ; 5.874      ;
; 5.724 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 5.863      ;
; 5.746 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 5.837      ;
; 5.754 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 5.833      ;
; 5.756 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.091     ; 5.839      ;
; 5.763 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[9]                             ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.089     ; 5.834      ;
; 5.767 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.084     ; 5.835      ;
; 5.769 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.098     ; 5.819      ;
; 5.774 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[9]                             ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.082     ; 5.830      ;
; 5.780 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 5.803      ;
; 5.780 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.091     ; 5.815      ;
; 5.782 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.094     ; 5.810      ;
; 5.786 ; sdram_reset_n_reg                                                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.094     ; 5.806      ;
; 5.786 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.098     ; 5.802      ;
; 5.791 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.092     ; 5.803      ;
; 5.796 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 5.787      ;
; 5.807 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.096     ; 5.783      ;
; 5.813 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.100     ; 5.773      ;
; 5.817 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[12]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.092     ; 5.777      ;
; 5.830 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 5.753      ;
; 5.835 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.087     ; 5.764      ;
; 5.836 ; sdram_reset_n_reg                                                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.094     ; 5.756      ;
; 5.836 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.098     ; 5.752      ;
; 5.841 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.096     ; 5.749      ;
; 5.842 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[9]                             ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.085     ; 5.759      ;
; 5.847 ; sdram_reset_n_reg                                                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.087     ; 5.752      ;
; 5.847 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.091     ; 5.748      ;
; 5.848 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.094     ; 5.744      ;
; 5.849 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.100     ; 5.737      ;
; 5.863 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.100     ; 5.723      ;
; 5.867 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[12]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.092     ; 5.727      ;
; 5.870 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[11]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.091     ; 5.725      ;
; 5.874 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.093     ; 5.719      ;
; 5.875 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 5.712      ;
; 5.878 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[12]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.085     ; 5.723      ;
; 5.879 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.091     ; 5.716      ;
; 5.899 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.100     ; 5.687      ;
; 5.909 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 5.678      ;
; 5.910 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.093     ; 5.683      ;
; 5.915 ; sdram_reset_n_reg                                                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.090     ; 5.681      ;
; 5.915 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.094     ; 5.677      ;
; 5.920 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[11]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.091     ; 5.675      ;
; 5.929 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.091     ; 5.666      ;
; 5.931 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[11]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.084     ; 5.671      ;
; 5.940 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.084     ; 5.662      ;
; 5.942 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.096     ; 5.648      ;
; 5.943 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 5.646      ;
; 5.946 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[12]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.088     ; 5.652      ;
; 5.965 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                                                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.098     ; 5.623      ;
; 5.973 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[13]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.092     ; 5.621      ;
; 5.974 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[10]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.089     ; 5.623      ;
; 5.978 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.096     ; 5.612      ;
; 5.997 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.089     ; 5.600      ;
; 5.999 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[11]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.087     ; 5.600      ;
; 6.005 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.096     ; 5.585      ;
; 6.008 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.087     ; 5.591      ;
; 6.011 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[13]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.100     ; 5.575      ;
; 6.015 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                                                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.098     ; 5.573      ;
; 6.018 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 5.571      ;
; 6.020 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 5.561      ;
; 6.022 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[11] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 5.567      ;
; 6.023 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[13]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.092     ; 5.571      ;
; 6.024 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[10]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.089     ; 5.573      ;
; 6.026 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                                                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.091     ; 5.569      ;
; 6.027 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 5.560      ;
; 6.030 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[11] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.104     ; 5.552      ;
; 6.032 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[9]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.101     ; 5.553      ;
; 6.034 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[13]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.085     ; 5.567      ;
; 6.035 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.096     ; 5.555      ;
; 6.035 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[10]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.082     ; 5.569      ;
; 6.045 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[11]                                                                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.098     ; 5.543      ;
; 6.050 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 5.531      ;
; 6.054 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_READ_reg                                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 5.535      ;
; 6.058 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 5.529      ;
; 6.060 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[11] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.104     ; 5.522      ;
; 6.061 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[13]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.100     ; 5.525      ;
; 6.061 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 5.526      ;
; 6.063 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.091     ; 5.532      ;
; 6.066 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.106     ; 5.514      ;
; 6.072 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[13]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.093     ; 5.521      ;
; 6.072 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.089     ; 5.525      ;
; 6.082 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[9]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.101     ; 5.503      ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3]'                                                                                                                                                  ;
+-------+-------------------------+-------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node               ; To Node           ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------+-------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 6.602 ; svideo_yout_dly2[4]     ; cvbs2_out[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.038     ; 2.109      ;
; 6.609 ; svideo_yout_dly2[6]     ; cvbs2_out[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.038     ; 2.102      ;
; 6.644 ; svideo_yout_dly2[3]     ; cvbs2_out[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.038     ; 2.067      ;
; 6.676 ; svideo_yout_dly2[2]     ; cvbs2_out[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.038     ; 2.035      ;
; 6.709 ; svideo_yout_dly2[4]     ; cvbs2_out[2]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.039     ; 2.001      ;
; 6.716 ; svideo_yout_dly2[6]     ; cvbs2_out[2]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.039     ; 1.994      ;
; 6.751 ; svideo_yout_dly2[3]     ; cvbs2_out[2]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.039     ; 1.959      ;
; 6.756 ; svideo_yout_dly2[5]     ; cvbs2_out[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.038     ; 1.955      ;
; 6.773 ; svideo_yout_dly2[1]     ; cvbs2_out[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.038     ; 1.938      ;
; 6.782 ; svideo_yout_dly2[2]     ; cvbs2_out[2]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.039     ; 1.928      ;
; 6.785 ; svideo_yout_dly2[7]     ; cvbs2_out[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.038     ; 1.926      ;
; 6.813 ; svideo_yout_dly2[4]     ; cvbs2_out[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.039     ; 1.897      ;
; 6.820 ; svideo_yout_dly2[6]     ; cvbs2_out[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.039     ; 1.890      ;
; 6.837 ; svideo_yout_dly2[4]     ; cvbs2_out[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.041     ; 1.871      ;
; 6.844 ; svideo_yout_dly2[6]     ; cvbs2_out[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.041     ; 1.864      ;
; 6.846 ; svideo_yout_dly2[4]     ; cvbs2_out[3]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.039     ; 1.864      ;
; 6.847 ; svideo_yout_dly2[2]     ; cvbs2_out[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.039     ; 1.863      ;
; 6.853 ; svideo_yout_dly2[6]     ; cvbs2_out[3]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.039     ; 1.857      ;
; 6.855 ; svideo_yout_dly2[3]     ; cvbs2_out[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.039     ; 1.855      ;
; 6.863 ; svideo_yout_dly2[5]     ; cvbs2_out[2]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.039     ; 1.847      ;
; 6.879 ; svideo_yout_dly2[3]     ; cvbs2_out[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.041     ; 1.829      ;
; 6.880 ; svideo_yout_dly2[1]     ; cvbs2_out[2]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.039     ; 1.830      ;
; 6.888 ; svideo_yout_dly2[3]     ; cvbs2_out[3]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.039     ; 1.822      ;
; 6.891 ; svideo_yout_dly2[2]     ; cvbs2_out[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.041     ; 1.817      ;
; 6.892 ; svideo_yout_dly2[7]     ; cvbs2_out[2]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.039     ; 1.818      ;
; 6.900 ; svideo_yout_dly2[2]     ; cvbs2_out[3]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.039     ; 1.810      ;
; 6.904 ; svideo_yout_dly2[4]     ; cvbs2_out[0]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.039     ; 1.806      ;
; 6.911 ; svideo_yout_dly2[6]     ; cvbs2_out[0]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.039     ; 1.799      ;
; 6.913 ; svideo_yout_dly2[4]     ; cvbs2_out[1]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.039     ; 1.797      ;
; 6.920 ; svideo_yout_dly2[6]     ; cvbs2_out[1]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.039     ; 1.790      ;
; 6.946 ; svideo_yout_dly2[3]     ; cvbs2_out[0]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.039     ; 1.764      ;
; 6.947 ; svideo_yout_dly2[0]     ; cvbs2_out[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.038     ; 1.764      ;
; 6.955 ; svideo_yout_dly2[3]     ; cvbs2_out[1]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.039     ; 1.755      ;
; 6.959 ; svideo_yout_dly2[2]     ; cvbs2_out[0]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.039     ; 1.751      ;
; 6.967 ; svideo_yout_dly2[5]     ; cvbs2_out[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.039     ; 1.743      ;
; 6.968 ; svideo_yout_dly2[7]     ; cvbs2_out[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.039     ; 1.742      ;
; 6.968 ; svideo_yout_dly2[2]     ; cvbs2_out[1]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.039     ; 1.742      ;
; 6.984 ; svideo_yout_dly2[1]     ; cvbs2_out[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.039     ; 1.726      ;
; 6.991 ; svideo_yout_dly2[5]     ; cvbs2_out[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.041     ; 1.717      ;
; 7.000 ; svideo_yout_dly2[5]     ; cvbs2_out[3]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.039     ; 1.710      ;
; 7.008 ; svideo_yout_dly2[1]     ; cvbs2_out[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.041     ; 1.700      ;
; 7.012 ; svideo_yout_dly2[7]     ; cvbs2_out[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.041     ; 1.696      ;
; 7.017 ; svideo_yout_dly2[1]     ; cvbs2_out[3]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.039     ; 1.693      ;
; 7.021 ; svideo_yout_dly2[7]     ; cvbs2_out[3]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.039     ; 1.689      ;
; 7.027 ; svideo_yout_dly2[4]     ; cvbs2_out[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.041     ; 1.681      ;
; 7.034 ; svideo_yout_dly2[6]     ; cvbs2_out[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.041     ; 1.674      ;
; 7.054 ; svideo_yout_dly2[0]     ; cvbs2_out[2]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.039     ; 1.656      ;
; 7.058 ; svideo_yout_dly2[5]     ; cvbs2_out[0]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.039     ; 1.652      ;
; 7.062 ; svideo_yout_dly2[2]     ; cvbs2_out[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.041     ; 1.646      ;
; 7.067 ; svideo_yout_dly2[5]     ; cvbs2_out[1]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.039     ; 1.643      ;
; 7.069 ; svideo_yout_dly2[3]     ; cvbs2_out[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.041     ; 1.639      ;
; 7.075 ; svideo_yout_dly2[1]     ; cvbs2_out[0]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.039     ; 1.635      ;
; 7.080 ; svideo_yout_dly2[7]     ; cvbs2_out[0]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.039     ; 1.630      ;
; 7.084 ; svideo_yout_dly2[1]     ; cvbs2_out[1]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.039     ; 1.626      ;
; 7.089 ; svideo_yout_dly2[7]     ; cvbs2_out[1]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.039     ; 1.621      ;
; 7.143 ; svideo_yout_dly2[0]     ; cvbs2_out[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.039     ; 1.567      ;
; 7.181 ; svideo_yout_dly2[5]     ; cvbs2_out[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.041     ; 1.527      ;
; 7.182 ; svideo_yout_dly2[0]     ; cvbs2_out[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.041     ; 1.526      ;
; 7.183 ; svideo_yout_dly2[7]     ; cvbs2_out[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.041     ; 1.525      ;
; 7.191 ; svideo_yout_dly2[0]     ; cvbs2_out[3]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.039     ; 1.519      ;
; 7.198 ; svideo_yout_dly2[1]     ; cvbs2_out[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.041     ; 1.510      ;
; 7.213 ; cvbs1_out[9]            ; cvbs2_out[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.036     ; 1.500      ;
; 7.231 ; cvbs1_out[4]            ; cvbs2_out[2]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.037     ; 1.481      ;
; 7.249 ; svideo_yout_dly2[0]     ; cvbs2_out[0]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.039     ; 1.461      ;
; 7.258 ; svideo_yout_dly2[0]     ; cvbs2_out[1]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.039     ; 1.452      ;
; 7.330 ; cvbs1_out[2]            ; cvbs2_out[0]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.037     ; 1.382      ;
; 7.351 ; cvbs1_out[7]            ; cvbs2_out[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.039     ; 1.359      ;
; 7.355 ; cvbs1_out[3]            ; cvbs2_out[1]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.037     ; 1.357      ;
; 7.358 ; svideo_yout_dly2[0]     ; cvbs2_out[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.041     ; 1.350      ;
; 7.390 ; svideo:svideo|chroma[1] ; cvbs1_out[9]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.099     ; 1.308      ;
; 7.394 ; svideo:svideo|chroma[1] ; cvbs1_out[8]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.099     ; 1.304      ;
; 7.457 ; svideo:svideo|chroma[3] ; cvbs1_out[9]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.099     ; 1.241      ;
; 7.458 ; svideo:svideo|chroma[1] ; cvbs1_out[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.099     ; 1.240      ;
; 7.461 ; svideo:svideo|chroma[3] ; cvbs1_out[8]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.099     ; 1.237      ;
; 7.462 ; svideo:svideo|chroma[1] ; cvbs1_out[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.099     ; 1.236      ;
; 7.463 ; cvbs1_out[5]            ; cvbs2_out[3]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.037     ; 1.249      ;
; 7.466 ; svideo:svideo|chroma[0] ; cvbs1_out[9]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.099     ; 1.232      ;
; 7.474 ; svideo:svideo|chroma[0] ; cvbs1_out[8]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.099     ; 1.224      ;
; 7.517 ; svideo:svideo|chroma[2] ; cvbs1_out[9]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.099     ; 1.181      ;
; 7.518 ; svideo:svideo|luma[3]   ; luma_saturated[9] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.098     ; 1.181      ;
; 7.525 ; svideo:svideo|chroma[3] ; cvbs1_out[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.099     ; 1.173      ;
; 7.526 ; svideo:svideo|chroma[1] ; cvbs1_out[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.099     ; 1.172      ;
; 7.529 ; svideo:svideo|chroma[3] ; cvbs1_out[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.099     ; 1.169      ;
; 7.530 ; svideo:svideo|chroma[1] ; cvbs1_out[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.099     ; 1.168      ;
; 7.531 ; svideo:svideo|chroma[2] ; cvbs1_out[8]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.099     ; 1.167      ;
; 7.534 ; svideo:svideo|chroma[0] ; cvbs1_out[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.099     ; 1.164      ;
; 7.542 ; svideo:svideo|chroma[0] ; cvbs1_out[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.099     ; 1.156      ;
; 7.543 ; cvbs1_out[8]            ; cvbs2_out[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.039     ; 1.167      ;
; 7.545 ; svideo:svideo|chroma[5] ; cvbs1_out[9]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.099     ; 1.153      ;
; 7.549 ; svideo:svideo|chroma[5] ; cvbs1_out[8]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.099     ; 1.149      ;
; 7.579 ; svideo:svideo|luma[3]   ; luma_saturated[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.098     ; 1.120      ;
; 7.585 ; svideo:svideo|chroma[2] ; cvbs1_out[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.099     ; 1.113      ;
; 7.586 ; svideo:svideo|luma[3]   ; luma_saturated[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.098     ; 1.113      ;
; 7.588 ; svideo:svideo|chroma[4] ; cvbs1_out[9]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.099     ; 1.110      ;
; 7.592 ; svideo:svideo|chroma[7] ; cvbs1_out[9]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.099     ; 1.106      ;
; 7.592 ; svideo:svideo|chroma[4] ; cvbs1_out[8]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.099     ; 1.106      ;
; 7.593 ; svideo:svideo|chroma[3] ; cvbs1_out[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.099     ; 1.105      ;
; 7.594 ; svideo:svideo|chroma[1] ; cvbs1_out[3]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.099     ; 1.104      ;
; 7.596 ; svideo:svideo|chroma[7] ; cvbs1_out[8]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.099     ; 1.102      ;
; 7.597 ; svideo:svideo|chroma[3] ; cvbs1_out[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 8.810        ; -0.099     ; 1.101      ;
+-------+-------------------------+-------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'mcc_pll3|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                ;
+--------+-----------------------------------------------+---------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                     ; To Node                                           ; Launch Clock                                         ; Latch Clock                                          ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------+---------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+
; 29.519 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[7] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[14] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.773      ;
; 29.525 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[7] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[3]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.767      ;
; 29.533 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[7] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[6]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.759      ;
; 29.535 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[7] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[11] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.757      ;
; 29.536 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[7] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[10] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.756      ;
; 29.540 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[7] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[5]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.752      ;
; 29.542 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[7] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[9]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.750      ;
; 29.543 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[7] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[7]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.749      ;
; 29.598 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[14] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.694      ;
; 29.604 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[3]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.688      ;
; 29.612 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[6]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.680      ;
; 29.614 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[11] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.678      ;
; 29.615 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[10] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.677      ;
; 29.619 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[5]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.673      ;
; 29.621 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[9]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.671      ;
; 29.622 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[7]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.670      ;
; 29.629 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[14] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.663      ;
; 29.635 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[3]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.657      ;
; 29.643 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[6]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.649      ;
; 29.645 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[11] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.647      ;
; 29.646 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[10] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.646      ;
; 29.650 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[5]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.642      ;
; 29.652 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[9]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.640      ;
; 29.653 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[7]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.639      ;
; 29.678 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[7] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[4]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.614      ;
; 29.682 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[7] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[8]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.610      ;
; 29.691 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[7] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[1]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.601      ;
; 29.692 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[7] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[2]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.600      ;
; 29.731 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[14] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.561      ;
; 29.737 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[3]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.555      ;
; 29.745 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[6]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.547      ;
; 29.747 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[11] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.545      ;
; 29.748 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[10] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.544      ;
; 29.752 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[5]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.540      ;
; 29.754 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[9]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.538      ;
; 29.755 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[7]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.537      ;
; 29.756 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[14] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.536      ;
; 29.757 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[4]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.535      ;
; 29.761 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[8]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.531      ;
; 29.762 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[3]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.530      ;
; 29.767 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[6] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[14] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.525      ;
; 29.770 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[1]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.522      ;
; 29.770 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[6]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.522      ;
; 29.771 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[2]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.521      ;
; 29.772 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[11] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.520      ;
; 29.773 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[6] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[3]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.519      ;
; 29.773 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[10] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.519      ;
; 29.777 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[5]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.515      ;
; 29.779 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[9]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.513      ;
; 29.780 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[7]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.512      ;
; 29.781 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[6] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[6]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.511      ;
; 29.783 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[6] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[11] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.509      ;
; 29.784 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[6] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[10] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.508      ;
; 29.788 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[6] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[5]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.504      ;
; 29.788 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[4]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.504      ;
; 29.790 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[6] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[9]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.502      ;
; 29.791 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[6] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[7]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.501      ;
; 29.792 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[14] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.500      ;
; 29.792 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[8]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.500      ;
; 29.798 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[3]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.494      ;
; 29.801 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[1]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.491      ;
; 29.802 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[2]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.490      ;
; 29.806 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[7] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[13] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.009     ; 3.495      ;
; 29.806 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[6]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.486      ;
; 29.808 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[11] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.484      ;
; 29.809 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[10] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.483      ;
; 29.813 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[5]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.479      ;
; 29.815 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[9]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.477      ;
; 29.816 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[7]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.476      ;
; 29.833 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[0]      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.009     ; 3.468      ;
; 29.833 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[1]      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.009     ; 3.468      ;
; 29.858 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[0]      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.009     ; 3.443      ;
; 29.858 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[1]      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.009     ; 3.443      ;
; 29.871 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[4]      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.009     ; 3.430      ;
; 29.871 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[6]      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.009     ; 3.430      ;
; 29.885 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[13] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.009     ; 3.416      ;
; 29.890 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[4]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.402      ;
; 29.892 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[2]      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.010     ; 3.408      ;
; 29.894 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[8]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.398      ;
; 29.896 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[4]      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.009     ; 3.405      ;
; 29.896 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[6]      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.009     ; 3.405      ;
; 29.903 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[1]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.389      ;
; 29.904 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[2]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.388      ;
; 29.915 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[4]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.377      ;
; 29.916 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[13] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.009     ; 3.385      ;
; 29.917 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[2]      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.010     ; 3.383      ;
; 29.919 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[8]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.373      ;
; 29.921 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[7] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[12] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.009     ; 3.380      ;
; 29.926 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[6] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[4]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.366      ;
; 29.928 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[1]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.364      ;
; 29.929 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[2]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.363      ;
; 29.930 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[6] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[8]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.362      ;
; 29.931 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[0]      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.009     ; 3.370      ;
; 29.931 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[1]      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.009     ; 3.370      ;
; 29.939 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[6] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[1]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.353      ;
; 29.940 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[6] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[2]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.352      ;
; 29.943 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[0] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[14] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.349      ;
; 29.949 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[0] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[3]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.343      ;
; 29.951 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[4]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.341      ;
; 29.955 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1_3ms[8]  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 33.333       ; -0.018     ; 3.337      ;
+--------+-----------------------------------------------+---------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'altera_reserved_tck'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                        ; To Node                                                                                                                                                                                                               ; Launch Clock        ; Latch Clock         ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; 47.974 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.435      ; 2.448      ;
; 48.122 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                                                   ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.435      ; 2.300      ;
; 48.215 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.435      ; 2.207      ;
; 48.243 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]                                              ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.436      ; 2.180      ;
; 48.308 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.435      ; 2.114      ;
; 48.411 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.442      ; 2.018      ;
; 48.461 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.440      ; 1.966      ;
; 48.476 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2]                                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.438      ; 1.949      ;
; 48.489 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.438      ; 1.936      ;
; 48.494 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]                                              ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.441      ; 1.934      ;
; 48.536 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.440      ; 1.891      ;
; 48.700 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.440      ; 1.727      ;
; 48.729 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.438      ; 1.696      ;
; 48.826 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.437      ; 1.598      ;
; 48.840 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                                                   ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.439      ; 1.586      ;
; 48.870 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.437      ; 1.554      ;
; 48.957 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.439      ; 1.469      ;
; 48.966 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.437      ; 1.458      ;
; 49.217 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.440      ; 1.210      ;
; 49.254 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.435      ; 1.168      ;
; 49.368 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[0]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.440      ; 1.059      ;
; 49.389 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg                                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.439      ; 1.037      ;
; 49.550 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[0]                                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.439      ; 0.876      ;
; 49.623 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[0]                                                                                                                               ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.439      ; 0.803      ;
; 97.736 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.031     ; 2.220      ;
; 97.736 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.031     ; 2.220      ;
; 97.736 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.031     ; 2.220      ;
; 97.736 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.031     ; 2.220      ;
; 97.736 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.031     ; 2.220      ;
; 97.789 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.033     ; 2.165      ;
; 97.789 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[6]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.033     ; 2.165      ;
; 97.789 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[5]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.033     ; 2.165      ;
; 97.789 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.033     ; 2.165      ;
; 97.789 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.033     ; 2.165      ;
; 97.789 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.033     ; 2.165      ;
; 97.789 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.033     ; 2.165      ;
; 97.806 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.176     ; 2.005      ;
; 97.807 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.041     ; 2.139      ;
; 97.807 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.041     ; 2.139      ;
; 97.807 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.041     ; 2.139      ;
; 97.807 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.041     ; 2.139      ;
; 97.807 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.041     ; 2.139      ;
; 97.810 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.177     ; 2.000      ;
; 97.812 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.033     ; 2.142      ;
; 97.812 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.033     ; 2.142      ;
; 97.812 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.033     ; 2.142      ;
; 97.812 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.033     ; 2.142      ;
; 97.812 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.033     ; 2.142      ;
; 97.816 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3]                                                                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.039     ; 2.132      ;
; 97.816 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2]                                                                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.039     ; 2.132      ;
; 97.816 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1]                                                                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.039     ; 2.132      ;
; 97.816 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0]                                                                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.039     ; 2.132      ;
; 97.827 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.177     ; 1.983      ;
; 97.832 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.177     ; 1.978      ;
; 97.835 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 2.116      ;
; 97.835 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 2.116      ;
; 97.835 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 2.116      ;
; 97.835 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 2.116      ;
; 97.835 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 2.116      ;
; 97.862 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4]                                                                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.039     ; 2.086      ;
; 97.873 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.177     ; 1.937      ;
; 97.883 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.032     ; 2.072      ;
; 97.892 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[5]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.176     ; 1.919      ;
; 97.893 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.038     ; 2.056      ;
; 97.893 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[5]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.177     ; 1.917      ;
; 97.893 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0                                                                                                                                        ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.038     ; 2.056      ;
; 97.893 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 2.057      ;
; 97.893 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 2.057      ;
; 97.893 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 2.057      ;
; 97.893 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 2.057      ;
; 97.893 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 2.057      ;
; 97.902 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[6]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.177     ; 1.908      ;
; 97.907 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 2.043      ;
; 97.907 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 2.043      ;
; 97.907 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 2.043      ;
; 97.907 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 2.043      ;
; 97.912 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3]                                                                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.039     ; 2.036      ;
; 97.912 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2]                                                                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.039     ; 2.036      ;
; 97.912 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1]                                                                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.039     ; 2.036      ;
; 97.912 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0]                                                                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.039     ; 2.036      ;
; 97.917 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.176     ; 1.894      ;
; 97.921 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.177     ; 1.889      ;
; 97.928 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[3]      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 2.022      ;
; 97.928 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[2]      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 2.022      ;
; 97.928 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[1]      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 2.022      ;
; 97.928 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                                                                ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[0]      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 2.022      ;
; 97.951 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                                                                                                                                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.038     ; 1.998      ;
; 97.951 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                                                                                                                                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.038     ; 1.998      ;
; 97.951 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                                                                                                                                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.038     ; 1.998      ;
; 97.951 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                                                                                                                                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.038     ; 1.998      ;
; 97.951 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                                                                                                                                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.038     ; 1.998      ;
; 97.953 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[1]                                                                                                                 ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.041     ; 1.993      ;
; 97.953 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[2]                                                                                                                 ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.041     ; 1.993      ;
; 97.953 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[3]                                                                                                                 ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.041     ; 1.993      ;
; 97.953 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[4]                                                                                                                 ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.041     ; 1.993      ;
; 97.953 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[0]                                                                                                                 ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.041     ; 1.993      ;
; 97.958 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                        ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4]                                                                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.039     ; 1.990      ;
; 97.961 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[6]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.176     ; 1.850      ;
; 97.963 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.032     ; 1.992      ;
; 97.963 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.032     ; 1.992      ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3]'                                                                                                                                                             ;
+-------+---------------------------+---------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                 ; To Node                   ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------+---------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 0.141 ; svideo:svideo|luma[8]     ; svideo:svideo|luma_1[8]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.083      ; 0.326      ;
; 0.141 ; svideo:svideo|luma[9]     ; svideo:svideo|luma_1[9]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.083      ; 0.326      ;
; 0.195 ; svideo_yout_dly1[1]       ; svideo_yout_dly2[1]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; svideo_yout_dly1[3]       ; svideo_yout_dly2[3]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.314      ;
; 0.196 ; svideo_yout_dly1[4]       ; svideo_yout_dly2[4]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.315      ;
; 0.197 ; svideo:svideo|luma_1[9]   ; svideo:svideo|luma_2[9]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.316      ;
; 0.201 ; svideo:svideo|luma[5]     ; svideo:svideo|luma_1[5]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.082      ; 0.385      ;
; 0.210 ; svideo:svideo|luma[6]     ; svideo:svideo|luma_1[6]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.084      ; 0.396      ;
; 0.214 ; svideo:svideo|luma[7]     ; svideo:svideo|luma_1[7]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.083      ; 0.399      ;
; 0.215 ; svideo:svideo|luma[9]     ; luma_saturated[9]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.083      ; 0.400      ;
; 0.216 ; svideo:svideo|luma[4]     ; svideo:svideo|luma_1[4]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.083      ; 0.401      ;
; 0.217 ; svideo:svideo|luma[1]     ; svideo:svideo|luma_1[1]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.084      ; 0.403      ;
; 0.242 ; svideo:svideo|luma[2]     ; luma_saturated[2]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.084      ; 0.428      ;
; 0.244 ; svideo:svideo|luma[6]     ; luma_saturated[6]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.084      ; 0.430      ;
; 0.246 ; svideo:svideo|luma[0]     ; luma_saturated[1]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.084      ; 0.432      ;
; 0.247 ; svideo:svideo|luma[1]     ; luma_saturated[1]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.084      ; 0.433      ;
; 0.262 ; svideo:svideo|luma_acc[7] ; svideo_yout_dly1[5]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.382      ;
; 0.263 ; svideo:svideo|luma_1[3]   ; svideo:svideo|luma_2[3]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.382      ;
; 0.266 ; svideo:svideo|luma_1[0]   ; svideo:svideo|luma_2[0]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.385      ;
; 0.267 ; svideo:svideo|luma_1[4]   ; svideo:svideo|luma_2[4]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.386      ;
; 0.267 ; svideo:svideo|luma_1[8]   ; svideo:svideo|luma_2[8]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.386      ;
; 0.268 ; svideo_yout_dly1[5]       ; svideo_yout_dly2[5]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.387      ;
; 0.269 ; luma_saturated[9]         ; cvbs1_out[9]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.034      ; 0.387      ;
; 0.269 ; svideo_yout_dly1[6]       ; svideo_yout_dly2[6]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.388      ;
; 0.269 ; svideo_yout_dly1[2]       ; svideo_yout_dly2[2]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.388      ;
; 0.270 ; svideo:svideo|luma[0]     ; luma_saturated[0]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.084      ; 0.456      ;
; 0.271 ; svideo_yout_dly1[7]       ; svideo_yout_dly2[7]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.390      ;
; 0.271 ; svideo_yout_dly1[0]       ; svideo_yout_dly2[0]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.390      ;
; 0.272 ; svideo:svideo|luma_1[7]   ; svideo:svideo|luma_2[7]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.391      ;
; 0.272 ; svideo:svideo|luma_acc[8] ; svideo_yout_dly1[6]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.392      ;
; 0.273 ; svideo:svideo|luma_1[6]   ; svideo:svideo|luma_2[6]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.392      ;
; 0.275 ; svideo:svideo|luma_1[2]   ; svideo:svideo|luma_2[2]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.394      ;
; 0.285 ; svideo:svideo|luma[0]     ; svideo:svideo|luma_1[0]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.084      ; 0.471      ;
; 0.296 ; svideo:svideo|luma[2]     ; svideo:svideo|luma_1[2]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.084      ; 0.482      ;
; 0.297 ; svideo:svideo|luma_acc[1] ; svideo:svideo|luma_acc[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.416      ;
; 0.297 ; svideo:svideo|luma_2[7]   ; svideo:svideo|luma_acc[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.416      ;
; 0.297 ; svideo:svideo|luma_2[6]   ; svideo:svideo|luma_acc[6] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.416      ;
; 0.298 ; svideo:svideo|luma_2[4]   ; svideo:svideo|luma_acc[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.417      ;
; 0.298 ; svideo:svideo|luma_2[2]   ; svideo:svideo|luma_acc[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.417      ;
; 0.301 ; svideo:svideo|luma_acc[0] ; svideo:svideo|luma_acc[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.420      ;
; 0.304 ; svideo:svideo|luma[5]     ; luma_saturated[5]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.082      ; 0.488      ;
; 0.305 ; svideo:svideo|luma[4]     ; luma_saturated[4]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.083      ; 0.490      ;
; 0.305 ; svideo:svideo|luma_2[0]   ; svideo:svideo|luma_acc[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.424      ;
; 0.308 ; svideo:svideo|luma[7]     ; luma_saturated[7]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.083      ; 0.493      ;
; 0.310 ; svideo:svideo|luma[8]     ; luma_saturated[8]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.083      ; 0.495      ;
; 0.335 ; svideo:svideo|luma_acc[9] ; svideo_yout_dly1[7]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.455      ;
; 0.337 ; svideo:svideo|luma_acc[4] ; svideo_yout_dly1[2]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.457      ;
; 0.348 ; svideo:svideo|luma_acc[6] ; svideo_yout_dly1[4]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.468      ;
; 0.348 ; svideo:svideo|luma_acc[5] ; svideo_yout_dly1[3]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.468      ;
; 0.349 ; svideo:svideo|luma_acc[3] ; svideo_yout_dly1[1]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.469      ;
; 0.350 ; svideo:svideo|luma_1[1]   ; svideo:svideo|luma_2[1]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.469      ;
; 0.355 ; svideo:svideo|luma_1[5]   ; svideo:svideo|luma_2[5]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.474      ;
; 0.362 ; luma_saturated[6]         ; cvbs1_out[6]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.034      ; 0.480      ;
; 0.362 ; luma_saturated[4]         ; cvbs1_out[4]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.034      ; 0.480      ;
; 0.362 ; svideo:svideo|luma_acc[2] ; svideo_yout_dly1[0]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.036      ; 0.482      ;
; 0.364 ; svideo:svideo|luma_2[3]   ; svideo:svideo|luma_acc[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.483      ;
; 0.365 ; luma_saturated[3]         ; cvbs1_out[3]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.034      ; 0.483      ;
; 0.367 ; svideo:svideo|luma_2[1]   ; svideo:svideo|luma_acc[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.486      ;
; 0.378 ; luma_saturated[7]         ; cvbs1_out[7]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.034      ; 0.496      ;
; 0.378 ; luma_saturated[8]         ; cvbs1_out[8]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.034      ; 0.496      ;
; 0.378 ; luma_saturated[5]         ; cvbs1_out[5]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.034      ; 0.496      ;
; 0.381 ; svideo:svideo|luma_2[5]   ; svideo:svideo|luma_acc[5] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.500      ;
; 0.383 ; svideo:svideo|luma_2[8]   ; svideo:svideo|luma_acc[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.502      ;
; 0.384 ; svideo:svideo|luma_2[9]   ; svideo:svideo|luma_acc[9] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.503      ;
; 0.391 ; svideo:svideo|luma[2]     ; luma_saturated[3]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.084      ; 0.577      ;
; 0.392 ; svideo:svideo|luma[6]     ; luma_saturated[7]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.084      ; 0.578      ;
; 0.398 ; svideo:svideo|luma[0]     ; luma_saturated[2]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.084      ; 0.584      ;
; 0.400 ; svideo:svideo|luma[1]     ; luma_saturated[2]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.084      ; 0.586      ;
; 0.401 ; svideo:svideo|luma[0]     ; luma_saturated[3]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.084      ; 0.587      ;
; 0.403 ; svideo:svideo|luma[1]     ; luma_saturated[3]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.084      ; 0.589      ;
; 0.428 ; svideo:svideo|luma[3]     ; svideo:svideo|luma_1[3]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.082      ; 0.612      ;
; 0.436 ; svideo:svideo|chroma[6]   ; cvbs1_out[6]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.081      ; 0.619      ;
; 0.445 ; svideo:svideo|luma_acc[1] ; svideo:svideo|luma_acc[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.564      ;
; 0.446 ; svideo:svideo|chroma[5]   ; cvbs1_out[5]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.081      ; 0.629      ;
; 0.446 ; svideo:svideo|luma_2[7]   ; svideo:svideo|luma_acc[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.565      ;
; 0.448 ; svideo:svideo|chroma[4]   ; cvbs1_out[4]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.081      ; 0.631      ;
; 0.452 ; svideo:svideo|chroma[2]   ; cvbs1_out[2]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.081      ; 0.635      ;
; 0.454 ; svideo:svideo|luma[4]     ; luma_saturated[5]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.083      ; 0.639      ;
; 0.454 ; svideo:svideo|luma[2]     ; luma_saturated[4]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.084      ; 0.640      ;
; 0.454 ; svideo:svideo|luma_acc[0] ; svideo:svideo|luma_acc[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.573      ;
; 0.455 ; svideo:svideo|luma[6]     ; luma_saturated[8]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.084      ; 0.641      ;
; 0.455 ; svideo:svideo|luma_2[6]   ; svideo:svideo|luma_acc[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.574      ;
; 0.456 ; svideo:svideo|luma_2[2]   ; svideo:svideo|luma_acc[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.575      ;
; 0.456 ; svideo:svideo|luma_2[4]   ; svideo:svideo|luma_acc[5] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.575      ;
; 0.457 ; svideo:svideo|luma[2]     ; luma_saturated[5]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.084      ; 0.643      ;
; 0.457 ; svideo:svideo|luma_acc[0] ; svideo:svideo|luma_acc[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.576      ;
; 0.457 ; svideo:svideo|luma_2[0]   ; svideo:svideo|luma_acc[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.576      ;
; 0.458 ; svideo:svideo|luma[8]     ; luma_saturated[9]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.083      ; 0.643      ;
; 0.458 ; svideo:svideo|luma[6]     ; luma_saturated[9]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.084      ; 0.644      ;
; 0.458 ; svideo:svideo|luma_2[6]   ; svideo:svideo|luma_acc[8] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.577      ;
; 0.459 ; luma_saturated[2]         ; cvbs1_out[2]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.034      ; 0.577      ;
; 0.459 ; svideo:svideo|luma_2[4]   ; svideo:svideo|luma_acc[6] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.578      ;
; 0.459 ; svideo:svideo|luma_2[2]   ; svideo:svideo|luma_acc[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.578      ;
; 0.460 ; svideo:svideo|luma[3]     ; luma_saturated[3]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.082      ; 0.644      ;
; 0.460 ; svideo:svideo|luma_2[0]   ; svideo:svideo|luma_acc[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000        ; 0.035      ; 0.579      ;
; 0.463 ; svideo:svideo|luma[5]     ; luma_saturated[6]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.082      ; 0.647      ;
; 0.464 ; svideo:svideo|luma[0]     ; luma_saturated[4]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.084      ; 0.650      ;
; 0.465 ; svideo:svideo|chroma[3]   ; cvbs1_out[3]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.081      ; 0.648      ;
; 0.466 ; svideo:svideo|luma[5]     ; luma_saturated[7]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.082      ; 0.650      ;
; 0.466 ; svideo:svideo|luma[1]     ; luma_saturated[4]         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; -0.002       ; 0.084      ; 0.652      ;
+-------+---------------------------+---------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                       ; To Node                                                                                                                                                                                                                                   ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 0.159 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_raw_reg[5]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a8~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.483      ;
; 0.160 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|sizep0_raw_reg[0]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a0~porta_datain_reg0     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.484      ;
; 0.164 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|cntr_pqf:cntr1|counter_reg_bit[4] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a0~portb_address_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.491      ;
; 0.165 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|cntr_pqf:cntr1|counter_reg_bit[4] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a0~porta_address_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.490      ;
; 0.165 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|sizep0_raw_reg[1]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a0~porta_datain_reg0     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.489      ;
; 0.166 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_raw_reg[6]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a8~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.489      ;
; 0.166 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_raw_reg[4]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a8~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.489      ;
; 0.168 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|cntr_pqf:cntr1|counter_reg_bit[3] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a0~portb_address_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.495      ;
; 0.168 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_raw_reg[7]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.491      ;
; 0.169 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|cntr_pqf:cntr1|counter_reg_bit[3] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a0~porta_address_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.494      ;
; 0.170 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_raw_reg[5]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.493      ;
; 0.171 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_raw_reg[3]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.494      ;
; 0.171 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|sizem_raw_reg[5]                                                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a0~porta_datain_reg0     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.218      ; 0.493      ;
; 0.172 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[7]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.218      ; 0.494      ;
; 0.172 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_raw_reg[1]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a8~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.495      ;
; 0.174 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp0_raw_reg[0]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.216      ; 0.494      ;
; 0.174 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_raw_reg[0]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a8~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.498      ;
; 0.175 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[1]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.499      ;
; 0.175 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_raw_reg[0]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a8~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.499      ;
; 0.175 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|sizem_raw_reg[4]                                                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a0~porta_datain_reg0     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.218      ; 0.497      ;
; 0.176 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_raw_reg[4]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.499      ;
; 0.176 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_raw_reg[3]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.218      ; 0.498      ;
; 0.177 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_raw_reg[3]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a8~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.501      ;
; 0.178 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[4]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.218      ; 0.500      ;
; 0.179 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_raw_reg[1]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.502      ;
; 0.179 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_raw_reg[2]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a8~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.502      ;
; 0.179 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_raw_reg[6]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a8~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.218      ; 0.501      ;
; 0.180 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[2]                                                                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[2]                                                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.043      ; 0.307      ;
; 0.180 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[6]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.218      ; 0.502      ;
; 0.180 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_raw_reg[1]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a8~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.503      ;
; 0.180 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|sizem_raw_reg[1]                                                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a0~porta_datain_reg0     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.218      ; 0.502      ;
; 0.181 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_raw_reg[7]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a8~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.504      ;
; 0.182 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|cntr_qqf:cntr1|counter_reg_bit[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a0~portb_address_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.506      ;
; 0.182 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|cntr_6pf:cntr1|counter_reg_bit[1]   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~portb_address_reg0   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.505      ;
; 0.182 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_raw_reg[6]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.505      ;
; 0.182 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_raw_reg[0]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.218      ; 0.504      ;
; 0.183 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|cntr_qqf:cntr1|counter_reg_bit[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a0~porta_address_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.218      ; 0.505      ;
; 0.183 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|cntr_6pf:cntr1|counter_reg_bit[1]   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_address_reg0   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.217      ; 0.504      ;
; 0.183 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_raw_reg[7]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.218      ; 0.505      ;
; 0.183 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_raw_reg[2]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.218      ; 0.505      ;
; 0.183 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_raw_reg[7]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a8~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.218      ; 0.505      ;
; 0.185 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[5]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.218      ; 0.507      ;
; 0.185 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_raw_reg[3]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a8~porta_datain_reg0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.218      ; 0.507      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|cntr_qqf:cntr1|counter_reg_bit[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a0~portb_address_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.510      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|cntr_qqf:cntr1|counter_reg_bit[3] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a0~portb_address_reg0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.510      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[22]                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[22]                                                                                                                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_load2                                                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_load2                                                                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[30]                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[30]                                                                                                                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[14]                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[14]                                                                                                                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[18]                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[18]                                                                                                                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[19]                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[19]                                                                                                                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[25]                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[25]                                                                                                                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|skctl_reg[1]                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|skctl_reg[1]                                                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[0]                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[0]                                                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[3]                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[3]                                                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[4]                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[4]                                                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[5]                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[5]                                                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[6]                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[6]                                                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[7]                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[7]                                                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer2|delay_line:underflow0_delay|shift_reg[0]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer2|delay_line:underflow0_delay|shift_reg[0]                                                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[2]                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[2]                                                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[3]                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[3]                                                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[6]                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[6]                                                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[4]                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[4]                                                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[5]                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[5]                                                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[7]                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[7]                                                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer3|delay_line:underflow0_delay|shift_reg[0]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer3|delay_line:underflow0_delay|shift_reg[0]                                                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[8]                                                                                                                                                                 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[8]                                                                                                                                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[26]                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[26]                                                                                                                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[23]                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[23]                                                                                                                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[6]                                                                                                                                                    ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[6]                                                                                                                                                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[10]                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[10]                                                                                                                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[12]                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[12]                                                                                                                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[15]                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[15]                                                                                                                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[27]                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[27]                                                                                                                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[24]                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[24]                                                                                                                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_reg                                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_reg                                                                                                                                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|spi_speed_reg[7]                                                                                                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|spi_speed_reg[7]                                                                                                                                                                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|assert_data                                                                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|assert_data                                                                                                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pot_reset_reg                                                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pot_reset_reg                                                                                                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[16]                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[16]                                                                                                                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[7]                                                                                                                                                    ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[7]                                                                                                                                                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serial_ip_framing_reg                                                                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serial_ip_framing_reg                                                                                                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[31]                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[31]                                                                                                                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_fetch                                                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_fetch                                                                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|irqst_reg[5]                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|irqst_reg[5]                                                                                                                                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serial_ip_overrun_reg                                                                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serial_ip_overrun_reg                                                                                                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[1]                                                                                                                                                    ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[1]                                                                                                                                                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[0]                                                                                                                                                    ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[0]                                                                                                                                                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_loadb2                                                                                                                                           ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_loadb2                                                                                                                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[0]                                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[0]                                                                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[1]                                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[1]                                                                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[2]                                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[2]                                                                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[3]                                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[3]                                                                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[5]                                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[5]                                                                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[6]                                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[6]                                                                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[7]                                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[7]                                                                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[4]                                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[4]                                                                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Creg                                                                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Creg                                                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|serin_bitcount_reg[1]                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|serin_bitcount_reg[1]                                                                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'mcc_pll3|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                        ;
+-------+---------------------------------------------------------------------+---------------------------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                           ; To Node                                                             ; Launch Clock                                         ; Latch Clock                                          ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------+---------------------------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.end_set_idle            ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.end_set_idle            ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|set_command[1]                     ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|set_command[1]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.end_set_address         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.end_set_address         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|set_command[0]                     ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|set_command[0]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.end_set_configuration   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.end_set_configuration   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|start_sendcom                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|start_sendcom                      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|address_start[0]                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|address_start[0]                   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|address_start[2]                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|address_start[2]                   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|address_start[4]                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|address_start[4]                   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|address_start[5]                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|address_start[5]                   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|address_start[7]                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|address_start[7]                   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|detach_ack                         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|detach_ack                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait2                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait2                   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.setaddress_sendpkt3_end ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.setaddress_sendpkt3_end ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_pktin3             ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_pktin3             ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait6                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait6                   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.send_ack_end            ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.send_ack_end            ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.usb_reset_1ms_start     ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.usb_reset_1ms_start     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait1                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait1                   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.start_get_data          ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.start_get_data          ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte2         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte2         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte3         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte3         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte4         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte4         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte5         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte5         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte6         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte6         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte7         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte7         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte8         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte8         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte9         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte9         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte10        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte10        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|read_byte_valid_c                  ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|read_byte_valid_c                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte11        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_read_byte11        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait40                  ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait40                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.send_getreport_ack_end  ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.send_getreport_ack_end  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter2[2]                        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter2[2]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.usb_reset_1ms_wait1     ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.usb_reset_1ms_wait1     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.getreport_sendpkt1_end  ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.getreport_sendpkt1_end  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait30                  ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait30                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait20                  ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait20                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait21                  ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait21                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait4                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait4                   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter2[1]                        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter2[1]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.setaddress_sendpkt1_end ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.setaddress_sendpkt1_end ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[2]                        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|counter1[2]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_for_deviceconnect  ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.wait_for_deviceconnect  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.usb_reset_state         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_manage.usb_reset_state         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_available                     ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_available                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_valid                         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_valid                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.start_get_data          ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.start_get_data          ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte2         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte2         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte3         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte3         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte4         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte4         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte5         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte5         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte6         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte6         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte7         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte7         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte8         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte8         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte9         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte9         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte10        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte10        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|read_byte_valid_c                  ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|read_byte_valid_c                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte11        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte11        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.Idle                    ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.Idle                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|set_command[0]                     ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|set_command[0]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.end_set_address         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.end_set_address         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait4                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait4                   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.setaddress_sendpkt3_end ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.setaddress_sendpkt3_end ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_pktin2             ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_pktin2             ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.end_set_configuration   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.end_set_configuration   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|set_command[1]                     ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|set_command[1]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.end_set_idle            ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.end_set_idle            ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.getreport_sendpkt1_end  ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.getreport_sendpkt1_end  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait40                  ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait40                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_for_deviceconnect  ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_for_deviceconnect  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_start[0]                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_start[0]                   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_start[2]                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_start[2]                   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_start[5]                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_start[5]                   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_start[7]                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_start[7]                   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.185 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_valid_temp                    ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_valid_temp                    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.307      ;
; 0.186 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait2                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait2                   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.setaddress_sendpkt2_end ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.setaddress_sendpkt2_end ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.setaddress_sendpkt1_end ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.setaddress_sendpkt1_end ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait1                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait1                   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.usb_reset_1ms_start     ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.usb_reset_1ms_start     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter2[2]                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter2[2]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter2[1]                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter2[1]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait6                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait6                   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait30                  ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait30                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|detach_ack                         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|detach_ack                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.send_getreport_ack_end  ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.send_getreport_ack_end  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait20                  ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait20                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[2]                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[2]                        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.usb_reset_state         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.usb_reset_state         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|start_sendcom                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|start_sendcom                      ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_start[4]                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_start[4]                   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_available                     ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_available                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_valid                         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_valid                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|joyright_temp[3]                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|joyright_temp[3]                   ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.187 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_send_com.Idle                  ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_send_com.Idle                  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_send_com.reset_start           ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb_send_com.reset_start           ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|send_frame                         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|send_frame                         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[3]                     ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[3]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[2]                     ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_tosend[2]                     ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+-------+---------------------------------------------------------------------+---------------------------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'altera_reserved_tck'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                             ; To Node                                                                                                                                                                                                               ; Launch Clock        ; Latch Clock         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; 0.187 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0]                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1]                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11]                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11]                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1]                                                                                                                                         ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1]                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2]                                                                                                                                         ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2]                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                             ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2]                                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]                                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4]                                                                                                                                             ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4]                                                                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0]                                                                                                                                         ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0]                                                                                                                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg                                                         ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg                                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg                                                         ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg                                                         ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg                                                                                                                                          ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg                                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13]                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13]                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.307      ;
; 0.188 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1]                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1]                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2]                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2]                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6]                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2]                                        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]                                        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                                                        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[1] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[1] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                                                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.307      ;
; 0.193 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][2]                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.313      ;
; 0.194 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[3]                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[2]                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.313      ;
; 0.194 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2]                                                                                                                                         ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                                                                                                                                                 ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3]                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0]                                                                                                                           ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[0]                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.314      ;
; 0.195 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0]                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0]                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0]                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3]                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1]                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2]                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[0] ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[0] ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[1]      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[0]      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.314      ;
; 0.196 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[2]                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[1]                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.315      ;
; 0.196 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[1]                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[0]                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.315      ;
; 0.196 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][1]                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.316      ;
; 0.196 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0]                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.315      ;
; 0.197 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][4]                                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.317      ;
; 0.197 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[3]                                                                                                                           ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[2]                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.317      ;
; 0.197 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13]                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[14]                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.317      ;
; 0.197 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0]                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1]                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.316      ;
; 0.198 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8]                                                                                                                                          ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7]                                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.318      ;
; 0.198 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2]                                                                                                                                          ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1]                                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.318      ;
; 0.198 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1]                                                                                                                           ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0]                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.318      ;
; 0.198 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[12]                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13]                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.318      ;
; 0.199 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[3]                                                                                                                           ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[3]                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.319      ;
; 0.199 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[2]                                                                                                                           ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1]                                                                                                                           ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.319      ;
; 0.199 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1]                                                                                                                           ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[1]                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.319      ;
; 0.199 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[10]                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[12]                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.319      ;
; 0.199 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0]                                                                                                                    ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2]                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.318      ;
; 0.200 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7]                                                                                                                                          ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6]                                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.320      ;
; 0.200 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[2]                                                                                                                           ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[2]                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.320      ;
; 0.200 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[14]                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11]                                                                                                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.320      ;
; 0.201 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6]                                                                                                                                          ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5]                                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.321      ;
; 0.202 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3]                                                                                                                                          ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2]                                                                                                                                          ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.322      ;
; 0.204 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7]                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.323      ;
; 0.205 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                                                                                           ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3]                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.325      ;
; 0.205 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.325      ;
; 0.205 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]                                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.325      ;
; 0.206 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.325      ;
; 0.206 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.325      ;
; 0.207 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                                                                                           ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1]                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.326      ;
; 0.207 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2]                                                                                                                                           ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2]                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.326      ;
; 0.207 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                                                                                           ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0]                                                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.326      ;
; 0.207 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.326      ;
; 0.208 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[6]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[5]                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.328      ;
; 0.208 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.327      ;
; 0.209 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.328      ;
; 0.210 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[15]                                                                                                                     ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[2]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.330      ;
; 0.211 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[4]                                                                                                                 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[4]                                                                                                                 ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.331      ;
; 0.211 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0]                                                                                                                      ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1]                                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.331      ;
; 0.212 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]                                        ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.332      ;
; 0.214 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_datain_reg0                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.180      ; 0.498      ;
; 0.218 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_datain_reg0                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.180      ; 0.502      ;
; 0.220 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_datain_reg0                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.180      ; 0.504      ;
; 0.220 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]                                        ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                        ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.339      ;
; 0.222 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_datain_reg0                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.180      ; 0.506      ;
; 0.224 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[6]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.177      ; 0.505      ;
; 0.224 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_datain_reg0                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.180      ; 0.508      ;
; 0.225 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.176      ; 0.505      ;
; 0.226 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.177      ; 0.507      ;
; 0.228 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.177      ; 0.509      ;
; 0.229 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_datain_reg0                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.179      ; 0.512      ;
; 0.232 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.177      ; 0.513      ;
; 0.233 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.176      ; 0.513      ;
; 0.235 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.177      ; 0.516      ;
; 0.235 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_datain_reg0                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.180      ; 0.519      ;
; 0.235 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.176      ; 0.515      ;
; 0.237 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.177      ; 0.518      ;
; 0.238 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_datain_reg0                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.179      ; 0.521      ;
; 0.239 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.176      ; 0.519      ;
; 0.239 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.176      ; 0.519      ;
; 0.240 ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]                                                   ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.177      ; 0.521      ;
; 0.241 ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]                                                   ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.176      ; 0.521      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                               ;
+-------+-----------------------------------------------------------------------------------------------------------------+-------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                       ; To Node                                               ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------+-------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 0.188 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                                      ; sdram_ctrl:sdram_controller|r_init_tmr[10]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[0]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                           ; sdram_ctrl:sdram_controller|sdram_rdy                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_wr_act                                                                            ; sdram_ctrl:sdram_controller|r_wr_act                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                                                                        ; sdram_ctrl:sdram_controller|r_bst_stp[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_rd_bctr[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_rd_act                                                                            ; sdram_ctrl:sdram_controller|r_rd_act                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_refr_act                                                                          ; sdram_ctrl:sdram_controller|r_refr_act                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.195 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[0]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.314      ;
; 0.261 ; sdram_ctrl:sdram_controller|r_rd_act                                                                            ; sdram_ctrl:sdram_controller|ap1_rd_bst_act            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.380      ;
; 0.261 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_rd_act                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.380      ;
; 0.261 ; sdram_ctrl:sdram_controller|r_psel_dly[0]                                                                       ; sdram_ctrl:sdram_controller|ap1_rd_bst_act            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.380      ;
; 0.271 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[23] ; ram_di_reg[7]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 0.458      ;
; 0.271 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[25] ; ram_di_reg[9]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 0.457      ;
; 0.273 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[21] ; ram_di_reg[5]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 0.460      ;
; 0.274 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[16] ; ram_di_reg[0]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 0.461      ;
; 0.275 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[18] ; ram_di_reg[2]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 0.461      ;
; 0.284 ; seq_reg[6]                                                                                                      ; seq_reg[7]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.403      ;
; 0.284 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_wr_act                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.403      ;
; 0.287 ; seq_reg[11]                                                                                                     ; sdram_ctrl:sdram_controller|r_init_fsm[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.406      ;
; 0.288 ; seq_reg[4]                                                                                                      ; seq_reg[5]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.407      ;
; 0.288 ; seq_reg[9]                                                                                                      ; seq_reg[10]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.408      ;
; 0.288 ; seq_reg[11]                                                                                                     ; sdram_ctrl:sdram_controller|r_init_fsm[0]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.407      ;
; 0.289 ; seq_reg[5]                                                                                                      ; seq_reg[6]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.408      ;
; 0.294 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.413      ;
; 0.295 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.414      ;
; 0.295 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.414      ;
; 0.296 ; seq_reg[1]                                                                                                      ; seq_reg[2]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.415      ;
; 0.296 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.415      ;
; 0.296 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.415      ;
; 0.296 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.415      ;
; 0.296 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                                                                        ; sdram_ctrl:sdram_controller|r_rd_bctr[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.415      ;
; 0.297 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.416      ;
; 0.297 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.416      ;
; 0.301 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.420      ;
; 0.302 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.421      ;
; 0.325 ; sdram_ctrl:sdram_controller|r_rd_act                                                                            ; sdram_ctrl:sdram_controller|r_rd_bctr[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.444      ;
; 0.330 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[24] ; ram_di_reg[8]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 0.517      ;
; 0.345 ; sdram_ctrl:sdram_controller|r_refr_act                                                                          ; sdram_ctrl:sdram_controller|r_rd_reg                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.464      ;
; 0.348 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[1]  ; ram_di_reg[1]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 0.534      ;
; 0.350 ; seq_reg[10]                                                                                                     ; seq_reg[11]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.469      ;
; 0.351 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.470      ;
; 0.354 ; sdram_ctrl:sdram_controller|r_refr_act                                                                          ; sdram_ctrl:sdram_controller|r_wr_reg                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.473      ;
; 0.358 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[0]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.477      ;
; 0.373 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[20] ; ram_di_reg[4]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 0.560      ;
; 0.373 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[22] ; ram_di_reg[6]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 0.559      ;
; 0.373 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[31] ; ram_di_reg[15]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 0.560      ;
; 0.374 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[26] ; ram_di_reg[10]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 0.560      ;
; 0.374 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[27] ; ram_di_reg[11]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 0.560      ;
; 0.374 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[30] ; ram_di_reg[14]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 0.560      ;
; 0.375 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[17] ; ram_di_reg[1]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 0.561      ;
; 0.379 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[19] ; ram_di_reg[3]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 0.566      ;
; 0.380 ; seq_reg[7]                                                                                                      ; seq_reg[8]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.499      ;
; 0.380 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[28] ; ram_di_reg[12]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 0.567      ;
; 0.380 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[29] ; ram_di_reg[13]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 0.567      ;
; 0.398 ; seq_reg[10]                                                                                                     ; sdram_ctrl:sdram_controller|sdram_rdy                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.517      ;
; 0.405 ; sdram_ctrl:sdram_controller|r_rd_reg                                                                            ; sdram_ctrl:sdram_controller|r_rd_act                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.525      ;
; 0.409 ; seq_reg[11]                                                                                                     ; sdram_ctrl:sdram_controller|r_init_fsm[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.528      ;
; 0.416 ; sdram_ctrl:sdram_controller|r_wr_act                                                                            ; sdram_ctrl:sdram_controller|r_wr_bctr[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.535      ;
; 0.421 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[2]  ; ram_di_reg[2]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 0.607      ;
; 0.423 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[15] ; ram_di_reg[15]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 0.610      ;
; 0.424 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[12] ; ram_di_reg[12]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 0.611      ;
; 0.425 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[8]  ; ram_di_reg[8]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 0.612      ;
; 0.425 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[13] ; ram_di_reg[13]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 0.612      ;
; 0.443 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.562      ;
; 0.444 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.563      ;
; 0.444 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.563      ;
; 0.445 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.564      ;
; 0.451 ; seq_reg[8]                                                                                                      ; seq_reg[9]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.571      ;
; 0.452 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                                       ; sdram_ctrl:sdram_controller|sdram_rdy                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.571      ;
; 0.453 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.572      ;
; 0.454 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.573      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.574      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.574      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.574      ;
; 0.456 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.575      ;
; 0.457 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.576      ;
; 0.458 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.577      ;
; 0.458 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.577      ;
; 0.458 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.577      ;
; 0.474 ; seq_reg[2]                                                                                                      ; seq_reg[3]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.593      ;
; 0.484 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg          ; sdram_ctrl:sdram_controller|r_refr_req                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 0.676      ;
; 0.487 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[9]  ; ram_di_reg[9]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 0.673      ;
; 0.492 ; sdram_ctrl:sdram_controller|r_refr_req                                                                          ; sdram_ctrl:sdram_controller|r_rd_reg                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.612      ;
; 0.492 ; sdram_ctrl:sdram_controller|r_refr_req                                                                          ; sdram_ctrl:sdram_controller|r_wr_reg                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.612      ;
; 0.494 ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1                                                           ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.613      ;
; 0.495 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.614      ;
; 0.503 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                                                                       ; sdram_ctrl:sdram_controller|sdram_rdy                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.622      ;
; 0.507 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.626      ;
; 0.507 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.626      ;
; 0.508 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.627      ;
; 0.510 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.629      ;
; 0.510 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.629      ;
; 0.511 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.630      ;
; 0.519 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.638      ;
; 0.520 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.639      ;
; 0.521 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.640      ;
; 0.521 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.640      ;
+-------+-----------------------------------------------------------------------------------------------------------------+-------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                          ;
+-------+---------------------------------------+------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                                                                                        ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 9.208 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[13]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.090     ; 2.437      ;
; 9.208 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_8BIT_WRITE_ENABLE_reg                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.090     ; 2.437      ;
; 9.208 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_READ_reg                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.090     ; 2.437      ;
; 9.211 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[8]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.099     ; 2.425      ;
; 9.211 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[10]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.099     ; 2.425      ;
; 9.211 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[9]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.099     ; 2.425      ;
; 9.211 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[1]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.099     ; 2.425      ;
; 9.222 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[14]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 2.424      ;
; 9.222 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[15]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 2.424      ;
; 9.228 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 2.423      ;
; 9.231 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[11]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 2.420      ;
; 9.396 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[22]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; 0.103      ; 2.442      ;
; 9.396 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[23]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; 0.103      ; 2.442      ;
; 9.396 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[1]                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; 0.083      ; 2.422      ;
; 9.396 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[18]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; 0.103      ; 2.442      ;
; 9.396 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[19]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; 0.103      ; 2.442      ;
; 9.396 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[0]                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; 0.083      ; 2.422      ;
; 9.396 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[20]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; 0.103      ; 2.442      ;
; 9.396 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[21]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; 0.103      ; 2.442      ;
; 9.402 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[3]                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 2.250      ;
; 9.402 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[18]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 2.249      ;
; 9.402 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[17]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 2.249      ;
; 9.402 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[21]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 2.249      ;
; 9.402 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[22]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 2.249      ;
; 9.402 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[20]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 2.249      ;
; 9.402 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[19]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 2.249      ;
; 9.403 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[14]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.092     ; 2.240      ;
; 9.403 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[8]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.092     ; 2.240      ;
; 9.403 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[11]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.092     ; 2.240      ;
; 9.403 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[10]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.092     ; 2.240      ;
; 9.403 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[9]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.092     ; 2.240      ;
; 9.403 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[6]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.093     ; 2.239      ;
; 9.403 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[13]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.092     ; 2.240      ;
; 9.403 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[12]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.092     ; 2.240      ;
; 9.403 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[3]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.090     ; 2.242      ;
; 9.403 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[0]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.090     ; 2.242      ;
; 9.403 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[2]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.090     ; 2.242      ;
; 9.403 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[1]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.090     ; 2.242      ;
; 9.403 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[16]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.090     ; 2.242      ;
; 9.403 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[17]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.090     ; 2.242      ;
; 9.404 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[15]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.093     ; 2.238      ;
; 9.404 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[5]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.093     ; 2.238      ;
; 9.405 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[11]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.090     ; 2.240      ;
; 9.405 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.090     ; 2.240      ;
; 9.405 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.090     ; 2.240      ;
; 9.405 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|memory_ready_reg                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.090     ; 2.240      ;
; 9.406 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[6]                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 2.234      ;
; 9.406 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[12]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 2.240      ;
; 9.407 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[8]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.090     ; 2.238      ;
; 9.407 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[9]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.090     ; 2.238      ;
; 9.407 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[9]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.090     ; 2.238      ;
; 9.408 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[14]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 2.244      ;
; 9.409 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[0]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 2.231      ;
; 9.409 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[2]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 2.231      ;
; 9.409 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[3]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 2.231      ;
; 9.409 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[1]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 2.231      ;
; 9.409 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[0]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 2.231      ;
; 9.409 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 2.238      ;
; 9.409 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 2.238      ;
; 9.409 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[2]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 2.238      ;
; 9.409 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 2.238      ;
; 9.409 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[3]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 2.238      ;
; 9.409 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 2.238      ;
; 9.409 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[6]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 2.238      ;
; 9.409 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[4]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 2.238      ;
; 9.409 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 2.238      ;
; 9.409 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[5]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 2.238      ;
; 9.409 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[5] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 2.238      ;
; 9.409 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[6] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 2.238      ;
; 9.409 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[7]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 2.238      ;
; 9.409 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[7] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 2.238      ;
; 9.409 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_clock_last_reg                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 2.232      ;
; 9.409 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_holding_full_reg                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 2.232      ;
; 9.409 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_holding_reg[2]                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 2.231      ;
; 9.409 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_holding_reg[3]                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 2.231      ;
; 9.409 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_holding_reg[4]                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 2.231      ;
; 9.409 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_holding_reg[5]                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 2.231      ;
; 9.409 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_holding_reg[6]                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 2.231      ;
; 9.409 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_shift_reg[9]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 2.232      ;
; 9.409 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_holding_reg[7]                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 2.231      ;
; 9.409 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_shift_reg[8]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 2.232      ;
; 9.409 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_shift_reg[7]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 2.232      ;
; 9.409 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_shift_reg[6]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 2.232      ;
; 9.409 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_shift_reg[5]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 2.232      ;
; 9.409 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_shift_reg[4]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 2.232      ;
; 9.409 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_shift_reg[3]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 2.232      ;
; 9.409 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_holding_reg[1]                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 2.231      ;
; 9.409 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_shift_reg[2]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 2.232      ;
; 9.409 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_holding_reg[0]                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 2.231      ;
; 9.409 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_shift_reg[1]                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 2.232      ;
; 9.409 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_active_reg                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 2.232      ;
; 9.409 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serial_out_reg                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 2.232      ;
; 9.409 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|twotone_reg                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 2.232      ;
; 9.409 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|sio_out_reg                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 2.232      ;
; 9.409 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|ss_n[0]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 2.237      ;
; 9.409 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|state                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 2.237      ;
; 9.409 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|irqst_reg[3]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 2.231      ;
; 9.409 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|irqst_reg[4]                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 2.232      ;
; 9.409 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|mosi~en                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 2.237      ;
; 9.410 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|delay_line:stimer_delay|shift_reg[1]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.091     ; 2.234      ;
+-------+---------------------------------------+------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                         ;
+-------+------------------------+----------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                      ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+----------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 9.725 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.142     ; 1.817      ;
; 9.755 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.828      ;
; 9.755 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[11] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.828      ;
; 9.756 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 1.825      ;
; 9.756 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 1.825      ;
; 9.757 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 1.827      ;
; 9.757 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 1.827      ;
; 9.757 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.104     ; 1.825      ;
; 9.760 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.119     ; 1.808      ;
; 9.761 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[9]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.125     ; 1.801      ;
; 9.761 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[13] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.113     ; 1.813      ;
; 9.761 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[14] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.113     ; 1.813      ;
; 9.761 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[15] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.113     ; 1.813      ;
; 9.762 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[8]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.173     ; 1.750      ;
; 9.763 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[14]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.167     ; 1.755      ;
; 9.763 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[15]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.167     ; 1.755      ;
; 9.763 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[13]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.167     ; 1.755      ;
; 9.763 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[9]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.179     ; 1.743      ;
; 9.766 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.120     ; 1.801      ;
; 9.766 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[11] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.120     ; 1.801      ;
; 9.766 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[12] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.120     ; 1.801      ;
; 9.768 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[10]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 1.743      ;
; 9.768 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[12]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 1.743      ;
; 9.768 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[11]     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 1.743      ;
; 9.769 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[0]    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.098     ; 1.819      ;
; 9.769 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[1]    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.098     ; 1.819      ;
; 9.769 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.123     ; 1.795      ;
; 9.770 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[0]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.098     ; 1.818      ;
; 9.770 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.098     ; 1.818      ;
; 9.770 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.095     ; 1.821      ;
; 9.770 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.095     ; 1.821      ;
; 9.770 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.096     ; 1.820      ;
; 9.770 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.098     ; 1.818      ;
; 9.771 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[4]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.177     ; 1.737      ;
; 9.772 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.115     ; 1.800      ;
; 9.774 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[5]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.169     ; 1.742      ;
; 9.774 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[6]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.113     ; 1.800      ;
; 9.775 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[0]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.111     ; 1.801      ;
; 9.775 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.111     ; 1.801      ;
; 9.775 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.111     ; 1.801      ;
; 9.775 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[3]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.113     ; 1.799      ;
; 9.776 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.167     ; 1.742      ;
; 9.777 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[1]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.165     ; 1.743      ;
; 9.777 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[3]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.167     ; 1.741      ;
; 9.777 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[0]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.165     ; 1.743      ;
; 9.777 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[2]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.165     ; 1.743      ;
; 9.793 ; sdram_reset_ctrl_n_reg ; ram_di_reg[11]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.101     ; 1.840      ;
; 9.796 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 1.836      ;
; 9.805 ; sdram_reset_ctrl_n_reg ; ram_do_reg[19]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.093     ; 1.836      ;
; 9.805 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.093     ; 1.836      ;
; 9.805 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.093     ; 1.836      ;
; 9.805 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.093     ; 1.836      ;
; 9.805 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.093     ; 1.836      ;
; 9.805 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.093     ; 1.836      ;
; 9.805 ; sdram_reset_ctrl_n_reg ; ram_do_reg[20]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.093     ; 1.836      ;
; 9.867 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 1.717      ;
; 9.880 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.096     ; 1.710      ;
; 9.880 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.096     ; 1.710      ;
; 9.880 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.096     ; 1.710      ;
; 9.880 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.096     ; 1.710      ;
; 9.880 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.096     ; 1.710      ;
; 9.985 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.094     ; 1.655      ;
; 9.985 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.094     ; 1.655      ;
; 9.985 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.094     ; 1.655      ;
; 9.985 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.094     ; 1.655      ;
; 9.985 ; sdram_reset_ctrl_n_reg ; seq_reg[5]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.094     ; 1.655      ;
; 9.985 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.094     ; 1.655      ;
; 9.985 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.094     ; 1.655      ;
; 9.985 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.095     ; 1.654      ;
; 9.985 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.095     ; 1.654      ;
; 9.985 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.095     ; 1.654      ;
; 9.985 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.094     ; 1.655      ;
; 9.985 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.650      ;
; 9.985 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.650      ;
; 9.985 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.650      ;
; 9.985 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.650      ;
; 9.985 ; sdram_reset_ctrl_n_reg ; ram_do_reg[14]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.650      ;
; 9.985 ; sdram_reset_ctrl_n_reg ; ram_do_reg[11]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.650      ;
; 9.985 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.094     ; 1.655      ;
; 9.985 ; sdram_reset_ctrl_n_reg ; ram_do_reg[15]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.650      ;
; 9.985 ; sdram_reset_ctrl_n_reg ; ram_do_reg[12]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.650      ;
; 9.985 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.096     ; 1.653      ;
; 9.985 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.100     ; 1.649      ;
; 9.985 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.096     ; 1.653      ;
; 9.985 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.100     ; 1.649      ;
; 9.985 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.100     ; 1.649      ;
; 9.985 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.650      ;
; 9.985 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.101     ; 1.648      ;
; 9.985 ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.100     ; 1.649      ;
; 9.985 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.650      ;
; 9.985 ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.100     ; 1.649      ;
; 9.985 ; sdram_reset_ctrl_n_reg ; ram_di_reg[6]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.101     ; 1.648      ;
; 9.985 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.100     ; 1.649      ;
; 9.985 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.650      ;
; 9.985 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.101     ; 1.648      ;
; 9.985 ; sdram_reset_ctrl_n_reg ; ram_di_reg[12]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.650      ;
; 9.985 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.100     ; 1.649      ;
; 9.985 ; sdram_reset_ctrl_n_reg ; ram_di_reg[14]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.101     ; 1.648      ;
; 9.985 ; sdram_reset_ctrl_n_reg ; ram_di_reg[15]                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.100     ; 1.649      ;
; 9.985 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.092     ; 1.657      ;
+-------+------------------------+----------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: 'altera_reserved_tck'                                                                                                                                                                                                                                                                                                                            ;
+--------+--------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                        ; To Node                                                                                                                                                                        ; Launch Clock        ; Latch Clock         ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; 49.197 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 50.000       ; 0.435      ; 1.225      ;
; 98.689 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.042     ; 1.256      ;
; 98.689 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.042     ; 1.256      ;
; 98.689 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.042     ; 1.256      ;
; 98.689 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.042     ; 1.256      ;
; 98.712 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.042     ; 1.233      ;
; 98.712 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.042     ; 1.233      ;
; 98.712 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.042     ; 1.233      ;
; 98.712 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.042     ; 1.233      ;
; 98.852 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 1.099      ;
; 98.852 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 1.099      ;
; 98.852 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 1.099      ;
; 98.852 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 1.099      ;
; 98.870 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 1.081      ;
; 98.870 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 1.081      ;
; 98.870 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 1.081      ;
; 98.870 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0]       ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 1.081      ;
; 98.883 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg                  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.035     ; 1.069      ;
; 98.897 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                 ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.035     ; 1.055      ;
; 98.989 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.034     ; 0.964      ;
; 98.989 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.034     ; 0.964      ;
; 98.989 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.034     ; 0.964      ;
; 98.989 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.034     ; 0.964      ;
; 98.989 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.034     ; 0.964      ;
; 98.989 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.034     ; 0.964      ;
; 98.989 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.034     ; 0.964      ;
; 98.989 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.034     ; 0.964      ;
; 98.989 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][4]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.034     ; 0.964      ;
; 98.989 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.034     ; 0.964      ;
; 98.991 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.034     ; 0.962      ;
; 98.991 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.034     ; 0.962      ;
; 98.991 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                 ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.034     ; 0.962      ;
; 98.991 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0                                                                                                 ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.034     ; 0.962      ;
; 98.996 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.032     ; 0.959      ;
; 98.996 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.032     ; 0.959      ;
; 98.996 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][2]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.032     ; 0.959      ;
; 98.996 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.032     ; 0.959      ;
; 98.996 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][1]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.032     ; 0.959      ;
; 98.996 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.032     ; 0.959      ;
; 98.996 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.032     ; 0.959      ;
; 98.996 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.032     ; 0.959      ;
; 98.996 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][4]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.032     ; 0.959      ;
; 98.996 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.032     ; 0.959      ;
; 99.002 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                 ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.031     ; 0.954      ;
; 99.018 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2]                                                                                                  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.035     ; 0.934      ;
; 99.022 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 0.928      ;
; 99.022 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 0.928      ;
; 99.022 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 0.928      ;
; 99.050 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg                  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.038     ; 0.899      ;
; 99.068 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 0.883      ;
; 99.068 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 0.883      ;
; 99.068 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.036     ; 0.883      ;
; 99.070 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1]                                                                                                  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 0.880      ;
; 99.070 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 0.880      ;
; 99.070 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 0.880      ;
; 99.070 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 0.880      ;
; 99.070 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 0.880      ;
; 99.070 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0]                                                                                                  ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 0.880      ;
; 99.070 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 0.880      ;
; 99.081 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 0.869      ;
; 99.081 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 0.869      ;
; 99.081 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 0.869      ;
; 99.081 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 0.869      ;
; 99.081 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 0.869      ;
; 99.081 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[6]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 0.869      ;
; 99.081 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 0.869      ;
; 99.081 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 0.869      ;
; 99.081 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 0.869      ;
; 99.086 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.038     ; 0.863      ;
; 99.086 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.038     ; 0.863      ;
; 99.086 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.038     ; 0.863      ;
; 99.086 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.038     ; 0.863      ;
; 99.086 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.038     ; 0.863      ;
; 99.086 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[6]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.038     ; 0.863      ;
; 99.086 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.038     ; 0.863      ;
; 99.086 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.038     ; 0.863      ;
; 99.086 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]            ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.038     ; 0.863      ;
; 99.130 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 0.820      ;
; 99.130 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 0.820      ;
; 99.130 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 0.820      ;
; 99.130 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 0.820      ;
; 99.130 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 0.820      ;
; 99.130 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 0.820      ;
; 99.130 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 0.820      ;
; 99.130 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 0.820      ;
; 99.130 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 0.820      ;
; 99.130 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 0.820      ;
; 99.130 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_dr_scan_reg                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 0.820      ;
; 99.130 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 100.000      ; -0.037     ; 0.820      ;
+--------+--------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: 'mcc_pll3|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                              ;
+--------+--------------+-----------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node    ; To Node                                             ; Launch Clock                                         ; Latch Clock                                          ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------+-----------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+
; 64.844 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|dp1_last~_emulated ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.041     ; 1.758      ;
; 64.844 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|dm1_last~_emulated ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.041     ; 1.758      ;
; 65.049 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[2]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.044     ; 1.550      ;
; 65.049 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[0]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.044     ; 1.550      ;
; 65.049 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[1]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.044     ; 1.550      ;
; 65.049 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[3]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.044     ; 1.550      ;
; 65.049 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|synch              ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.044     ; 1.550      ;
; 65.049 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[6]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.044     ; 1.550      ;
; 65.049 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[6]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.044     ; 1.550      ;
; 65.049 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[2]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.044     ; 1.550      ;
; 65.049 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.044     ; 1.550      ;
; 65.049 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[3]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.044     ; 1.550      ;
; 65.049 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.044     ; 1.550      ;
; 65.049 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[4]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.044     ; 1.550      ;
; 65.049 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.044     ; 1.550      ;
; 65.049 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[5]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.044     ; 1.550      ;
; 65.049 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.044     ; 1.550      ;
; 65.049 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[0]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.044     ; 1.550      ;
; 65.049 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[0]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.044     ; 1.550      ;
; 65.049 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[1]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.044     ; 1.550      ;
; 65.049 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.044     ; 1.550      ;
; 65.049 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[7]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.044     ; 1.550      ;
; 65.049 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[7]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.044     ; 1.550      ;
; 65.049 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|read_byte_valid    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.044     ; 1.550      ;
; 65.050 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state2  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.041     ; 1.552      ;
; 65.050 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state4  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.041     ; 1.552      ;
; 65.050 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|stuffin1[0]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.041     ; 1.552      ;
; 65.050 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|stuffin1[1]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.041     ; 1.552      ;
; 65.050 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|stuffin1[2]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.041     ; 1.552      ;
; 65.050 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state1  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.041     ; 1.552      ;
; 65.050 ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state3  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; -0.041     ; 1.552      ;
; 66.284 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state3  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.197      ; 1.556      ;
; 66.284 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[0]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.196      ; 1.555      ;
; 66.284 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[4]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.196      ; 1.555      ;
; 66.284 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[2]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.196      ; 1.555      ;
; 66.284 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[3]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.196      ; 1.555      ;
; 66.284 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[5]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.196      ; 1.555      ;
; 66.284 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[1]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.196      ; 1.555      ;
; 66.284 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[7]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.196      ; 1.555      ;
; 66.284 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[6]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.196      ; 1.555      ;
; 66.284 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state4  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.197      ; 1.556      ;
; 66.285 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dp1_last~_emulated ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.197      ; 1.555      ;
; 66.285 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dm1_last~_emulated ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.197      ; 1.555      ;
; 66.290 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state1  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.205      ; 1.558      ;
; 66.290 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state2  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.205      ; 1.558      ;
; 66.290 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|synch              ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.205      ; 1.558      ;
; 66.290 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[4]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.205      ; 1.558      ;
; 66.290 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[2]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.205      ; 1.558      ;
; 66.290 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[5]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.205      ; 1.558      ;
; 66.290 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[1]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.205      ; 1.558      ;
; 66.290 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[7]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.205      ; 1.558      ;
; 66.290 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[6]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.205      ; 1.558      ;
; 66.290 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|read_byte_valid    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.205      ; 1.558      ;
; 66.291 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[0]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.206      ; 1.558      ;
; 66.291 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[2]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.206      ; 1.558      ;
; 66.291 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[3]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.206      ; 1.558      ;
; 66.291 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[0]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.205      ; 1.557      ;
; 66.291 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[3]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.205      ; 1.557      ;
; 66.291 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|stuffin1[0]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.205      ; 1.557      ;
; 66.291 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|stuffin1[2]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.205      ; 1.557      ;
; 66.291 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|stuffin1[1]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.205      ; 1.557      ;
; 66.291 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[1]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 66.666       ; 1.206      ; 1.558      ;
+--------+--------------+-----------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: 'mcc_pll3|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                               ;
+--------+--------------+-----------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node    ; To Node                                             ; Launch Clock                                         ; Latch Clock                                          ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------+-----------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+
; -0.015 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state1  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.350      ; 1.419      ;
; -0.015 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state2  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.350      ; 1.419      ;
; -0.015 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[2]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.350      ; 1.419      ;
; -0.015 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[1]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.350      ; 1.419      ;
; -0.014 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[0]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.350      ; 1.420      ;
; -0.014 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[2]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.350      ; 1.420      ;
; -0.014 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[3]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.350      ; 1.420      ;
; -0.014 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|synch              ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.350      ; 1.420      ;
; -0.014 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[0]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.349      ; 1.419      ;
; -0.014 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[4]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.350      ; 1.420      ;
; -0.014 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[3]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.349      ; 1.419      ;
; -0.014 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[5]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.350      ; 1.420      ;
; -0.014 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[7]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.350      ; 1.420      ;
; -0.014 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_temp[6]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.350      ; 1.420      ;
; -0.014 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|stuffin1[0]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.349      ; 1.419      ;
; -0.014 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|stuffin1[2]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.349      ; 1.419      ;
; -0.014 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|stuffin1[1]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.349      ; 1.419      ;
; -0.014 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|nb_bits[1]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.350      ; 1.420      ;
; -0.014 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|read_byte_valid    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.350      ; 1.420      ;
; -0.008 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state3  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.342      ; 1.418      ;
; -0.008 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dp1_last~_emulated ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.341      ; 1.417      ;
; -0.008 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|dm1_last~_emulated ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.341      ; 1.417      ;
; -0.008 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb1_state.state4  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.342      ; 1.418      ;
; -0.007 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[0]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.340      ; 1.417      ;
; -0.007 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[4]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.340      ; 1.417      ;
; -0.007 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[2]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.340      ; 1.417      ;
; -0.007 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[3]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.340      ; 1.417      ;
; -0.007 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[5]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.340      ; 1.417      ;
; -0.007 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[1]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.340      ; 1.417      ;
; -0.007 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[7]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.340      ; 1.417      ;
; -0.007 ; reset_usbdrv ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_pkt1[6]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 1.340      ; 1.417      ;
; 1.301  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state2  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.030      ; 1.415      ;
; 1.301  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state4  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.030      ; 1.415      ;
; 1.301  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|stuffin1[0]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.030      ; 1.415      ;
; 1.301  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|stuffin1[1]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.030      ; 1.415      ;
; 1.301  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|stuffin1[2]        ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.030      ; 1.415      ;
; 1.301  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[2]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.028      ; 1.413      ;
; 1.301  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state1  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.030      ; 1.415      ;
; 1.301  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|usb1_state.state3  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.030      ; 1.415      ;
; 1.301  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[0]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.028      ; 1.413      ;
; 1.301  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[1]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.028      ; 1.413      ;
; 1.301  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|nb_bits[3]         ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.028      ; 1.413      ;
; 1.301  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|synch              ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.028      ; 1.413      ;
; 1.301  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[6]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.028      ; 1.413      ;
; 1.301  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[6]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.028      ; 1.413      ;
; 1.301  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[2]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.028      ; 1.413      ;
; 1.301  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[2]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.028      ; 1.413      ;
; 1.301  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[3]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.028      ; 1.413      ;
; 1.301  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[3]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.028      ; 1.413      ;
; 1.301  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[4]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.028      ; 1.413      ;
; 1.301  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[4]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.028      ; 1.413      ;
; 1.301  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[5]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.028      ; 1.413      ;
; 1.301  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[5]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.028      ; 1.413      ;
; 1.301  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[0]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.028      ; 1.413      ;
; 1.301  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[0]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.028      ; 1.413      ;
; 1.301  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[1]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.028      ; 1.413      ;
; 1.301  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[1]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.028      ; 1.413      ;
; 1.301  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_temp[7]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.028      ; 1.413      ;
; 1.301  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|data_pkt1[7]       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.028      ; 1.413      ;
; 1.301  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|read_byte_valid    ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.028      ; 1.413      ;
; 1.481  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|dp1_last~_emulated ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.030      ; 1.595      ;
; 1.481  ; reset_usbdrv ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|dm1_last~_emulated ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.030      ; 1.595      ;
+--------+--------------+-----------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: 'altera_reserved_tck'                                                                                                                                                                                                                                                                                                                             ;
+--------+--------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                        ; To Node                                                                                                                                                                        ; Launch Clock        ; Latch Clock         ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+
; 0.585  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.704      ;
; 0.585  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.704      ;
; 0.585  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.704      ;
; 0.585  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.704      ;
; 0.585  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.704      ;
; 0.585  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.704      ;
; 0.585  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.704      ;
; 0.585  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.704      ;
; 0.585  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.704      ;
; 0.585  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0]                                                                                                   ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.704      ;
; 0.585  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_dr_scan_reg                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.704      ;
; 0.585  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.704      ;
; 0.655  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.034      ; 0.773      ;
; 0.655  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.034      ; 0.773      ;
; 0.655  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.034      ; 0.773      ;
; 0.655  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.034      ; 0.773      ;
; 0.655  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.034      ; 0.773      ;
; 0.655  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[6]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.034      ; 0.773      ;
; 0.655  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.034      ; 0.773      ;
; 0.655  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.034      ; 0.773      ;
; 0.655  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.034      ; 0.773      ;
; 0.657  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1]                                                                                                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.776      ;
; 0.657  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.776      ;
; 0.657  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.776      ;
; 0.657  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.776      ;
; 0.657  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.776      ;
; 0.657  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0]                                                                                                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.776      ;
; 0.657  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.776      ;
; 0.660  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.034      ; 0.778      ;
; 0.660  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.034      ; 0.778      ;
; 0.660  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.034      ; 0.778      ;
; 0.660  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.034      ; 0.778      ;
; 0.660  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.034      ; 0.778      ;
; 0.660  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[6]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.034      ; 0.778      ;
; 0.660  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.034      ; 0.778      ;
; 0.660  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.034      ; 0.778      ;
; 0.660  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]            ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.034      ; 0.778      ;
; 0.667  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.034      ; 0.785      ;
; 0.667  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.034      ; 0.785      ;
; 0.667  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.034      ; 0.785      ;
; 0.671  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.034      ; 0.789      ;
; 0.684  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg                ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2]                                                                                                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.805      ;
; 0.703  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.822      ;
; 0.703  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.822      ;
; 0.703  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.822      ;
; 0.705  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                 ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.040      ; 0.829      ;
; 0.712  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.040      ; 0.836      ;
; 0.712  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.040      ; 0.836      ;
; 0.712  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][2]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.040      ; 0.836      ;
; 0.712  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.040      ; 0.836      ;
; 0.712  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][1]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.040      ; 0.836      ;
; 0.712  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.040      ; 0.836      ;
; 0.712  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.040      ; 0.836      ;
; 0.712  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.040      ; 0.836      ;
; 0.712  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][4]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.040      ; 0.836      ;
; 0.712  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.040      ; 0.836      ;
; 0.717  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.038      ; 0.839      ;
; 0.717  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                      ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.038      ; 0.839      ;
; 0.717  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                 ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.038      ; 0.839      ;
; 0.717  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0                                                                                                 ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.038      ; 0.839      ;
; 0.721  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.842      ;
; 0.721  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.842      ;
; 0.721  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.842      ;
; 0.721  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.842      ;
; 0.721  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.842      ;
; 0.721  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.842      ;
; 0.721  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.842      ;
; 0.721  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.842      ;
; 0.721  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][4]                                                                                             ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.842      ;
; 0.721  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                                                                                                    ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.842      ;
; 0.803  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.922      ;
; 0.803  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.922      ;
; 0.803  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.922      ;
; 0.803  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.922      ;
; 0.811  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                 ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.036      ; 0.931      ;
; 0.817  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg                            ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg                  ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.037      ; 0.938      ;
; 0.864  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.983      ;
; 0.864  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.983      ;
; 0.864  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.983      ;
; 0.864  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                      ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.035      ; 0.983      ;
; 0.979  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.030      ; 1.093      ;
; 0.979  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.030      ; 1.093      ;
; 0.979  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.030      ; 1.093      ;
; 0.979  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.030      ; 1.093      ;
; 1.000  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.030      ; 1.114      ;
; 1.000  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.030      ; 1.114      ;
; 1.000  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.030      ; 1.114      ;
; 1.000  ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                      ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0]       ; altera_reserved_tck ; altera_reserved_tck ; 0.000        ; 0.030      ; 1.114      ;
; 50.449 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                              ; altera_reserved_tck ; altera_reserved_tck ; -50.000      ; 0.512      ; 1.065      ;
+--------+--------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                           ; To Node                                                                                                                                                                                                                ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 0.694 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a55  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 0.984      ;
; 0.694 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a54  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 0.984      ;
; 0.694 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a53  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 0.984      ;
; 0.694 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a52  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 0.984      ;
; 0.694 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a51  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 0.984      ;
; 0.694 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a50  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 0.984      ;
; 0.694 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a49  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 0.984      ;
; 0.694 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a48  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 0.984      ;
; 0.694 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a47  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 0.984      ;
; 0.694 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a46  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 0.984      ;
; 0.694 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a45  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 0.984      ;
; 0.694 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a44  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 0.984      ;
; 0.694 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a43  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 0.984      ;
; 0.694 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a42  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 0.984      ;
; 0.694 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a41  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 0.984      ;
; 0.694 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a40  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 0.984      ;
; 0.694 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a39  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 0.984      ;
; 0.694 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a38  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 0.984      ;
; 0.694 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a37  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 0.984      ;
; 0.694 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a36  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 0.984      ;
; 0.694 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a23  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 0.984      ;
; 0.694 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a22  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 0.984      ;
; 0.694 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a21  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 0.984      ;
; 0.694 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a20  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 0.984      ;
; 0.694 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a19  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 0.984      ;
; 0.694 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a18  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 0.984      ;
; 0.694 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a17  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 0.984      ;
; 0.694 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a16  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 0.984      ;
; 0.694 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a7   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 0.984      ;
; 0.694 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a6   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 0.984      ;
; 0.694 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a5   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 0.984      ;
; 0.694 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a4   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 0.984      ;
; 0.694 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a3   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 0.984      ;
; 0.694 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a2   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 0.984      ;
; 0.694 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a1   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 0.984      ;
; 0.694 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 0.984      ;
; 0.698 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a5 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 0.989      ;
; 0.698 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a4 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 0.989      ;
; 0.698 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a3 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 0.989      ;
; 0.698 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a2 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 0.989      ;
; 0.698 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 0.989      ;
; 0.698 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 0.989      ;
; 0.852 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a63  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 1.142      ;
; 0.852 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a62  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 1.142      ;
; 0.852 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a61  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 1.142      ;
; 0.852 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a60  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 1.142      ;
; 0.852 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a59  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 1.142      ;
; 0.852 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a58  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 1.142      ;
; 0.852 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a57  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 1.142      ;
; 0.852 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a56  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 1.142      ;
; 0.852 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a35  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 1.142      ;
; 0.852 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a34  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 1.142      ;
; 0.852 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a33  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 1.142      ;
; 0.852 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a32  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 1.142      ;
; 0.852 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a31  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 1.142      ;
; 0.852 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a30  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 1.142      ;
; 0.852 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a29  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 1.142      ;
; 0.852 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a28  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 1.142      ;
; 0.852 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a27  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 1.142      ;
; 0.852 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a26  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 1.142      ;
; 0.852 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a25  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 1.142      ;
; 0.852 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a24  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 1.142      ;
; 0.852 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a15  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 1.142      ;
; 0.852 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a14  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 1.142      ;
; 0.852 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a13  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 1.142      ;
; 0.852 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a12  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 1.142      ;
; 0.852 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a11  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 1.142      ;
; 0.852 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a10  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 1.142      ;
; 0.852 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a9   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 1.142      ;
; 0.852 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|dffe4   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a8   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 1.142      ;
; 0.906 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a6 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.213      ; 1.209      ;
; 0.906 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a5 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.213      ; 1.209      ;
; 0.906 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a4 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.213      ; 1.209      ;
; 0.906 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a3 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.213      ; 1.209      ;
; 0.906 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a2 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.213      ; 1.209      ;
; 0.906 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.213      ; 1.209      ;
; 0.906 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|dffe4 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a0 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.213      ; 1.209      ;
; 1.073 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a15   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 1.364      ;
; 1.073 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a14   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 1.364      ;
; 1.073 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a13   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 1.364      ;
; 1.073 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a12   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 1.364      ;
; 1.073 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a11   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 1.364      ;
; 1.073 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a10   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 1.364      ;
; 1.073 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a9    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 1.364      ;
; 1.073 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a8    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 1.364      ;
; 1.073 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a7    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 1.364      ;
; 1.073 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a6    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 1.364      ;
; 1.073 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a5    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 1.364      ;
; 1.073 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a4    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 1.364      ;
; 1.073 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a3    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 1.364      ;
; 1.073 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a2    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 1.364      ;
; 1.073 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a1    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 1.364      ;
; 1.073 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|dffe4    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0|shift_taps_s5n:auto_generated|altsyncram_s1b1:altsyncram2|ram_block5a0    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 1.364      ;
; 1.686 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[4]                                                                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.300      ; 2.091      ;
; 1.686 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[5]                                                                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.300      ; 2.091      ;
; 1.705 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]                                                                                                                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.296      ; 2.106      ;
; 1.705 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[8]                                                                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.296      ; 2.106      ;
; 1.705 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                                                                                                                                                                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.296      ; 2.106      ;
; 1.892 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[2]                                                                                                                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.102      ; 2.099      ;
; 1.893 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[15]                                                                                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.104      ; 2.102      ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                       ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                                   ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 1.107 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.289      ; 1.499      ;
; 1.304 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.087      ; 1.494      ;
; 1.304 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.087      ; 1.494      ;
; 1.304 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.087      ; 1.494      ;
; 1.304 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.087      ; 1.494      ;
; 1.304 ; sdram_reset_ctrl_n_reg ; seq_reg[5]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.087      ; 1.494      ;
; 1.304 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.087      ; 1.494      ;
; 1.304 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.087      ; 1.494      ;
; 1.304 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.087      ; 1.494      ;
; 1.304 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.087      ; 1.494      ;
; 1.304 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.087      ; 1.494      ;
; 1.304 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 1.493      ;
; 1.304 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 1.486      ;
; 1.304 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 1.486      ;
; 1.304 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 1.486      ;
; 1.304 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 1.486      ;
; 1.304 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 1.486      ;
; 1.304 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 1.486      ;
; 1.304 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 1.486      ;
; 1.304 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 1.486      ;
; 1.304 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 1.486      ;
; 1.304 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 1.486      ;
; 1.304 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 1.486      ;
; 1.304 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 1.493      ;
; 1.304 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 1.493      ;
; 1.304 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 1.493      ;
; 1.304 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.086      ; 1.493      ;
; 1.304 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.087      ; 1.494      ;
; 1.304 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.087      ; 1.494      ;
; 1.304 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.085      ; 1.492      ;
; 1.304 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.085      ; 1.492      ;
; 1.304 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 1.496      ;
; 1.304 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.091      ; 1.498      ;
; 1.306 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.490      ;
; 1.306 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.490      ;
; 1.306 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.490      ;
; 1.306 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.490      ;
; 1.306 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.490      ;
; 1.306 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.491      ;
; 1.306 ; sdram_reset_ctrl_n_reg ; ram_do_reg[5]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.490      ;
; 1.306 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.491      ;
; 1.306 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.491      ;
; 1.306 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.491      ;
; 1.306 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.490      ;
; 1.306 ; sdram_reset_ctrl_n_reg ; ram_do_reg[14]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.491      ;
; 1.306 ; sdram_reset_ctrl_n_reg ; ram_do_reg[8]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.490      ;
; 1.306 ; sdram_reset_ctrl_n_reg ; ram_do_reg[11]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.491      ;
; 1.306 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.490      ;
; 1.306 ; sdram_reset_ctrl_n_reg ; ram_do_reg[9]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.490      ;
; 1.306 ; sdram_reset_ctrl_n_reg ; ram_do_reg[15]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.491      ;
; 1.306 ; sdram_reset_ctrl_n_reg ; ram_do_reg[25]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.490      ;
; 1.306 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.490      ;
; 1.306 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.490      ;
; 1.306 ; sdram_reset_ctrl_n_reg ; ram_do_reg[13]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.490      ;
; 1.306 ; sdram_reset_ctrl_n_reg ; ram_do_reg[12]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.491      ;
; 1.306 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.490      ;
; 1.306 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.490      ;
; 1.306 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.489      ;
; 1.306 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.489      ;
; 1.306 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.491      ;
; 1.306 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.490      ;
; 1.306 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.491      ;
; 1.306 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.491      ;
; 1.306 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.491      ;
; 1.306 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.491      ;
; 1.306 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.489      ;
; 1.306 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.490      ;
; 1.306 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.489      ;
; 1.306 ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.489      ;
; 1.306 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.490      ;
; 1.306 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[1]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.489      ;
; 1.306 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[0]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.491      ;
; 1.307 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.492      ;
; 1.307 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.490      ;
; 1.307 ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.491      ;
; 1.307 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.492      ;
; 1.307 ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.491      ;
; 1.307 ; sdram_reset_ctrl_n_reg ; ram_di_reg[6]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.490      ;
; 1.307 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.491      ;
; 1.307 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.492      ;
; 1.307 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.490      ;
; 1.307 ; sdram_reset_ctrl_n_reg ; ram_di_reg[12]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.492      ;
; 1.307 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.491      ;
; 1.307 ; sdram_reset_ctrl_n_reg ; ram_di_reg[14]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.490      ;
; 1.307 ; sdram_reset_ctrl_n_reg ; ram_di_reg[15]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.491      ;
; 1.411 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.560      ;
; 1.411 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.560      ;
; 1.411 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.560      ;
; 1.411 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.560      ;
; 1.411 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.560      ;
; 1.423 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.068      ; 1.566      ;
; 1.466 ; sdram_reset_ctrl_n_reg ; ram_do_reg[19]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.088      ; 1.657      ;
; 1.466 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.088      ; 1.657      ;
; 1.466 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.088      ; 1.657      ;
; 1.466 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.088      ; 1.657      ;
; 1.466 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.088      ; 1.657      ;
; 1.466 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.088      ; 1.657      ;
; 1.466 ; sdram_reset_ctrl_n_reg ; ram_do_reg[20]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.088      ; 1.657      ;
; 1.476 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 1.658      ;
; 1.478 ; sdram_reset_ctrl_n_reg ; ram_di_reg[11]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.661      ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3]'                                                         ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+---------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                         ; Clock Edge ; Target                    ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+---------------------------+
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[2]              ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[3]              ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[4]              ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[5]              ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[6]              ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[7]              ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[8]              ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[9]              ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[0]         ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[1]         ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[2]         ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[3]         ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[4]         ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[5]         ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[6]         ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[7]         ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[8]         ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[9]         ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[0]   ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[1]   ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[2]   ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[3]   ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[4]   ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[5]   ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[6]   ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[7]   ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[8]   ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[9]   ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[0]   ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[1]   ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[2]   ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[3]   ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[4]   ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[5]   ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[6]   ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[7]   ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[8]   ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[9]   ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[0] ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[1] ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[2] ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[3] ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[4] ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[5] ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[6] ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[7] ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[8] ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[9] ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly1[0]       ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly1[1]       ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly1[2]       ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly1[3]       ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly1[4]       ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly1[5]       ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly1[6]       ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly1[7]       ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly2[0]       ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly2[1]       ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly2[2]       ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly2[3]       ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly2[4]       ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly2[5]       ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly2[6]       ;
; 4.188 ; 4.404        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo_yout_dly2[7]       ;
; 4.219 ; 4.403        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[0]   ;
; 4.219 ; 4.403        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[1]   ;
; 4.219 ; 4.403        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[2]   ;
; 4.219 ; 4.403        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[4]   ;
; 4.219 ; 4.403        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[6]   ;
; 4.219 ; 4.403        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_2[7]   ;
; 4.219 ; 4.403        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[0] ;
; 4.219 ; 4.403        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[1] ;
; 4.219 ; 4.403        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[2] ;
; 4.219 ; 4.403        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[3] ;
; 4.219 ; 4.403        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[4] ;
; 4.219 ; 4.403        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[5] ;
; 4.219 ; 4.403        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[6] ;
; 4.219 ; 4.403        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[7] ;
; 4.219 ; 4.403        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[8] ;
; 4.219 ; 4.403        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_acc[9] ;
; 4.220 ; 4.404        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[2]              ;
; 4.220 ; 4.404        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[3]              ;
; 4.220 ; 4.404        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[4]              ;
; 4.220 ; 4.404        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[5]              ;
; 4.220 ; 4.404        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[6]              ;
; 4.220 ; 4.404        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[7]              ;
; 4.220 ; 4.404        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[8]              ;
; 4.220 ; 4.404        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; cvbs1_out[9]              ;
; 4.220 ; 4.404        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[0]         ;
; 4.220 ; 4.404        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[1]         ;
; 4.220 ; 4.404        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[2]         ;
; 4.220 ; 4.404        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[3]         ;
; 4.220 ; 4.404        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[4]         ;
; 4.220 ; 4.404        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[5]         ;
; 4.220 ; 4.404        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[6]         ;
; 4.220 ; 4.404        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[7]         ;
; 4.220 ; 4.404        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[8]         ;
; 4.220 ; 4.404        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; luma_saturated[9]         ;
; 4.220 ; 4.404        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[0]   ;
; 4.220 ; 4.404        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; Rise       ; svideo:svideo|luma_1[1]   ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+---------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                         ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                         ; Clock Edge ; Target                                                    ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[0]                                           ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[0]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[11]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[12]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[13]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[15]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[3]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[4]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[5]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[7]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[8]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[0]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[10]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[11]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[12]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[13]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[14]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[15]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[17]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[18]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[1]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[21]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[24]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[25]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[26]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[29]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[2]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[3]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[4]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[5]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[6]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[7]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[8]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[9]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_act                      ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_req                    ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[0]                                                ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[1]                                           ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[10]                                            ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[14]                                            ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[1]                                             ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[2]                                             ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[6]                                             ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[9]                                             ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[16]                                            ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[19]                                            ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[20]                                            ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[22]                                            ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[23]                                            ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[27]                                            ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[31]                                            ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_reg                      ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_act                    ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_act                      ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_reg                      ;
; 5.657 ; 5.873        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[28]                                            ;
; 5.657 ; 5.873        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[30]                                            ;
; 5.657 ; 5.873        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ;
; 5.657 ; 5.873        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ;
; 5.657 ; 5.873        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ;
; 5.657 ; 5.873        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ;
; 5.657 ; 5.873        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ;
; 5.657 ; 5.873        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|sdram_rdy                     ;
; 5.657 ; 5.873        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[11]                                               ;
; 5.657 ; 5.873        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[1]                                                ;
; 5.657 ; 5.873        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[2]                                                ;
; 5.657 ; 5.873        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[3]                                                ;
; 5.657 ; 5.873        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[4]                                                ;
; 5.657 ; 5.873        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[5]                                                ;
; 5.657 ; 5.873        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[6]                                                ;
; 5.657 ; 5.873        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[7]                                                ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel[0]                     ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_reg                                         ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[10]                                               ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[8]                                                ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[9]                                                ;
; 5.662 ; 5.846        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_complete_reg                                ;
; 5.663 ; 5.818        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[13]                  ;
; 5.663 ; 5.818        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[14]                  ;
; 5.663 ; 5.818        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[15]                  ;
; 5.665 ; 5.820        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[0]                   ;
; 5.665 ; 5.820        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[1]                   ;
; 5.665 ; 5.820        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[2]                   ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                          ;
+--------+--------------+----------------+-----------------+-------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type            ; Clock                                                                         ; Clock Edge ; Target                                                                                                                                                                                                                                     ;
+--------+--------------+----------------+-----------------+-------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_ig41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                           ;
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_ig41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                 ;
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_ig41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                            ;
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_ig41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                  ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~porta_address_reg0    ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a8~porta_address_reg0    ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; svideo:svideo|sin_cos:tab_inst|sin_rom:sin_inst|altsyncram:altsyncram_component|altsyncram_r842:auto_generated|ram_block1a0~porta_address_reg0                                                                                             ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; svideo:svideo|sin_cos:tab_inst|sin_rom:sin_inst|altsyncram:altsyncram_component|altsyncram_r842:auto_generated|ram_block1a3~porta_address_reg0                                                                                             ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ld71:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                                       ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ld71:auto_generated|ram_block1a10~porta_address_reg0                                                                                                                                      ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ld71:auto_generated|ram_block1a11~porta_address_reg0                                                                                                                                      ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ld71:auto_generated|ram_block1a13~porta_address_reg0                                                                                                                                      ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ld71:auto_generated|ram_block1a14~porta_address_reg0                                                                                                                                      ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ld71:auto_generated|ram_block1a2~porta_address_reg0                                                                                                                                       ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ld71:auto_generated|ram_block1a3~porta_address_reg0                                                                                                                                       ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ld71:auto_generated|ram_block1a5~porta_address_reg0                                                                                                                                       ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ld71:auto_generated|ram_block1a9~porta_address_reg0                                                                                                                                       ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_ig41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                           ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_ig41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_ig41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                          ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_ig41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|generic_ram_infer:freezer_bram|altsyncram:ram_block_rtl_0|altsyncram_sd41:auto_generated|ram_block1a0~porta_address_reg0 ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|generic_ram_infer:freezer_bram|altsyncram:ram_block_rtl_0|altsyncram_sd41:auto_generated|ram_block1a0~porta_we_reg       ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0|shift_taps_gkm:auto_generated|altsyncram_62b1:altsyncram2|ram_block5a0~porta_address_reg0  ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0|shift_taps_hkm:auto_generated|altsyncram_72b1:altsyncram2|ram_block5a0~porta_address_reg0  ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0                       ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a0~portb_address_reg0    ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a1                       ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a10                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a11                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a12                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a13                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a14                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a15                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a16                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a17                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a18                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a19                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a2                       ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a20                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a21                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a22                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a23                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a24                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a25                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a26                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a27                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a28                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a29                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a3                       ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a30                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a31                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a32                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a33                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a34                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a35                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a36                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a37                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a38                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a39                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a4                       ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a40                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a41                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a42                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a43                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a44                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a45                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a46                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a47                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a48                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a49                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a5                       ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a50                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a51                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a52                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a53                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a54                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a55                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a56                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a57                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a58                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a59                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a6                       ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a60                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a61                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a62                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a63                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a7                       ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a8                       ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a8~portb_address_reg0    ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_06n:auto_generated|altsyncram_82b1:altsyncram2|ram_block5a9                       ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; svideo:svideo|sin_cos:tab_inst|sin_rom:sin_inst|altsyncram:altsyncram_component|altsyncram_r842:auto_generated|ram_block1a0~portb_address_reg0                                                                                             ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; svideo:svideo|sin_cos:tab_inst|sin_rom:sin_inst|altsyncram:altsyncram_component|altsyncram_r842:auto_generated|ram_block1a3~portb_address_reg0                                                                                             ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ld71:auto_generated|ram_block1a12~porta_address_reg0                                                                                                                                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ld71:auto_generated|ram_block1a1~porta_address_reg0                                                                                                                                       ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ld71:auto_generated|ram_block1a22~porta_address_reg0                                                                                                                                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ld71:auto_generated|ram_block1a4~porta_address_reg0                                                                                                                                       ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ld71:auto_generated|ram_block1a6~porta_address_reg0                                                                                                                                       ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ld71:auto_generated|ram_block1a7~porta_address_reg0                                                                                                                                       ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_ld71:auto_generated|ram_block1a8~porta_address_reg0                                                                                                                                       ;
+--------+--------------+----------------+-----------------+-------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                   ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                        ; Clock Edge ; Target                                                                                             ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------+
; 17.601 ; 17.601       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.601 ; 17.601       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.601 ; 17.601       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.601 ; 17.601       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3]                      ;
; 17.601 ; 17.601       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 17.615 ; 17.615       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.619 ; 17.619       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.619 ; 17.619       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.623 ; 17.623       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.623 ; 17.623       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.626 ; 17.626       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.641 ; 17.641       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.641 ; 17.641       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.641 ; 17.641       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.641 ; 17.641       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3]                      ;
; 17.641 ; 17.641       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'mcc_pll3|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                  ;
+--------+--------------+----------------+------------------+------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                ; Clock Edge ; Target                                                                                                                                                                            ;
+--------+--------------+----------------+------------------+------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 33.024 ; 33.254       ; 0.230          ; Low Pulse Width  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~porta_address_reg0 ;
; 33.024 ; 33.254       ; 0.230          ; Low Pulse Width  ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~porta_re_reg       ;
; 33.044 ; 33.260       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_start[0]                                                                                                                                 ;
; 33.044 ; 33.260       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_start[1]                                                                                                                                 ;
; 33.044 ; 33.260       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_start[2]                                                                                                                                 ;
; 33.044 ; 33.260       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_start[5]                                                                                                                                 ;
; 33.044 ; 33.260       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_start[7]                                                                                                                                 ;
; 33.044 ; 33.260       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|read_byte_valid_c                                                                                                                                ;
; 33.044 ; 33.260       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.read_byte1                                                                                                                            ;
; 33.044 ; 33.260       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.read_byte10                                                                                                                           ;
; 33.044 ; 33.260       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.read_byte11                                                                                                                           ;
; 33.044 ; 33.260       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.read_byte2                                                                                                                            ;
; 33.044 ; 33.260       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.read_byte3                                                                                                                            ;
; 33.044 ; 33.260       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.read_byte4                                                                                                                            ;
; 33.044 ; 33.260       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.read_byte5                                                                                                                            ;
; 33.044 ; 33.260       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.read_byte6                                                                                                                            ;
; 33.044 ; 33.260       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.read_byte7                                                                                                                            ;
; 33.044 ; 33.260       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.read_byte8                                                                                                                            ;
; 33.044 ; 33.260       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.read_byte9                                                                                                                            ;
; 33.044 ; 33.260       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.send_ack                                                                                                                              ;
; 33.044 ; 33.260       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.setaddress_sendpkt3                                                                                                                   ;
; 33.044 ; 33.260       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.setaddress_sendpkt3_end                                                                                                               ;
; 33.044 ; 33.260       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait4                                                                                                                                 ;
; 33.044 ; 33.260       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_pktin1                                                                                                                           ;
; 33.044 ; 33.260       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte10                                                                                                                      ;
; 33.044 ; 33.260       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte11                                                                                                                      ;
; 33.044 ; 33.260       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte2                                                                                                                       ;
; 33.044 ; 33.260       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte3                                                                                                                       ;
; 33.044 ; 33.260       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte4                                                                                                                       ;
; 33.044 ; 33.260       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte5                                                                                                                       ;
; 33.044 ; 33.260       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte6                                                                                                                       ;
; 33.044 ; 33.260       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte7                                                                                                                       ;
; 33.044 ; 33.260       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte8                                                                                                                       ;
; 33.044 ; 33.260       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_read_byte9                                                                                                                       ;
; 33.045 ; 33.261       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_start[4]                                                                                                                                 ;
; 33.045 ; 33.261       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|address_start[6]                                                                                                                                 ;
; 33.045 ; 33.261       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_available                                                                                                                                   ;
; 33.045 ; 33.261       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_byte2[0]                                                                                                                                    ;
; 33.045 ; 33.261       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_byte2[1]                                                                                                                                    ;
; 33.045 ; 33.261       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_byte2[2]                                                                                                                                    ;
; 33.045 ; 33.261       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_byte2[3]                                                                                                                                    ;
; 33.045 ; 33.261       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_byte2[4]                                                                                                                                    ;
; 33.045 ; 33.261       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_byte2[5]                                                                                                                                    ;
; 33.045 ; 33.261       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_byte2[6]                                                                                                                                    ;
; 33.045 ; 33.261       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_byte2[7]                                                                                                                                    ;
; 33.045 ; 33.261       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_valid                                                                                                                                       ;
; 33.045 ; 33.261       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|joyleft_temp[0]                                                                                                                                  ;
; 33.045 ; 33.261       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|joyleft_temp[1]                                                                                                                                  ;
; 33.045 ; 33.261       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|joyleft_temp[2]                                                                                                                                  ;
; 33.045 ; 33.261       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|joyleft_temp[3]                                                                                                                                  ;
; 33.045 ; 33.261       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|set_command[0]                                                                                                                                   ;
; 33.045 ; 33.261       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|set_command[1]                                                                                                                                   ;
; 33.045 ; 33.261       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|start_sendcom                                                                                                                                    ;
; 33.045 ; 33.261       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.crc_complete                                                                                                                          ;
; 33.045 ; 33.261       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.end_set_address                                                                                                                       ;
; 33.045 ; 33.261       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.end_set_configuration                                                                                                                 ;
; 33.045 ; 33.261       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.end_set_idle                                                                                                                          ;
; 33.045 ; 33.261       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.send_ack_end                                                                                                                          ;
; 33.045 ; 33.261       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.send_getreport_ack_end                                                                                                                ;
; 33.045 ; 33.261       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.usb_reset_1ms_start                                                                                                                   ;
; 33.045 ; 33.261       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait1                                                                                                                                 ;
; 33.045 ; 33.261       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait20                                                                                                                                ;
; 33.045 ; 33.261       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait21                                                                                                                                ;
; 33.045 ; 33.261       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait30                                                                                                                                ;
; 33.046 ; 33.262       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1_3ms[0]                                                                                                                                  ;
; 33.046 ; 33.262       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1_3ms[5]                                                                                                                                  ;
; 33.046 ; 33.262       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1_3ms[9]                                                                                                                                  ;
; 33.046 ; 33.262       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter2[0]                                                                                                                                      ;
; 33.046 ; 33.262       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter2[1]                                                                                                                                      ;
; 33.046 ; 33.262       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter2[2]                                                                                                                                      ;
; 33.046 ; 33.262       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter2[3]                                                                                                                                      ;
; 33.046 ; 33.262       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter30ms[0]                                                                                                                                   ;
; 33.046 ; 33.262       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter30ms[1]                                                                                                                                   ;
; 33.046 ; 33.262       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter30ms[2]                                                                                                                                   ;
; 33.046 ; 33.262       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter30ms[3]                                                                                                                                   ;
; 33.046 ; 33.262       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter30ms[4]                                                                                                                                   ;
; 33.046 ; 33.262       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter30ms[5]                                                                                                                                   ;
; 33.046 ; 33.262       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter30ms[6]                                                                                                                                   ;
; 33.046 ; 33.262       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter30ms[7]                                                                                                                                   ;
; 33.046 ; 33.262       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter30ms[8]                                                                                                                                   ;
; 33.046 ; 33.262       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|data_valid_temp                                                                                                                                  ;
; 33.046 ; 33.262       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|joyright_temp[3]                                                                                                                                 ;
; 33.046 ; 33.262       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.Idle                                                                                                                                  ;
; 33.046 ; 33.262       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.getreport_sendpkt1                                                                                                                    ;
; 33.046 ; 33.262       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.getreport_sendpkt1_end                                                                                                                ;
; 33.046 ; 33.262       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.send_getreport_ack                                                                                                                    ;
; 33.046 ; 33.262       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.setaddress_sendpkt1                                                                                                                   ;
; 33.046 ; 33.262       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.setaddress_sendpkt2                                                                                                                   ;
; 33.046 ; 33.262       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.setaddress_sendpkt2_end                                                                                                               ;
; 33.046 ; 33.262       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.usb_manage2                                                                                                                           ;
; 33.046 ; 33.262       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.usb_reset_1ms_release                                                                                                                 ;
; 33.046 ; 33.262       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.usb_reset_1ms_wait1                                                                                                                   ;
; 33.046 ; 33.262       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.usb_reset_state                                                                                                                       ;
; 33.046 ; 33.262       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_ack2                                                                                                                             ;
; 33.046 ; 33.262       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_for_deviceconnect                                                                                                                ;
; 33.046 ; 33.262       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_manage.wait_report_start                                                                                                                     ;
; 33.046 ; 33.262       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|usb_reset                                                                                                                                        ;
; 33.047 ; 33.263       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[0]                                                                                                                                      ;
; 33.047 ; 33.263       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[1]                                                                                                                                      ;
; 33.047 ; 33.263       ; 0.216          ; High Pulse Width ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|counter1[2]                                                                                                                                      ;
+--------+--------------+----------------+------------------+------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'altera_reserved_tck'                                                                                                                                                                                                                                                      ;
+--------+--------------+----------------+------------------+---------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock               ; Clock Edge ; Target                                                                                                                                                                                                                ;
+--------+--------------+----------------+------------------+---------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 49.295 ; 49.525       ; 0.230          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ;
; 49.295 ; 49.525       ; 0.230          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                           ;
; 49.295 ; 49.525       ; 0.230          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_address_reg0                                     ;
; 49.295 ; 49.525       ; 0.230          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_we_reg                                           ;
; 49.297 ; 49.527       ; 0.230          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_datain_reg0                                      ;
; 49.297 ; 49.527       ; 0.230          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|altsyncram_eie2:altsyncram1|ram_block3a0~portb_datain_reg0                                      ;
; 49.311 ; 49.527       ; 0.216          ; High Pulse Width ; altera_reserved_tck ; Fall       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo                                                                                                                                                     ;
; 49.353 ; 49.537       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]                                                   ;
; 49.353 ; 49.537       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]                                                   ;
; 49.353 ; 49.537       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]                                                   ;
; 49.353 ; 49.537       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]                                                   ;
; 49.353 ; 49.537       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]                                                   ;
; 49.353 ; 49.537       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5]                                                   ;
; 49.353 ; 49.537       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[6]                                                   ;
; 49.353 ; 49.537       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7]                                                   ;
; 49.353 ; 49.537       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8]                                                   ;
; 49.353 ; 49.537       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1]                                                   ;
; 49.353 ; 49.537       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2]                                                   ;
; 49.353 ; 49.537       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3]                                                   ;
; 49.353 ; 49.537       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4]                                                   ;
; 49.353 ; 49.537       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[5]                                                   ;
; 49.353 ; 49.537       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[6]                                                   ;
; 49.353 ; 49.537       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7]                                                   ;
; 49.353 ; 49.537       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]                                                                                                                                           ;
; 49.353 ; 49.537       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1]                                                                                                                                           ;
; 49.353 ; 49.537       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2]                                                                                                                                           ;
; 49.353 ; 49.537       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3]                                                                                                                                           ;
; 49.353 ; 49.537       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4]                                                                                                                                           ;
; 49.353 ; 49.537       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0]                                                                                                                                    ;
; 49.353 ; 49.537       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][1]                                                                                                                                    ;
; 49.353 ; 49.537       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][2]                                                                                                                                    ;
; 49.353 ; 49.537       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3]                                                                                                                                    ;
; 49.353 ; 49.537       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][4]                                                                                                                                    ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                                                        ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0]                                              ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1]                                              ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2]                                              ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3]                                              ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg                                                         ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]                                                   ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]                                                   ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]                                                   ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]                                                   ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]                                                   ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5]                                                   ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[6]                                                   ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7]                                                   ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8]                                                   ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]                                                   ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1]                                                   ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2]                                                   ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3]                                                   ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4]                                                   ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[5]                                                   ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[6]                                                   ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7]                                                   ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                        ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]                                        ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2]                                        ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[0]      ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[1]      ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[2]      ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[3]      ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[0] ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[1] ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[2] ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[3] ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                                                        ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]                                                   ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]                                        ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]                                        ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2]                                        ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]                                                                                                                                           ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1]                                                                                                                                           ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2]                                                                                                                                           ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3]                                                                                                                                           ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4]                                                                                                                                           ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5]                                                                                                                                             ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6]                                                                                                                                             ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0                                                                                                                                        ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0                                                                                                                                        ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|reset_ena_reg                                                                                                                                           ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0]                                                                                                                                    ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1]                                                                                                                                    ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2]                                                                                                                                    ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3]                                                                                                                                    ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][4]                                                                                                                                    ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4]                                                                                                                      ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5]                                                                                                                      ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6]                                                                                                                      ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7]                                                                                                                      ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8]                                                                                                                      ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0]                                                                                                                    ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1]                                                                                                                    ;
; 49.354 ; 49.538       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2]                                                                                                                    ;
; 49.355 ; 49.539       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0]                                              ;
; 49.355 ; 49.539       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1]                                              ;
; 49.355 ; 49.539       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2]                                              ;
; 49.355 ; 49.539       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3]                                              ;
; 49.355 ; 49.539       ; 0.184          ; Low Pulse Width  ; altera_reserved_tck ; Rise       ; USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|rom_com1:rom_com_inst|altsyncram:altsyncram_component|altsyncram_m5d1:auto_generated|sld_mod_ram_rom:mgl_prim2|is_in_use_reg                                                         ;
+--------+--------------+----------------+------------------+---------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'                                                                                                                        ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------+
; Slack   ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                                                 ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------+
; 99.418  ; 99.418       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 99.418  ; 99.418       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 99.420  ; 99.420       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                                   ;
; 99.420  ; 99.420       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|observablevcoout                         ;
; 99.449  ; 99.449       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                       ;
; 99.460  ; 99.460       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 99.462  ; 99.462       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|inclk[0]                                 ;
; 100.000 ; 100.000      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                       ;
; 100.000 ; 100.000      ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                       ;
; 100.538 ; 100.538      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|inclk[0]                                 ;
; 100.539 ; 100.539      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 100.551 ; 100.551      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                       ;
; 100.579 ; 100.579      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                                   ;
; 100.579 ; 100.579      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|observablevcoout                         ;
; 100.580 ; 100.580      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 100.580 ; 100.580      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 196.000 ; 200.000      ; 4.000          ; Port Rate        ; FPGA_CLK ; Rise       ; FPGA_CLK                                                                               ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                                            ;
+---------------------+---------------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port           ; Clock Port          ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+---------------------+---------------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]         ; FPGA_CLK            ; 1.419 ; 1.970 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]        ; FPGA_CLK            ; 1.405 ; 1.956 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]        ; FPGA_CLK            ; 1.405 ; 1.956 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]        ; FPGA_CLK            ; 1.405 ; 1.956 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]        ; FPGA_CLK            ; 1.407 ; 1.958 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]        ; FPGA_CLK            ; 1.417 ; 1.968 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]        ; FPGA_CLK            ; 1.409 ; 1.960 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]        ; FPGA_CLK            ; 1.407 ; 1.958 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]        ; FPGA_CLK            ; 1.385 ; 1.934 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]        ; FPGA_CLK            ; 1.413 ; 1.964 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]        ; FPGA_CLK            ; 1.419 ; 1.970 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]       ; FPGA_CLK            ; 1.414 ; 1.965 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]       ; FPGA_CLK            ; 1.414 ; 1.965 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]       ; FPGA_CLK            ; 1.414 ; 1.965 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]       ; FPGA_CLK            ; 1.407 ; 1.958 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]       ; FPGA_CLK            ; 1.407 ; 1.958 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]       ; FPGA_CLK            ; 1.407 ; 1.958 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_DAT0             ; FPGA_CLK            ; 1.912 ; 2.386 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; altera_reserved_tdi ; altera_reserved_tck ; 0.776 ; 1.209 ; Rise       ; altera_reserved_tck                                                           ;
; altera_reserved_tms ; altera_reserved_tck ; 3.041 ; 3.458 ; Rise       ; altera_reserved_tck                                                           ;
; dminus1             ; FPGA_CLK            ; 1.984 ; 2.756 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dminus2             ; FPGA_CLK            ; 0.630 ; 1.375 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1              ; FPGA_CLK            ; 2.296 ; 3.105 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2              ; FPGA_CLK            ; 0.639 ; 1.357 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1              ; FPGA_CLK            ; 2.550 ; 3.358 ; Fall       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2              ; FPGA_CLK            ; 0.636 ; 1.373 ; Fall       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
+---------------------+---------------------+-------+-------+------------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                               ;
+---------------------+---------------------+--------+--------+------------+-------------------------------------------------------------------------------+
; Data Port           ; Clock Port          ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                               ;
+---------------------+---------------------+--------+--------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]         ; FPGA_CLK            ; -0.937 ; -1.486 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]        ; FPGA_CLK            ; -0.956 ; -1.507 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]        ; FPGA_CLK            ; -0.956 ; -1.507 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]        ; FPGA_CLK            ; -0.956 ; -1.507 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]        ; FPGA_CLK            ; -0.958 ; -1.509 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]        ; FPGA_CLK            ; -0.968 ; -1.519 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]        ; FPGA_CLK            ; -0.960 ; -1.511 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]        ; FPGA_CLK            ; -0.958 ; -1.509 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]        ; FPGA_CLK            ; -0.937 ; -1.486 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]        ; FPGA_CLK            ; -0.964 ; -1.515 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]        ; FPGA_CLK            ; -0.970 ; -1.521 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]       ; FPGA_CLK            ; -0.965 ; -1.516 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]       ; FPGA_CLK            ; -0.965 ; -1.516 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]       ; FPGA_CLK            ; -0.965 ; -1.516 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]       ; FPGA_CLK            ; -0.958 ; -1.509 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]       ; FPGA_CLK            ; -0.958 ; -1.509 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]       ; FPGA_CLK            ; -0.958 ; -1.509 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_DAT0             ; FPGA_CLK            ; -1.419 ; -1.896 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; altera_reserved_tdi ; altera_reserved_tck ; 0.869  ; 0.413  ; Rise       ; altera_reserved_tck                                                           ;
; altera_reserved_tms ; altera_reserved_tck ; -0.260 ; -0.663 ; Rise       ; altera_reserved_tck                                                           ;
; dminus1             ; FPGA_CLK            ; -1.564 ; -2.329 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dminus2             ; FPGA_CLK            ; -0.163 ; -0.902 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1              ; FPGA_CLK            ; -1.880 ; -2.680 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2              ; FPGA_CLK            ; -0.186 ; -0.899 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1              ; FPGA_CLK            ; -1.900 ; -2.701 ; Fall       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2              ; FPGA_CLK            ; -0.088 ; -0.808 ; Fall       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
+---------------------+---------------------+--------+--------+------------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                                    ;
+---------------------+---------------------+--------+--------+------------+-------------------------------------------------------------------------------+
; Data Port           ; Clock Port          ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                               ;
+---------------------+---------------------+--------+--------+------------+-------------------------------------------------------------------------------+
; SDRAM_A[*]          ; FPGA_CLK            ; 3.442  ; 3.819  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]         ; FPGA_CLK            ; 1.672  ; 1.577  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]         ; FPGA_CLK            ; 1.672  ; 1.577  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]         ; FPGA_CLK            ; 1.675  ; 1.580  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]         ; FPGA_CLK            ; 1.675  ; 1.580  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]         ; FPGA_CLK            ; 1.668  ; 1.573  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]         ; FPGA_CLK            ; 1.668  ; 1.573  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]         ; FPGA_CLK            ; 1.666  ; 1.571  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]         ; FPGA_CLK            ; 1.228  ; 1.202  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]         ; FPGA_CLK            ; 3.442  ; 3.819  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]         ; FPGA_CLK            ; 1.667  ; 1.572  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]        ; FPGA_CLK            ; 1.672  ; 1.577  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]        ; FPGA_CLK            ; 1.667  ; 1.572  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]         ; FPGA_CLK            ; 3.449  ; 3.826  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]        ; FPGA_CLK            ; 3.449  ; 3.826  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]        ; FPGA_CLK            ; 1.235  ; 1.209  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N         ; FPGA_CLK            ; 1.237  ; 1.211  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N          ; FPGA_CLK            ; 1.674  ; 1.579  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]         ; FPGA_CLK            ; 3.089  ; 3.564  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]        ; FPGA_CLK            ; 1.918  ; 1.876  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]        ; FPGA_CLK            ; 1.918  ; 1.876  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]        ; FPGA_CLK            ; 1.918  ; 1.876  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]        ; FPGA_CLK            ; 3.089  ; 3.564  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]        ; FPGA_CLK            ; 3.079  ; 3.554  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]        ; FPGA_CLK            ; 1.311  ; 1.372  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]        ; FPGA_CLK            ; 1.771  ; 1.767  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]        ; FPGA_CLK            ; 1.674  ; 1.579  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]        ; FPGA_CLK            ; 1.910  ; 1.868  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]        ; FPGA_CLK            ; 3.077  ; 3.552  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]       ; FPGA_CLK            ; 1.909  ; 1.867  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]       ; FPGA_CLK            ; 1.909  ; 1.867  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]       ; FPGA_CLK            ; 1.909  ; 1.867  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]       ; FPGA_CLK            ; 3.089  ; 3.564  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]       ; FPGA_CLK            ; 1.916  ; 1.874  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]       ; FPGA_CLK            ; 1.916  ; 1.874  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH_n        ; FPGA_CLK            ; 1.668  ; 1.573  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML_n        ; FPGA_CLK            ; 1.674  ; 1.579  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N         ; FPGA_CLK            ; 1.674  ; 1.579  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N          ; FPGA_CLK            ; 3.451  ; 3.828  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L             ; FPGA_CLK            ; 3.513  ; 4.027  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R             ; FPGA_CLK            ; 1.584  ; 1.601  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK              ; FPGA_CLK            ; 2.521  ; 2.675  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD              ; FPGA_CLK            ; 2.281  ; 2.410  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3             ; FPGA_CLK            ; 2.587  ; 2.438  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK           ; FPGA_CLK            ; 10.169 ;        ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK           ; FPGA_CLK            ;        ; 10.643 ; Fall       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]            ; FPGA_CLK            ; 3.005  ; 3.451  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[0]           ; FPGA_CLK            ; 1.230  ; 1.204  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[1]           ; FPGA_CLK            ; 3.005  ; 3.451  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[2]           ; FPGA_CLK            ; 1.228  ; 1.202  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[3]           ; FPGA_CLK            ; 1.231  ; 1.205  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
; VGA_G[*]            ; FPGA_CLK            ; 3.007  ; 3.453  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[0]           ; FPGA_CLK            ; 1.230  ; 1.204  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[1]           ; FPGA_CLK            ; 1.230  ; 1.204  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[2]           ; FPGA_CLK            ; 1.230  ; 1.204  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[3]           ; FPGA_CLK            ; 3.007  ; 3.453  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
; altera_reserved_tdo ; altera_reserved_tck ; 6.722  ; 7.468  ; Fall       ; altera_reserved_tck                                                           ;
; dminus1             ; FPGA_CLK            ; 3.028  ; 3.147  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dminus2             ; FPGA_CLK            ; 3.958  ; 4.098  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1              ; FPGA_CLK            ; 5.314  ; 4.725  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2              ; FPGA_CLK            ; 4.128  ; 3.979  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
+---------------------+---------------------+--------+--------+------------+-------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                                           ;
+---------------------+---------------------+-------+--------+------------+-------------------------------------------------------------------------------+
; Data Port           ; Clock Port          ; Rise  ; Fall   ; Clock Edge ; Clock Reference                                                               ;
+---------------------+---------------------+-------+--------+------------+-------------------------------------------------------------------------------+
; SDRAM_A[*]          ; FPGA_CLK            ; 0.844 ; 0.818  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]         ; FPGA_CLK            ; 1.270 ; 1.178  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]         ; FPGA_CLK            ; 1.270 ; 1.178  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]         ; FPGA_CLK            ; 1.273 ; 1.181  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]         ; FPGA_CLK            ; 1.273 ; 1.181  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]         ; FPGA_CLK            ; 1.266 ; 1.174  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]         ; FPGA_CLK            ; 1.266 ; 1.174  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]         ; FPGA_CLK            ; 1.264 ; 1.172  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]         ; FPGA_CLK            ; 0.844 ; 0.818  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]         ; FPGA_CLK            ; 3.040 ; 3.420  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]         ; FPGA_CLK            ; 1.265 ; 1.173  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]        ; FPGA_CLK            ; 1.270 ; 1.178  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]        ; FPGA_CLK            ; 1.265 ; 1.173  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]         ; FPGA_CLK            ; 0.851 ; 0.825  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]        ; FPGA_CLK            ; 3.047 ; 3.427  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]        ; FPGA_CLK            ; 0.851 ; 0.825  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N         ; FPGA_CLK            ; 0.853 ; 0.827  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N          ; FPGA_CLK            ; 1.272 ; 1.180  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]         ; FPGA_CLK            ; 0.927 ; 0.989  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]        ; FPGA_CLK            ; 1.516 ; 1.478  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]        ; FPGA_CLK            ; 1.516 ; 1.478  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]        ; FPGA_CLK            ; 1.516 ; 1.478  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]        ; FPGA_CLK            ; 2.705 ; 3.181  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]        ; FPGA_CLK            ; 2.695 ; 3.171  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]        ; FPGA_CLK            ; 0.927 ; 0.989  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]        ; FPGA_CLK            ; 1.369 ; 1.369  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]        ; FPGA_CLK            ; 1.272 ; 1.180  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]        ; FPGA_CLK            ; 1.508 ; 1.470  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]        ; FPGA_CLK            ; 2.693 ; 3.169  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]       ; FPGA_CLK            ; 1.507 ; 1.469  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]       ; FPGA_CLK            ; 1.507 ; 1.469  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]       ; FPGA_CLK            ; 1.507 ; 1.469  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]       ; FPGA_CLK            ; 2.705 ; 3.181  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]       ; FPGA_CLK            ; 1.514 ; 1.476  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]       ; FPGA_CLK            ; 1.514 ; 1.476  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH_n        ; FPGA_CLK            ; 1.266 ; 1.174  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML_n        ; FPGA_CLK            ; 1.272 ; 1.180  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N         ; FPGA_CLK            ; 1.272 ; 1.180  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N          ; FPGA_CLK            ; 3.049 ; 3.429  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L             ; FPGA_CLK            ; 3.064 ; 3.576  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R             ; FPGA_CLK            ; 1.141 ; 1.156  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK              ; FPGA_CLK            ; 2.041 ; 2.188  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD              ; FPGA_CLK            ; 1.811 ; 1.934  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3             ; FPGA_CLK            ; 2.103 ; 1.961  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK           ; FPGA_CLK            ; 9.754 ;        ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK           ; FPGA_CLK            ;       ; 10.226 ; Fall       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]            ; FPGA_CLK            ; 0.844 ; 0.818  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[0]           ; FPGA_CLK            ; 0.846 ; 0.820  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[1]           ; FPGA_CLK            ; 2.621 ; 3.067  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[2]           ; FPGA_CLK            ; 0.844 ; 0.818  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[3]           ; FPGA_CLK            ; 0.847 ; 0.821  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
; VGA_G[*]            ; FPGA_CLK            ; 0.846 ; 0.820  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[0]           ; FPGA_CLK            ; 0.846 ; 0.820  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[1]           ; FPGA_CLK            ; 0.846 ; 0.820  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[2]           ; FPGA_CLK            ; 0.846 ; 0.820  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[3]           ; FPGA_CLK            ; 2.623 ; 3.069  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
; altera_reserved_tdo ; altera_reserved_tck ; 5.537 ; 6.286  ; Fall       ; altera_reserved_tck                                                           ;
; dminus1             ; FPGA_CLK            ; 2.711 ; 2.826  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dminus2             ; FPGA_CLK            ; 3.596 ; 3.733  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1              ; FPGA_CLK            ; 4.990 ; 4.405  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2              ; FPGA_CLK            ; 3.762 ; 3.617  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
+---------------------+---------------------+-------+--------+------------+-------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.708 ; 1.707 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.035 ; 2.034 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.035 ; 2.034 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.035 ; 2.034 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.892 ; 4.339 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 4.079 ; 4.526 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.133 ; 2.166 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.139 ; 2.172 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.206 ; 2.151 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.191 ; 2.190 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.671 ; 4.118 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.870 ; 1.869 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.870 ; 1.869 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.870 ; 1.869 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 3.339 ; 3.786 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.708 ; 1.707 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.708 ; 1.707 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.416 ; 2.361 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 2.865 ; 2.864 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dminus2       ; FPGA_CLK   ; 3.984 ; 4.017 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1        ; FPGA_CLK   ; 4.547 ; 4.994 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2        ; FPGA_CLK   ; 4.061 ; 4.094 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                             ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.276 ; 1.275 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.590 ; 1.589 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.590 ; 1.589 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.590 ; 1.589 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.439 ; 3.886 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.617 ; 4.064 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 1.679 ; 1.712 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 1.685 ; 1.718 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 1.738 ; 1.683 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 1.740 ; 1.739 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.226 ; 3.673 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.432 ; 1.431 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.432 ; 1.431 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.432 ; 1.431 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.907 ; 3.354 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.276 ; 1.275 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.276 ; 1.275 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 1.939 ; 1.884 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 2.560 ; 2.559 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dminus2       ; FPGA_CLK   ; 3.627 ; 3.660 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1        ; FPGA_CLK   ; 4.240 ; 4.687 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2        ; FPGA_CLK   ; 3.701 ; 3.734 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                            ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.746     ; 1.747     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.122     ; 2.123     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.122     ; 2.123     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.122     ; 2.123     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 4.469     ; 4.022     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 4.674     ; 4.227     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.285     ; 2.252     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.303     ; 2.270     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.295     ; 2.350     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.289     ; 2.290     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 4.206     ; 3.759     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.934     ; 1.935     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.934     ; 1.935     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.934     ; 1.935     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 3.825     ; 3.378     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.746     ; 1.747     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.746     ; 1.747     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.549     ; 2.604     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 2.942     ; 2.943     ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dminus2       ; FPGA_CLK   ; 4.090     ; 4.057     ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1        ; FPGA_CLK   ; 5.089     ; 4.642     ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2        ; FPGA_CLK   ; 4.172     ; 4.139     ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                                    ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.313     ; 1.314     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.673     ; 1.674     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.673     ; 1.674     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.673     ; 1.674     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 4.010     ; 3.563     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 4.207     ; 3.760     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 1.826     ; 1.793     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 1.843     ; 1.810     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 1.821     ; 1.876     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 1.834     ; 1.835     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.757     ; 3.310     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.493     ; 1.494     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.493     ; 1.494     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.493     ; 1.494     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 3.391     ; 2.944     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.313     ; 1.314     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.313     ; 1.314     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.064     ; 2.119     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 2.633     ; 2.634     ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dminus2       ; FPGA_CLK   ; 3.730     ; 3.697     ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1        ; FPGA_CLK   ; 4.777     ; 4.330     ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2        ; FPGA_CLK   ; 3.809     ; 3.776     ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+


---------------------------------------------
; Fast 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+----------------------------------------------------------------------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary                                                                                                          ;
+--------------------------------------------------------------------------------+----------+-------+----------+---------+---------------------+
; Clock                                                                          ; Setup    ; Hold  ; Recovery ; Removal ; Minimum Pulse Width ;
+--------------------------------------------------------------------------------+----------+-------+----------+---------+---------------------+
; Worst-case Slack                                                               ; -8.084   ; 0.141 ; 6.765    ; -0.036  ; 4.128               ;
;  FPGA_CLK                                                                      ; N/A      ; N/A   ; N/A      ; N/A     ; 99.418              ;
;  \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.263   ; 0.188 ; 7.798    ; 1.107   ; 5.583               ;
;  \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; -8.084   ; 0.159 ; 6.765    ; 0.694   ; 17.323              ;
;  \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 4.395    ; 0.141 ; N/A      ; N/A     ; 4.128               ;
;  \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]  ; N/A      ; N/A   ; N/A      ; N/A     ; 17.589              ;
;  altera_reserved_tck                                                           ; 45.292   ; 0.187 ; 47.801   ; 0.585   ; 49.295              ;
;  mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ; 25.894   ; 0.185 ; 63.166   ; -0.036  ; 32.979              ;
; Design-wide TNS                                                                ; -912.937 ; 0.0   ; 0.0      ; -0.981  ; 0.0                 ;
;  FPGA_CLK                                                                      ; N/A      ; N/A   ; N/A      ; N/A     ; 0.000               ;
;  \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.507   ; 0.000 ; 0.000    ; 0.000   ; 0.000               ;
;  \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; -912.430 ; 0.000 ; 0.000    ; 0.000   ; 0.000               ;
;  \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 0.000    ; 0.000 ; N/A      ; N/A     ; 0.000               ;
;  \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]  ; N/A      ; N/A   ; N/A      ; N/A     ; 0.000               ;
;  altera_reserved_tck                                                           ; 0.000    ; 0.000 ; 0.000    ; 0.000   ; 0.000               ;
;  mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ; 0.000    ; 0.000 ; 0.000    ; -0.981  ; 0.000               ;
+--------------------------------------------------------------------------------+----------+-------+----------+---------+---------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                                            ;
+---------------------+---------------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port           ; Clock Port          ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+---------------------+---------------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]         ; FPGA_CLK            ; 2.724 ; 2.903 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]        ; FPGA_CLK            ; 2.705 ; 2.884 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]        ; FPGA_CLK            ; 2.705 ; 2.884 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]        ; FPGA_CLK            ; 2.705 ; 2.884 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]        ; FPGA_CLK            ; 2.708 ; 2.887 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]        ; FPGA_CLK            ; 2.717 ; 2.896 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]        ; FPGA_CLK            ; 2.709 ; 2.888 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]        ; FPGA_CLK            ; 2.708 ; 2.887 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]        ; FPGA_CLK            ; 2.656 ; 2.834 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]        ; FPGA_CLK            ; 2.717 ; 2.896 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]        ; FPGA_CLK            ; 2.724 ; 2.903 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]       ; FPGA_CLK            ; 2.719 ; 2.898 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]       ; FPGA_CLK            ; 2.719 ; 2.898 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]       ; FPGA_CLK            ; 2.719 ; 2.898 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]       ; FPGA_CLK            ; 2.706 ; 2.885 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]       ; FPGA_CLK            ; 2.706 ; 2.885 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]       ; FPGA_CLK            ; 2.706 ; 2.885 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_DAT0             ; FPGA_CLK            ; 3.609 ; 3.785 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; altera_reserved_tdi ; altera_reserved_tck ; 2.250 ; 2.475 ; Rise       ; altera_reserved_tck                                                           ;
; altera_reserved_tms ; altera_reserved_tck ; 7.467 ; 7.629 ; Rise       ; altera_reserved_tck                                                           ;
; dminus1             ; FPGA_CLK            ; 3.767 ; 4.210 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dminus2             ; FPGA_CLK            ; 1.134 ; 1.527 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1              ; FPGA_CLK            ; 4.452 ; 4.920 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2              ; FPGA_CLK            ; 1.160 ; 1.573 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1              ; FPGA_CLK            ; 5.018 ; 5.462 ; Fall       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2              ; FPGA_CLK            ; 1.342 ; 1.765 ; Fall       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
+---------------------+---------------------+-------+-------+------------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                               ;
+---------------------+---------------------+--------+--------+------------+-------------------------------------------------------------------------------+
; Data Port           ; Clock Port          ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                               ;
+---------------------+---------------------+--------+--------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]         ; FPGA_CLK            ; -0.937 ; -1.486 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]        ; FPGA_CLK            ; -0.956 ; -1.507 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]        ; FPGA_CLK            ; -0.956 ; -1.507 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]        ; FPGA_CLK            ; -0.956 ; -1.507 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]        ; FPGA_CLK            ; -0.958 ; -1.509 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]        ; FPGA_CLK            ; -0.968 ; -1.519 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]        ; FPGA_CLK            ; -0.960 ; -1.511 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]        ; FPGA_CLK            ; -0.958 ; -1.509 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]        ; FPGA_CLK            ; -0.937 ; -1.486 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]        ; FPGA_CLK            ; -0.964 ; -1.515 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]        ; FPGA_CLK            ; -0.970 ; -1.521 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]       ; FPGA_CLK            ; -0.965 ; -1.516 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]       ; FPGA_CLK            ; -0.965 ; -1.516 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]       ; FPGA_CLK            ; -0.965 ; -1.516 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]       ; FPGA_CLK            ; -0.958 ; -1.509 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]       ; FPGA_CLK            ; -0.958 ; -1.509 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]       ; FPGA_CLK            ; -0.958 ; -1.509 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_DAT0             ; FPGA_CLK            ; -1.419 ; -1.896 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; altera_reserved_tdi ; altera_reserved_tck ; 1.223  ; 1.081  ; Rise       ; altera_reserved_tck                                                           ;
; altera_reserved_tms ; altera_reserved_tck ; -0.260 ; -0.663 ; Rise       ; altera_reserved_tck                                                           ;
; dminus1             ; FPGA_CLK            ; -1.564 ; -2.329 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dminus2             ; FPGA_CLK            ; -0.070 ; -0.365 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1              ; FPGA_CLK            ; -1.880 ; -2.680 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2              ; FPGA_CLK            ; -0.125 ; -0.447 ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1              ; FPGA_CLK            ; -1.900 ; -2.701 ; Fall       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2              ; FPGA_CLK            ; -0.088 ; -0.485 ; Fall       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
+---------------------+---------------------+--------+--------+------------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                                    ;
+---------------------+---------------------+--------+--------+------------+-------------------------------------------------------------------------------+
; Data Port           ; Clock Port          ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                               ;
+---------------------+---------------------+--------+--------+------------+-------------------------------------------------------------------------------+
; SDRAM_A[*]          ; FPGA_CLK            ; 5.688  ; 5.935  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]         ; FPGA_CLK            ; 3.084  ; 2.871  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]         ; FPGA_CLK            ; 3.084  ; 2.871  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]         ; FPGA_CLK            ; 3.087  ; 2.874  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]         ; FPGA_CLK            ; 3.087  ; 2.874  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]         ; FPGA_CLK            ; 3.074  ; 2.861  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]         ; FPGA_CLK            ; 3.074  ; 2.861  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]         ; FPGA_CLK            ; 3.072  ; 2.859  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]         ; FPGA_CLK            ; 2.251  ; 2.177  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]         ; FPGA_CLK            ; 5.688  ; 5.935  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]         ; FPGA_CLK            ; 3.073  ; 2.860  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]        ; FPGA_CLK            ; 3.084  ; 2.871  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]        ; FPGA_CLK            ; 3.073  ; 2.860  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]         ; FPGA_CLK            ; 5.701  ; 5.948  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]        ; FPGA_CLK            ; 5.701  ; 5.948  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]        ; FPGA_CLK            ; 2.264  ; 2.190  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N         ; FPGA_CLK            ; 2.265  ; 2.191  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N          ; FPGA_CLK            ; 3.085  ; 2.872  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]         ; FPGA_CLK            ; 5.026  ; 5.450  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]        ; FPGA_CLK            ; 3.455  ; 3.310  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]        ; FPGA_CLK            ; 3.455  ; 3.310  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]        ; FPGA_CLK            ; 3.455  ; 3.310  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]        ; FPGA_CLK            ; 5.024  ; 5.448  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]        ; FPGA_CLK            ; 5.015  ; 5.439  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]        ; FPGA_CLK            ; 2.410  ; 2.389  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]        ; FPGA_CLK            ; 3.272  ; 3.118  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]        ; FPGA_CLK            ; 3.086  ; 2.873  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]        ; FPGA_CLK            ; 3.443  ; 3.298  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]        ; FPGA_CLK            ; 5.008  ; 5.432  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]       ; FPGA_CLK            ; 3.441  ; 3.296  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]       ; FPGA_CLK            ; 3.441  ; 3.296  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]       ; FPGA_CLK            ; 3.441  ; 3.296  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]       ; FPGA_CLK            ; 5.026  ; 5.450  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]       ; FPGA_CLK            ; 3.454  ; 3.309  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]       ; FPGA_CLK            ; 3.454  ; 3.309  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH_n        ; FPGA_CLK            ; 3.074  ; 2.861  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML_n        ; FPGA_CLK            ; 3.086  ; 2.873  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N         ; FPGA_CLK            ; 3.085  ; 2.872  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N          ; FPGA_CLK            ; 5.703  ; 5.950  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L             ; FPGA_CLK            ; 5.983  ; 6.371  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R             ; FPGA_CLK            ; 3.057  ; 2.978  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK              ; FPGA_CLK            ; 4.937  ; 4.874  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD              ; FPGA_CLK            ; 4.416  ; 4.390  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3             ; FPGA_CLK            ; 4.720  ; 4.760  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK           ; FPGA_CLK            ; 11.898 ;        ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK           ; FPGA_CLK            ;        ; 12.246 ; Fall       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]            ; FPGA_CLK            ; 4.868  ; 5.254  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[0]           ; FPGA_CLK            ; 2.252  ; 2.178  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[1]           ; FPGA_CLK            ; 4.868  ; 5.254  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[2]           ; FPGA_CLK            ; 2.251  ; 2.177  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[3]           ; FPGA_CLK            ; 2.254  ; 2.180  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
; VGA_G[*]            ; FPGA_CLK            ; 4.870  ; 5.256  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[0]           ; FPGA_CLK            ; 2.253  ; 2.179  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[1]           ; FPGA_CLK            ; 2.253  ; 2.179  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[2]           ; FPGA_CLK            ; 2.253  ; 2.179  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[3]           ; FPGA_CLK            ; 4.870  ; 5.256  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
; altera_reserved_tdo ; altera_reserved_tck ; 12.491 ; 13.517 ; Fall       ; altera_reserved_tck                                                           ;
; dminus1             ; FPGA_CLK            ; 5.783  ; 5.760  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dminus2             ; FPGA_CLK            ; 7.734  ; 7.732  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1              ; FPGA_CLK            ; 8.753  ; 8.312  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2              ; FPGA_CLK            ; 7.773  ; 7.771  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
+---------------------+---------------------+--------+--------+------------+-------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                                           ;
+---------------------+---------------------+-------+--------+------------+-------------------------------------------------------------------------------+
; Data Port           ; Clock Port          ; Rise  ; Fall   ; Clock Edge ; Clock Reference                                                               ;
+---------------------+---------------------+-------+--------+------------+-------------------------------------------------------------------------------+
; SDRAM_A[*]          ; FPGA_CLK            ; 0.844 ; 0.818  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]         ; FPGA_CLK            ; 1.270 ; 1.178  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]         ; FPGA_CLK            ; 1.270 ; 1.178  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]         ; FPGA_CLK            ; 1.273 ; 1.181  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]         ; FPGA_CLK            ; 1.273 ; 1.181  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]         ; FPGA_CLK            ; 1.266 ; 1.174  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]         ; FPGA_CLK            ; 1.266 ; 1.174  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]         ; FPGA_CLK            ; 1.264 ; 1.172  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]         ; FPGA_CLK            ; 0.844 ; 0.818  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]         ; FPGA_CLK            ; 3.040 ; 3.420  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]         ; FPGA_CLK            ; 1.265 ; 1.173  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]        ; FPGA_CLK            ; 1.270 ; 1.178  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]        ; FPGA_CLK            ; 1.265 ; 1.173  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]         ; FPGA_CLK            ; 0.851 ; 0.825  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]        ; FPGA_CLK            ; 3.047 ; 3.427  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]        ; FPGA_CLK            ; 0.851 ; 0.825  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N         ; FPGA_CLK            ; 0.853 ; 0.827  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N          ; FPGA_CLK            ; 1.272 ; 1.180  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]         ; FPGA_CLK            ; 0.927 ; 0.989  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]        ; FPGA_CLK            ; 1.516 ; 1.478  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]        ; FPGA_CLK            ; 1.516 ; 1.478  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]        ; FPGA_CLK            ; 1.516 ; 1.478  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]        ; FPGA_CLK            ; 2.705 ; 3.181  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]        ; FPGA_CLK            ; 2.695 ; 3.171  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]        ; FPGA_CLK            ; 0.927 ; 0.989  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]        ; FPGA_CLK            ; 1.369 ; 1.369  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]        ; FPGA_CLK            ; 1.272 ; 1.180  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]        ; FPGA_CLK            ; 1.508 ; 1.470  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]        ; FPGA_CLK            ; 2.693 ; 3.169  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]       ; FPGA_CLK            ; 1.507 ; 1.469  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]       ; FPGA_CLK            ; 1.507 ; 1.469  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]       ; FPGA_CLK            ; 1.507 ; 1.469  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]       ; FPGA_CLK            ; 2.705 ; 3.181  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]       ; FPGA_CLK            ; 1.514 ; 1.476  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]       ; FPGA_CLK            ; 1.514 ; 1.476  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH_n        ; FPGA_CLK            ; 1.266 ; 1.174  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML_n        ; FPGA_CLK            ; 1.272 ; 1.180  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N         ; FPGA_CLK            ; 1.272 ; 1.180  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N          ; FPGA_CLK            ; 3.049 ; 3.429  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L             ; FPGA_CLK            ; 3.064 ; 3.576  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R             ; FPGA_CLK            ; 1.141 ; 1.156  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK              ; FPGA_CLK            ; 2.041 ; 2.188  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD              ; FPGA_CLK            ; 1.811 ; 1.934  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3             ; FPGA_CLK            ; 2.103 ; 1.961  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK           ; FPGA_CLK            ; 9.754 ;        ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK           ; FPGA_CLK            ;       ; 10.226 ; Fall       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]            ; FPGA_CLK            ; 0.844 ; 0.818  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[0]           ; FPGA_CLK            ; 0.846 ; 0.820  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[1]           ; FPGA_CLK            ; 2.621 ; 3.067  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[2]           ; FPGA_CLK            ; 0.844 ; 0.818  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_B[3]           ; FPGA_CLK            ; 0.847 ; 0.821  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
; VGA_G[*]            ; FPGA_CLK            ; 0.846 ; 0.820  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[0]           ; FPGA_CLK            ; 0.846 ; 0.820  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[1]           ; FPGA_CLK            ; 0.846 ; 0.820  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[2]           ; FPGA_CLK            ; 0.846 ; 0.820  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
;  VGA_G[3]           ; FPGA_CLK            ; 2.623 ; 3.069  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ;
; altera_reserved_tdo ; altera_reserved_tck ; 5.537 ; 6.286  ; Fall       ; altera_reserved_tck                                                           ;
; dminus1             ; FPGA_CLK            ; 2.711 ; 2.826  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dminus2             ; FPGA_CLK            ; 3.596 ; 3.733  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus1              ; FPGA_CLK            ; 4.990 ; 4.405  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
; dplus2              ; FPGA_CLK            ; 3.762 ; 3.617  ; Rise       ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ;
+---------------------+---------------------+-------+--------+------------+-------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                          ;
+---------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; Pin                 ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
+---------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; VGA_B[0]            ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[1]            ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[2]            ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[3]            ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[0]            ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[1]            ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[2]            ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[3]            ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; AUDIO_L             ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; AUDIO_R             ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_BA[0]         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_BA[1]         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_CS_N          ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_RAS_N         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_CAS_N         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_WE_N          ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQMH_n        ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQML_n        ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_CLK           ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_CKE           ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[0]          ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[1]          ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[2]          ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[3]          ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[4]          ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[5]          ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[6]          ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[7]          ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[8]          ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[9]          ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[10]         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[11]         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[12]         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SD_CLK              ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SD_CMD              ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SD_DAT3             ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; CFG_CLK             ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; CFG_CS_n            ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; CFG_DOUT            ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; dplus1              ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; dminus1             ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; dplus2              ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; dminus2             ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[0]         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[1]         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[2]         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[3]         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[4]         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[5]         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[6]         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[7]         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[8]         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[9]         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[10]        ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[11]        ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[12]        ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[13]        ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[14]        ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[15]        ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; altera_reserved_tdo ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+---------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+


+------------------------------------------------------------------------+
; Input Transition Times                                                 ;
+---------------------+--------------+-----------------+-----------------+
; Pin                 ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+---------------------+--------------+-----------------+-----------------+
; CFG_DIN             ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; dplus1              ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; dminus1             ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; dplus2              ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; dminus2             ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[0]         ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[1]         ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[2]         ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[3]         ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[4]         ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[5]         ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[6]         ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[7]         ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[8]         ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[9]         ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[10]        ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[11]        ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[12]        ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[13]        ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[14]        ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[15]        ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; FPGA_CLK            ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SD_DAT0             ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; altera_reserved_tms ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; altera_reserved_tck ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; altera_reserved_tdi ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
+---------------------+--------------+-----------------+-----------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1200mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin                 ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; VGA_B[0]            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; VGA_B[1]            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.09 V              ; -0.00419 V          ; 0.108 V                              ; 0.251 V                              ; 5.73e-09 s                  ; 5.85e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.69e-08 V                  ; 3.09 V             ; -0.00419 V         ; 0.108 V                             ; 0.251 V                             ; 5.73e-09 s                 ; 5.85e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[2]            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; VGA_B[3]            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; VGA_G[0]            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; VGA_G[1]            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; VGA_G[2]            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; VGA_G[3]            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.09 V              ; -0.00419 V          ; 0.108 V                              ; 0.251 V                              ; 5.73e-09 s                  ; 5.85e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.69e-08 V                  ; 3.09 V             ; -0.00419 V         ; 0.108 V                             ; 0.251 V                             ; 5.73e-09 s                 ; 5.85e-09 s                 ; Yes                       ; Yes                       ;
; AUDIO_L             ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.09 V              ; -0.00419 V          ; 0.108 V                              ; 0.251 V                              ; 5.73e-09 s                  ; 5.85e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.69e-08 V                  ; 3.09 V             ; -0.00419 V         ; 0.108 V                             ; 0.251 V                             ; 5.73e-09 s                 ; 5.85e-09 s                 ; Yes                       ; Yes                       ;
; AUDIO_R             ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_BA[0]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.09 V              ; -0.00419 V          ; 0.108 V                              ; 0.251 V                              ; 5.73e-09 s                  ; 5.85e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.69e-08 V                  ; 3.09 V             ; -0.00419 V         ; 0.108 V                             ; 0.251 V                             ; 5.73e-09 s                 ; 5.85e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_BA[1]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_CS_N          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_RAS_N         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_CAS_N         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_WE_N          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.09 V              ; -0.00419 V          ; 0.108 V                              ; 0.251 V                              ; 5.73e-09 s                  ; 5.85e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.69e-08 V                  ; 3.09 V             ; -0.00419 V         ; 0.108 V                             ; 0.251 V                             ; 5.73e-09 s                 ; 5.85e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQMH_n        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_DQML_n        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_CLK           ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.09 V              ; -0.00419 V          ; 0.108 V                              ; 0.251 V                              ; 5.73e-09 s                  ; 5.85e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.69e-08 V                  ; 3.09 V             ; -0.00419 V         ; 0.108 V                             ; 0.251 V                             ; 5.73e-09 s                 ; 5.85e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_CKE           ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[0]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[1]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[2]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[3]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[4]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[5]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[6]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[7]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[8]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.09 V              ; -0.00419 V          ; 0.108 V                              ; 0.251 V                              ; 5.73e-09 s                  ; 5.85e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.69e-08 V                  ; 3.09 V             ; -0.00419 V         ; 0.108 V                             ; 0.251 V                             ; 5.73e-09 s                 ; 5.85e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[9]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[10]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[11]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[12]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SD_CLK              ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SD_CMD              ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SD_DAT3             ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; CFG_CLK             ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.15e-09 V                   ; 3.18 V              ; -0.0303 V           ; 0.317 V                              ; 0.07 V                               ; 3.25e-10 s                  ; 3.88e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 6.15e-09 V                  ; 3.18 V             ; -0.0303 V          ; 0.317 V                             ; 0.07 V                              ; 3.25e-10 s                 ; 3.88e-10 s                 ; No                        ; Yes                       ;
; CFG_CS_n            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.76e-08 V                   ; 3.09 V              ; -0.0166 V           ; 0.084 V                              ; 0.289 V                              ; 2.05e-09 s                  ; 1.96e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.76e-08 V                  ; 3.09 V             ; -0.0166 V          ; 0.084 V                             ; 0.289 V                             ; 2.05e-09 s                 ; 1.96e-09 s                 ; Yes                       ; Yes                       ;
; CFG_DOUT            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.76e-08 V                   ; 3.09 V              ; -0.0166 V           ; 0.084 V                              ; 0.289 V                              ; 2.05e-09 s                  ; 1.96e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.76e-08 V                  ; 3.09 V             ; -0.0166 V          ; 0.084 V                             ; 0.289 V                             ; 2.05e-09 s                 ; 1.96e-09 s                 ; Yes                       ; Yes                       ;
; dplus1              ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.09 V              ; -0.00398 V          ; 0.168 V                              ; 0.263 V                              ; 6.02e-09 s                  ; 6.14e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.09 V             ; -0.00398 V         ; 0.168 V                             ; 0.263 V                             ; 6.02e-09 s                 ; 6.14e-09 s                 ; Yes                       ; Yes                       ;
; dminus1             ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0249 V           ; 0.153 V                              ; 0.299 V                              ; 1.37e-09 s                  ; 1.36e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0249 V          ; 0.153 V                             ; 0.299 V                             ; 1.37e-09 s                 ; 1.36e-09 s                 ; Yes                       ; Yes                       ;
; dplus2              ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0307 V           ; 0.185 V                              ; 0.216 V                              ; 1.07e-09 s                  ; 1.08e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0307 V          ; 0.185 V                             ; 0.216 V                             ; 1.07e-09 s                 ; 1.08e-09 s                 ; Yes                       ; Yes                       ;
; dminus2             ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0307 V           ; 0.185 V                              ; 0.216 V                              ; 1.07e-09 s                  ; 1.08e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0307 V          ; 0.185 V                             ; 0.216 V                             ; 1.07e-09 s                 ; 1.08e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[0]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0249 V           ; 0.153 V                              ; 0.299 V                              ; 1.37e-09 s                  ; 1.36e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0249 V          ; 0.153 V                             ; 0.299 V                             ; 1.37e-09 s                 ; 1.36e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[1]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0249 V           ; 0.153 V                              ; 0.299 V                              ; 1.37e-09 s                  ; 1.36e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0249 V          ; 0.153 V                             ; 0.299 V                             ; 1.37e-09 s                 ; 1.36e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[2]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0249 V           ; 0.153 V                              ; 0.299 V                              ; 1.37e-09 s                  ; 1.36e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0249 V          ; 0.153 V                             ; 0.299 V                             ; 1.37e-09 s                 ; 1.36e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[3]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.09 V              ; -0.00398 V          ; 0.168 V                              ; 0.263 V                              ; 6.02e-09 s                  ; 6.14e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.09 V             ; -0.00398 V         ; 0.168 V                             ; 0.263 V                             ; 6.02e-09 s                 ; 6.14e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[4]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.09 V              ; -0.00398 V          ; 0.168 V                              ; 0.263 V                              ; 6.02e-09 s                  ; 6.14e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.09 V             ; -0.00398 V         ; 0.168 V                             ; 0.263 V                             ; 6.02e-09 s                 ; 6.14e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[5]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0307 V           ; 0.185 V                              ; 0.216 V                              ; 1.07e-09 s                  ; 1.08e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0307 V          ; 0.185 V                             ; 0.216 V                             ; 1.07e-09 s                 ; 1.08e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[6]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0307 V           ; 0.185 V                              ; 0.216 V                              ; 1.07e-09 s                  ; 1.08e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0307 V          ; 0.185 V                             ; 0.216 V                             ; 1.07e-09 s                 ; 1.08e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[7]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_DQ[8]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0249 V           ; 0.153 V                              ; 0.299 V                              ; 1.37e-09 s                  ; 1.36e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0249 V          ; 0.153 V                             ; 0.299 V                             ; 1.37e-09 s                 ; 1.36e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[9]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.09 V              ; -0.00398 V          ; 0.168 V                              ; 0.263 V                              ; 6.02e-09 s                  ; 6.14e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.09 V             ; -0.00398 V         ; 0.168 V                             ; 0.263 V                             ; 6.02e-09 s                 ; 6.14e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[10]        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0249 V           ; 0.153 V                              ; 0.299 V                              ; 1.37e-09 s                  ; 1.36e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0249 V          ; 0.153 V                             ; 0.299 V                             ; 1.37e-09 s                 ; 1.36e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[11]        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0249 V           ; 0.153 V                              ; 0.299 V                              ; 1.37e-09 s                  ; 1.36e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0249 V          ; 0.153 V                             ; 0.299 V                             ; 1.37e-09 s                 ; 1.36e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[12]        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0249 V           ; 0.153 V                              ; 0.299 V                              ; 1.37e-09 s                  ; 1.36e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0249 V          ; 0.153 V                             ; 0.299 V                             ; 1.37e-09 s                 ; 1.36e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[13]        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.09 V              ; -0.00398 V          ; 0.168 V                              ; 0.263 V                              ; 6.02e-09 s                  ; 6.14e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.09 V             ; -0.00398 V         ; 0.168 V                             ; 0.263 V                             ; 6.02e-09 s                 ; 6.14e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[14]        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0249 V           ; 0.153 V                              ; 0.299 V                              ; 1.37e-09 s                  ; 1.36e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0249 V          ; 0.153 V                             ; 0.299 V                             ; 1.37e-09 s                 ; 1.36e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[15]        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0249 V           ; 0.153 V                              ; 0.299 V                              ; 1.37e-09 s                  ; 1.36e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0249 V          ; 0.153 V                             ; 0.299 V                             ; 1.37e-09 s                 ; 1.36e-09 s                 ; Yes                       ; Yes                       ;
; altera_reserved_tdo ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.09e-08 V                   ; 3.11 V              ; 5.09e-08 V          ; 0.193 V                              ; 0.27 V                               ; 1.07e-09 s                  ; 2.77e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 5.09e-08 V                  ; 3.11 V             ; 5.09e-08 V         ; 0.193 V                             ; 0.27 V                              ; 1.07e-09 s                 ; 2.77e-09 s                 ; Yes                       ; Yes                       ;
+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1200mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin                 ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; VGA_B[0]            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; VGA_B[1]            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.00169 V          ; 0.058 V                              ; 0.159 V                              ; 6.95e-09 s                  ; 7.33e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.00169 V         ; 0.058 V                             ; 0.159 V                             ; 6.95e-09 s                 ; 7.33e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[2]            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; VGA_B[3]            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; VGA_G[0]            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; VGA_G[1]            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; VGA_G[2]            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; VGA_G[3]            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.00169 V          ; 0.058 V                              ; 0.159 V                              ; 6.95e-09 s                  ; 7.33e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.00169 V         ; 0.058 V                             ; 0.159 V                             ; 6.95e-09 s                 ; 7.33e-09 s                 ; Yes                       ; Yes                       ;
; AUDIO_L             ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.00169 V          ; 0.058 V                              ; 0.159 V                              ; 6.95e-09 s                  ; 7.33e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.00169 V         ; 0.058 V                             ; 0.159 V                             ; 6.95e-09 s                 ; 7.33e-09 s                 ; Yes                       ; Yes                       ;
; AUDIO_R             ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_BA[0]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.00169 V          ; 0.058 V                              ; 0.159 V                              ; 6.95e-09 s                  ; 7.33e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.00169 V         ; 0.058 V                             ; 0.159 V                             ; 6.95e-09 s                 ; 7.33e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_BA[1]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_CS_N          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_RAS_N         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_CAS_N         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_WE_N          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.00169 V          ; 0.058 V                              ; 0.159 V                              ; 6.95e-09 s                  ; 7.33e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.00169 V         ; 0.058 V                             ; 0.159 V                             ; 6.95e-09 s                 ; 7.33e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQMH_n        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQML_n        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_CLK           ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.00169 V          ; 0.058 V                              ; 0.159 V                              ; 6.95e-09 s                  ; 7.33e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.00169 V         ; 0.058 V                             ; 0.159 V                             ; 6.95e-09 s                 ; 7.33e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_CKE           ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[0]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[1]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[2]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[3]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[4]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[5]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[6]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[7]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[8]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.00169 V          ; 0.058 V                              ; 0.159 V                              ; 6.95e-09 s                  ; 7.33e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.00169 V         ; 0.058 V                             ; 0.159 V                             ; 6.95e-09 s                 ; 7.33e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[9]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[10]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[11]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[12]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SD_CLK              ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SD_CMD              ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SD_DAT3             ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; CFG_CLK             ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.52e-07 V                   ; 3.14 V              ; -0.0428 V           ; 0.161 V                              ; 0.071 V                              ; 4.71e-10 s                  ; 4.5e-10 s                   ; Yes                        ; Yes                        ; 3.08 V                      ; 6.52e-07 V                  ; 3.14 V             ; -0.0428 V          ; 0.161 V                             ; 0.071 V                             ; 4.71e-10 s                 ; 4.5e-10 s                  ; Yes                       ; Yes                       ;
; CFG_CS_n            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.13e-06 V                   ; 3.08 V              ; -0.00721 V          ; 0.043 V                              ; 0.226 V                              ; 2.47e-09 s                  ; 2.5e-09 s                   ; Yes                        ; Yes                        ; 3.08 V                      ; 3.13e-06 V                  ; 3.08 V             ; -0.00721 V         ; 0.043 V                             ; 0.226 V                             ; 2.47e-09 s                 ; 2.5e-09 s                  ; Yes                       ; Yes                       ;
; CFG_DOUT            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.13e-06 V                   ; 3.08 V              ; -0.00721 V          ; 0.043 V                              ; 0.226 V                              ; 2.47e-09 s                  ; 2.5e-09 s                   ; Yes                        ; Yes                        ; 3.08 V                      ; 3.13e-06 V                  ; 3.08 V             ; -0.00721 V         ; 0.043 V                             ; 0.226 V                             ; 2.47e-09 s                 ; 2.5e-09 s                  ; Yes                       ; Yes                       ;
; dplus1              ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.00144 V          ; 0.08 V                               ; 0.174 V                              ; 7.33e-09 s                  ; 7.73e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.00144 V         ; 0.08 V                              ; 0.174 V                             ; 7.33e-09 s                 ; 7.73e-09 s                 ; Yes                       ; Yes                       ;
; dminus1             ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.012 V            ; 0.078 V                              ; 0.167 V                              ; 1.65e-09 s                  ; 1.74e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.012 V           ; 0.078 V                             ; 0.167 V                             ; 1.65e-09 s                 ; 1.74e-09 s                 ; Yes                       ; Yes                       ;
; dplus2              ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.0139 V           ; 0.07 V                               ; 0.155 V                              ; 1.28e-09 s                  ; 1.32e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.0139 V          ; 0.07 V                              ; 0.155 V                             ; 1.28e-09 s                 ; 1.32e-09 s                 ; Yes                       ; Yes                       ;
; dminus2             ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.0139 V           ; 0.07 V                               ; 0.155 V                              ; 1.28e-09 s                  ; 1.32e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.0139 V          ; 0.07 V                              ; 0.155 V                             ; 1.28e-09 s                 ; 1.32e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[0]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.012 V            ; 0.078 V                              ; 0.167 V                              ; 1.65e-09 s                  ; 1.74e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.012 V           ; 0.078 V                             ; 0.167 V                             ; 1.65e-09 s                 ; 1.74e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[1]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.012 V            ; 0.078 V                              ; 0.167 V                              ; 1.65e-09 s                  ; 1.74e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.012 V           ; 0.078 V                             ; 0.167 V                             ; 1.65e-09 s                 ; 1.74e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[2]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.012 V            ; 0.078 V                              ; 0.167 V                              ; 1.65e-09 s                  ; 1.74e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.012 V           ; 0.078 V                             ; 0.167 V                             ; 1.65e-09 s                 ; 1.74e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[3]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.00144 V          ; 0.08 V                               ; 0.174 V                              ; 7.33e-09 s                  ; 7.73e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.00144 V         ; 0.08 V                              ; 0.174 V                             ; 7.33e-09 s                 ; 7.73e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[4]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.00144 V          ; 0.08 V                               ; 0.174 V                              ; 7.33e-09 s                  ; 7.73e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.00144 V         ; 0.08 V                              ; 0.174 V                             ; 7.33e-09 s                 ; 7.73e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[5]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.0139 V           ; 0.07 V                               ; 0.155 V                              ; 1.28e-09 s                  ; 1.32e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.0139 V          ; 0.07 V                              ; 0.155 V                             ; 1.28e-09 s                 ; 1.32e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[6]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.0139 V           ; 0.07 V                               ; 0.155 V                              ; 1.28e-09 s                  ; 1.32e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.0139 V          ; 0.07 V                              ; 0.155 V                             ; 1.28e-09 s                 ; 1.32e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[7]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[8]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.012 V            ; 0.078 V                              ; 0.167 V                              ; 1.65e-09 s                  ; 1.74e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.012 V           ; 0.078 V                             ; 0.167 V                             ; 1.65e-09 s                 ; 1.74e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[9]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.00144 V          ; 0.08 V                               ; 0.174 V                              ; 7.33e-09 s                  ; 7.73e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.00144 V         ; 0.08 V                              ; 0.174 V                             ; 7.33e-09 s                 ; 7.73e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[10]        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.012 V            ; 0.078 V                              ; 0.167 V                              ; 1.65e-09 s                  ; 1.74e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.012 V           ; 0.078 V                             ; 0.167 V                             ; 1.65e-09 s                 ; 1.74e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[11]        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.012 V            ; 0.078 V                              ; 0.167 V                              ; 1.65e-09 s                  ; 1.74e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.012 V           ; 0.078 V                             ; 0.167 V                             ; 1.65e-09 s                 ; 1.74e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[12]        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.012 V            ; 0.078 V                              ; 0.167 V                              ; 1.65e-09 s                  ; 1.74e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.012 V           ; 0.078 V                             ; 0.167 V                             ; 1.65e-09 s                 ; 1.74e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[13]        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.00144 V          ; 0.08 V                               ; 0.174 V                              ; 7.33e-09 s                  ; 7.73e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.00144 V         ; 0.08 V                              ; 0.174 V                             ; 7.33e-09 s                 ; 7.73e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[14]        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.012 V            ; 0.078 V                              ; 0.167 V                              ; 1.65e-09 s                  ; 1.74e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.012 V           ; 0.078 V                             ; 0.167 V                             ; 1.65e-09 s                 ; 1.74e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[15]        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.012 V            ; 0.078 V                              ; 0.167 V                              ; 1.65e-09 s                  ; 1.74e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.012 V           ; 0.078 V                             ; 0.167 V                             ; 1.65e-09 s                 ; 1.74e-09 s                 ; Yes                       ; Yes                       ;
; altera_reserved_tdo ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.8e-06 V                    ; 3.09 V              ; 5.8e-06 V           ; 0.119 V                              ; 0.138 V                              ; 1.28e-09 s                  ; 3.52e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 5.8e-06 V                   ; 3.09 V             ; 5.8e-06 V          ; 0.119 V                             ; 0.138 V                             ; 1.28e-09 s                 ; 3.52e-09 s                 ; Yes                       ; Yes                       ;
+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Fast 1200mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin                 ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; VGA_B[0]            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_B[1]            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.47 V              ; -0.00753 V          ; 0.323 V                              ; 0.336 V                              ; 4.77e-09 s                  ; 5.18e-09 s                  ; Yes                        ; No                         ; 3.46 V                      ; 3.12e-07 V                  ; 3.47 V             ; -0.00753 V         ; 0.323 V                             ; 0.336 V                             ; 4.77e-09 s                 ; 5.18e-09 s                 ; Yes                       ; No                        ;
; VGA_B[2]            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_B[3]            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_G[0]            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_G[1]            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_G[2]            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_G[3]            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.47 V              ; -0.00753 V          ; 0.323 V                              ; 0.336 V                              ; 4.77e-09 s                  ; 5.18e-09 s                  ; Yes                        ; No                         ; 3.46 V                      ; 3.12e-07 V                  ; 3.47 V             ; -0.00753 V         ; 0.323 V                             ; 0.336 V                             ; 4.77e-09 s                 ; 5.18e-09 s                 ; Yes                       ; No                        ;
; AUDIO_L             ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.47 V              ; -0.00753 V          ; 0.323 V                              ; 0.336 V                              ; 4.77e-09 s                  ; 5.18e-09 s                  ; Yes                        ; No                         ; 3.46 V                      ; 3.12e-07 V                  ; 3.47 V             ; -0.00753 V         ; 0.323 V                             ; 0.336 V                             ; 4.77e-09 s                 ; 5.18e-09 s                 ; Yes                       ; No                        ;
; AUDIO_R             ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_BA[0]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.47 V              ; -0.00753 V          ; 0.323 V                              ; 0.336 V                              ; 4.77e-09 s                  ; 5.18e-09 s                  ; Yes                        ; No                         ; 3.46 V                      ; 3.12e-07 V                  ; 3.47 V             ; -0.00753 V         ; 0.323 V                             ; 0.336 V                             ; 4.77e-09 s                 ; 5.18e-09 s                 ; Yes                       ; No                        ;
; SDRAM_BA[1]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_CS_N          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_RAS_N         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_CAS_N         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_WE_N          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.47 V              ; -0.00753 V          ; 0.323 V                              ; 0.336 V                              ; 4.77e-09 s                  ; 5.18e-09 s                  ; Yes                        ; No                         ; 3.46 V                      ; 3.12e-07 V                  ; 3.47 V             ; -0.00753 V         ; 0.323 V                             ; 0.336 V                             ; 4.77e-09 s                 ; 5.18e-09 s                 ; Yes                       ; No                        ;
; SDRAM_DQMH_n        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQML_n        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_CLK           ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.47 V              ; -0.00753 V          ; 0.323 V                              ; 0.336 V                              ; 4.77e-09 s                  ; 5.18e-09 s                  ; Yes                        ; No                         ; 3.46 V                      ; 3.12e-07 V                  ; 3.47 V             ; -0.00753 V         ; 0.323 V                             ; 0.336 V                             ; 4.77e-09 s                 ; 5.18e-09 s                 ; Yes                       ; No                        ;
; SDRAM_CKE           ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[0]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[1]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[2]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[3]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[4]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[5]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[6]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[7]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[8]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.47 V              ; -0.00753 V          ; 0.323 V                              ; 0.336 V                              ; 4.77e-09 s                  ; 5.18e-09 s                  ; Yes                        ; No                         ; 3.46 V                      ; 3.12e-07 V                  ; 3.47 V             ; -0.00753 V         ; 0.323 V                             ; 0.336 V                             ; 4.77e-09 s                 ; 5.18e-09 s                 ; Yes                       ; No                        ;
; SDRAM_A[9]          ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[10]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[11]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[12]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SD_CLK              ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SD_CMD              ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SD_DAT3             ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; CFG_CLK             ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 6.59e-08 V                   ; 3.58 V              ; -0.0703 V           ; 0.234 V                              ; 0.091 V                              ; 2.93e-10 s                  ; 3.09e-10 s                  ; Yes                        ; Yes                        ; 3.46 V                      ; 6.59e-08 V                  ; 3.58 V             ; -0.0703 V          ; 0.234 V                             ; 0.091 V                             ; 2.93e-10 s                 ; 3.09e-10 s                 ; Yes                       ; Yes                       ;
; CFG_CS_n            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.08e-07 V                   ; 3.48 V              ; -0.026 V            ; 0.261 V                              ; 0.327 V                              ; 1.74e-09 s                  ; 1.77e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 3.08e-07 V                  ; 3.48 V             ; -0.026 V           ; 0.261 V                             ; 0.327 V                             ; 1.74e-09 s                 ; 1.77e-09 s                 ; No                        ; No                        ;
; CFG_DOUT            ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.08e-07 V                   ; 3.48 V              ; -0.026 V            ; 0.261 V                              ; 0.327 V                              ; 1.74e-09 s                  ; 1.77e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 3.08e-07 V                  ; 3.48 V             ; -0.026 V           ; 0.261 V                             ; 0.327 V                             ; 1.74e-09 s                 ; 1.77e-09 s                 ; No                        ; No                        ;
; dplus1              ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.47 V              ; -0.00704 V          ; 0.325 V                              ; 0.344 V                              ; 5.02e-09 s                  ; 5.44e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.47 V             ; -0.00704 V         ; 0.325 V                             ; 0.344 V                             ; 5.02e-09 s                 ; 5.44e-09 s                 ; No                        ; No                        ;
; dminus1             ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.5 V               ; -0.041 V            ; 0.29 V                               ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.5 V              ; -0.041 V           ; 0.29 V                              ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; dplus2              ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.51 V              ; -0.0513 V           ; 0.246 V                              ; 0.327 V                              ; 8.76e-10 s                  ; 8.99e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.51 V             ; -0.0513 V          ; 0.246 V                             ; 0.327 V                             ; 8.76e-10 s                 ; 8.99e-10 s                 ; No                        ; No                        ;
; dminus2             ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.51 V              ; -0.0513 V           ; 0.246 V                              ; 0.327 V                              ; 8.76e-10 s                  ; 8.99e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.51 V             ; -0.0513 V          ; 0.246 V                             ; 0.327 V                             ; 8.76e-10 s                 ; 8.99e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[0]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.5 V               ; -0.041 V            ; 0.29 V                               ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.5 V              ; -0.041 V           ; 0.29 V                              ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[1]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.5 V               ; -0.041 V            ; 0.29 V                               ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.5 V              ; -0.041 V           ; 0.29 V                              ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[2]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.5 V               ; -0.041 V            ; 0.29 V                               ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.5 V              ; -0.041 V           ; 0.29 V                              ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[3]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.47 V              ; -0.00704 V          ; 0.325 V                              ; 0.344 V                              ; 5.02e-09 s                  ; 5.44e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.47 V             ; -0.00704 V         ; 0.325 V                             ; 0.344 V                             ; 5.02e-09 s                 ; 5.44e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[4]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.47 V              ; -0.00704 V          ; 0.325 V                              ; 0.344 V                              ; 5.02e-09 s                  ; 5.44e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.47 V             ; -0.00704 V         ; 0.325 V                             ; 0.344 V                             ; 5.02e-09 s                 ; 5.44e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[5]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.51 V              ; -0.0513 V           ; 0.246 V                              ; 0.327 V                              ; 8.76e-10 s                  ; 8.99e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.51 V             ; -0.0513 V          ; 0.246 V                             ; 0.327 V                             ; 8.76e-10 s                 ; 8.99e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[6]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.51 V              ; -0.0513 V           ; 0.246 V                              ; 0.327 V                              ; 8.76e-10 s                  ; 8.99e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.51 V             ; -0.0513 V          ; 0.246 V                             ; 0.327 V                             ; 8.76e-10 s                 ; 8.99e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[7]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[8]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.5 V               ; -0.041 V            ; 0.29 V                               ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.5 V              ; -0.041 V           ; 0.29 V                              ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[9]         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.47 V              ; -0.00704 V          ; 0.325 V                              ; 0.344 V                              ; 5.02e-09 s                  ; 5.44e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.47 V             ; -0.00704 V         ; 0.325 V                             ; 0.344 V                             ; 5.02e-09 s                 ; 5.44e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[10]        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.5 V               ; -0.041 V            ; 0.29 V                               ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.5 V              ; -0.041 V           ; 0.29 V                              ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[11]        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.5 V               ; -0.041 V            ; 0.29 V                               ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.5 V              ; -0.041 V           ; 0.29 V                              ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[12]        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.5 V               ; -0.041 V            ; 0.29 V                               ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.5 V              ; -0.041 V           ; 0.29 V                              ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[13]        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.47 V              ; -0.00704 V          ; 0.325 V                              ; 0.344 V                              ; 5.02e-09 s                  ; 5.44e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.47 V             ; -0.00704 V         ; 0.325 V                             ; 0.344 V                             ; 5.02e-09 s                 ; 5.44e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[14]        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.5 V               ; -0.041 V            ; 0.29 V                               ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.5 V              ; -0.041 V           ; 0.29 V                              ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[15]        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.5 V               ; -0.041 V            ; 0.29 V                               ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.5 V              ; -0.041 V           ; 0.29 V                              ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; altera_reserved_tdo ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 5.7e-07 V                    ; 3.51 V              ; -0.00915 V          ; 0.24 V                               ; 0.283 V                              ; 8.77e-10 s                  ; 2.48e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 5.7e-07 V                   ; 3.51 V             ; -0.00915 V         ; 0.24 V                              ; 0.283 V                             ; 8.77e-10 s                 ; 2.48e-09 s                 ; No                        ; No                        ;
+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Transfers                                                                                                                                                                                           ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                                    ; To Clock                                                                      ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------+----------+----------+----------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1847     ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 128688   ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 6547     ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 22471885 ; 0        ; 0        ; 0        ;
; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 794      ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 117      ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 224      ; 0        ; 0        ; 0        ;
; altera_reserved_tck                                                           ; altera_reserved_tck                                                           ; 1908     ; 0        ; 35       ; 0        ;
; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ; 3350     ; 140      ; 1681     ; 10369    ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Transfers                                                                                                                                                                                            ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                                    ; To Clock                                                                      ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------+----------+----------+----------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1847     ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 128688   ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 6547     ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 22471885 ; 0        ; 0        ; 0        ;
; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 794      ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 117      ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] ; 224      ; 0        ; 0        ; 0        ;
; altera_reserved_tck                                                           ; altera_reserved_tck                                                           ; 1908     ; 0        ; 35       ; 0        ;
; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ; 3350     ; 140      ; 1681     ; 10369    ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Recovery Transfers                                                                                                                                                                                        ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                                    ; To Clock                                                                      ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------+----------+----------+----------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 146      ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 508      ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 1748     ; 0        ; 0        ; 0        ;
; altera_reserved_tck                                                           ; altera_reserved_tck                                                           ; 88       ; 0        ; 1        ; 0        ;
; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ; 62       ; 0        ; 0        ; 0        ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Removal Transfers                                                                                                                                                                                         ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                                    ; To Clock                                                                      ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------+----------+----------+----------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 146      ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 508      ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 1748     ; 0        ; 0        ; 0        ;
; altera_reserved_tck                                                           ; altera_reserved_tck                                                           ; 88       ; 0        ; 1        ; 0        ;
; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ; mcc_pll3|altpll_component|auto_generated|pll1|clk[0]                          ; 62       ; 0        ; 0        ; 0        ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design


---------------
; Report RSKM ;
---------------
No dedicated SERDES Receiver circuitry present in device or used in design


+------------------------------------------------+
; Unconstrained Paths                            ;
+---------------------------------+-------+------+
; Property                        ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks                  ; 0     ; 0    ;
; Unconstrained Clocks            ; 3     ; 3    ;
; Unconstrained Input Ports       ; 23    ; 23   ;
; Unconstrained Input Port Paths  ; 88    ; 88   ;
; Unconstrained Output Ports      ; 55    ; 55   ;
; Unconstrained Output Port Paths ; 76    ; 76   ;
+---------------------------------+-------+------+


+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II 32-bit TimeQuest Timing Analyzer
    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
    Info: Processing started: Sat Nov  8 23:40:26 2014
Info: Command: quartus_sta atari800core -c atari800core
Info: qsta_default_script.tcl version: #1
Info (11104): Parallel Compilation has detected 4 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 2 of the 2 physical processors detected instead.
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Warning (335093): TimeQuest Timing Analyzer is analyzing 6 combinational loops as latches.
Info (332164): Evaluating HDL-embedded SDC commands
    Info (332165): Entity sld_jtag_hub
        Info (332166): create_clock -name altera_reserved_tck [get_ports {altera_reserved_tck}] -period 10MHz   
        Info (332166): set_clock_groups -asynchronous -group {altera_reserved_tck}
Info (332104): Reading SDC File: 'atari800core.sdc'
Info (332110): Deriving PLL clocks
    Info (332110): create_generated_clock -source {\gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 40 -multiply_by 227 -duty_cycle 50.00 -name {\gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]} {\gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]}
    Info (332110): create_generated_clock -source {\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 3 -duty_cycle 50.00 -name {\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]} {\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]}
    Info (332110): create_generated_clock -source {\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]} -duty_cycle 50.00 -name {\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]} {\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]}
    Info (332110): create_generated_clock -source {\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 3 -phase 225.00 -duty_cycle 50.00 -name {\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]} {\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]}
    Info (332110): create_generated_clock -source {\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 4 -duty_cycle 50.00 -name {\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3]} {\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3]}
    Info (332110): create_generated_clock -source {mcc_pll3|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 3 -duty_cycle 50.00 -name {mcc_pll3|altpll_component|auto_generated|pll1|clk[0]} {mcc_pll3|altpll_component|auto_generated|pll1|clk[0]}
Info (332151): Clock uncertainty is not calculated until you update the timing netlist.
Warning (332060): Node: USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|reg_10bits[4] was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: reset_usbdrv was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|reg_10bits[4] was determined to be a clock but was found without an associated clock assignment.
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Analyzing Slow 1200mV 85C Model
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -8.084
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -8.084      -912.430 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    -0.263        -0.507 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     4.395         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] 
    Info (332119):    25.894         0.000 mcc_pll3|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    45.292         0.000 altera_reserved_tck 
Info (332146): Worst-case hold slack is 0.355
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.355         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] 
    Info (332119):     0.380         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.412         0.000 mcc_pll3|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.413         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.413         0.000 altera_reserved_tck 
Info (332146): Worst-case recovery slack is 6.765
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     6.765         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     7.798         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    47.801         0.000 altera_reserved_tck 
    Info (332119):    63.166         0.000 mcc_pll3|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case removal slack is -0.012
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -0.012        -0.217 mcc_pll3|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     1.254         0.000 altera_reserved_tck 
    Info (332119):     1.451         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     2.199         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case minimum pulse width slack is 4.128
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     4.128         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] 
    Info (332119):     5.598         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    17.342         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    17.594         0.000 \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    33.028         0.000 mcc_pll3|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    49.479         0.000 altera_reserved_tck 
    Info (332119):    99.796         0.000 FPGA_CLK 
Info: Analyzing Slow 1200mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Warning (332060): Node: USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|reg_10bits[4] was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: reset_usbdrv was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|reg_10bits[4] was determined to be a clock but was found without an associated clock assignment.
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -7.366
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -7.366      -824.594 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.668         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     4.783         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] 
    Info (332119):    26.607         0.000 mcc_pll3|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    45.838         0.000 altera_reserved_tck 
Info (332146): Worst-case hold slack is 0.329
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.329         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] 
    Info (332119):     0.350         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.362         0.000 altera_reserved_tck 
    Info (332119):     0.363         0.000 mcc_pll3|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.364         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case recovery slack is 7.260
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     7.260         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     8.197         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    48.098         0.000 altera_reserved_tck 
    Info (332119):    63.499         0.000 mcc_pll3|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case removal slack is -0.036
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -0.036        -0.981 mcc_pll3|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     1.150         0.000 altera_reserved_tck 
    Info (332119):     1.311         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     1.973         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case minimum pulse width slack is 4.129
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     4.129         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] 
    Info (332119):     5.583         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    17.323         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    17.589         0.000 \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    32.979         0.000 mcc_pll3|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    49.393         0.000 altera_reserved_tck 
    Info (332119):    99.778         0.000 FPGA_CLK 
Info: Analyzing Fast 1200mV 0C Model
Warning (332060): Node: USBF_IFC1:UUSB_1|USB_DRVR1:UDRVR|reg_10bits[4] was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: reset_usbdrv was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: USBF_IFC2:UUSB_2|USB_DRVR2:UDRVR|reg_10bits[4] was determined to be a clock but was found without an associated clock assignment.
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -3.915
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -3.915      -445.217 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     5.587         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     6.602         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] 
    Info (332119):    29.519         0.000 mcc_pll3|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    47.974         0.000 altera_reserved_tck 
Info (332146): Worst-case hold slack is 0.141
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.141         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] 
    Info (332119):     0.159         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.185         0.000 mcc_pll3|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.187         0.000 altera_reserved_tck 
    Info (332119):     0.188         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case recovery slack is 9.208
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     9.208         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     9.725         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    49.197         0.000 altera_reserved_tck 
    Info (332119):    64.844         0.000 mcc_pll3|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case removal slack is -0.015
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -0.015        -0.358 mcc_pll3|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.585         0.000 altera_reserved_tck 
    Info (332119):     0.694         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     1.107         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case minimum pulse width slack is 4.188
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     4.188         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[3] 
    Info (332119):     5.655         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    17.369         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    17.601         0.000 \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    33.024         0.000 mcc_pll3|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    49.295         0.000 altera_reserved_tck 
    Info (332119):    99.418         0.000 FPGA_CLK 
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 13 warnings
    Info: Peak virtual memory: 536 megabytes
    Info: Processing ended: Sat Nov  8 23:41:07 2014
    Info: Elapsed time: 00:00:41
    Info: Total CPU time (on all processors): 00:00:35


