Design Assistant report for atari5200core
Sat Nov  8 23:23:45 2014
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition


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; Table of Contents ;
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  1. Legal Notice
  2. Design Assistant Summary
  3. Design Assistant Settings
  4. High Violations
  5. Medium Violations
  6. Information only Violations
  7. Design Assistant Messages



----------------
; Legal Notice ;
----------------
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+-------------------------------------------------------------------------+
; Design Assistant Summary                                                ;
+-----------------------------------+-------------------------------------+
; Design Assistant Status           ; Analyzed - Sat Nov  8 23:23:45 2014 ;
; Revision Name                     ; atari5200core                       ;
; Top-level Entity Name             ; atari5200core_de1                   ;
; Family                            ; Cyclone II                          ;
; Total Critical Violations         ; 0                                   ;
; Total High Violations             ; 100                                 ;
; - Rule R101                       ; 2                                   ;
; - Rule D101                       ; 98                                  ;
; Total Medium Violations           ; 2                                   ;
; - Rule C104                       ; 1                                   ;
; - Rule C106                       ; 1                                   ;
; Total Information only Violations ; 196                                 ;
; - Rule T101                       ; 146                                 ;
; - Rule T102                       ; 50                                  ;
+-----------------------------------+-------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Design Assistant Settings                                                                                                                                                                                                                                                                                ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+----+
; Option                                                                                                                                                                                                                                                                               ; Setting      ; To ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+----+
; Design Assistant mode                                                                                                                                                                                                                                                                ; Post-Fitting ;    ;
; Threshold value for clock net not mapped to clock spines rule                                                                                                                                                                                                                        ; 25           ;    ;
; Minimum number of clock port feed by gated clocks                                                                                                                                                                                                                                    ; 30           ;    ;
; Minimum number of node fan-out                                                                                                                                                                                                                                                       ; 30           ;    ;
; Maximum number of nodes to report                                                                                                                                                                                                                                                    ; 50           ;    ;
; Rule C101: Gated clock should be implemented according to the Altera standard scheme                                                                                                                                                                                                 ; On           ;    ;
; Rule C102: Logic cell should not be used to generate an inverted clock signal                                                                                                                                                                                                        ; On           ;    ;
; Rule C103: Gated clock does not feed at least a pre-defined number of clock ports to effectively save power                                                                                                                                                                          ; On           ;    ;
; Rule C104: Clock signal source should drive only clock input ports                                                                                                                                                                                                                   ; On           ;    ;
; Rule C105: Clock signal should be a global signal (Rule applies during post-fitting analysis. This rule applies during both post-fitting analysis and post-synthesis analysis if the design targets a MAX 3000 or MAX 7000 device. For more information, see the Help for the rule.) ; On           ;    ;
; Rule C106: Clock signal source should not drive registers triggered by different clock edges                                                                                                                                                                                         ; On           ;    ;
; Rule R101: Combinational logic used as a reset signal should be synchronized                                                                                                                                                                                                         ; On           ;    ;
; Rule R102: External reset signals should be synchronized using two cascaded registers                                                                                                                                                                                                ; On           ;    ;
; Rule R103: External reset signal should be correctly synchronized                                                                                                                                                                                                                    ; On           ;    ;
; Rule R104: The reset signal that is generated in one clock domain and used in another clock domain should be correctly synchronized                                                                                                                                                  ; On           ;    ;
; Rule R105: The reset signal that is generated in one clock domain and used in another clock domain should be synchronized                                                                                                                                                            ; On           ;    ;
; Rule T101: Nodes with more than the specified number of fan-outs                                                                                                                                                                                                                     ; On           ;    ;
; Rule T102: Top nodes with the highest number of fan-outs                                                                                                                                                                                                                             ; On           ;    ;
; Rule A101: Design should not contain combinational loops                                                                                                                                                                                                                             ; On           ;    ;
; Rule A102: Register output should not drive its own control signal directly or through combinational logic                                                                                                                                                                           ; On           ;    ;
; Rule A103: Design should not contain delay chains                                                                                                                                                                                                                                    ; On           ;    ;
; Rule A104: Design should not contain ripple clock structures                                                                                                                                                                                                                         ; On           ;    ;
; Rule A105: Pulses should not be implemented asynchronously                                                                                                                                                                                                                           ; On           ;    ;
; Rule A106: Multiple pulses should not be generated in design                                                                                                                                                                                                                         ; On           ;    ;
; Rule A107: Design should not contain SR latches                                                                                                                                                                                                                                      ; On           ;    ;
; Rule A108: Design should not contain latches                                                                                                                                                                                                                                         ; On           ;    ;
; Rule S101: Output enable and input of the same tri-state node should not be driven by same signal source                                                                                                                                                                             ; On           ;    ;
; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source                                                                                                                                                                ; On           ;    ;
; Rule S103: More than one asynchronous port of a register should not be driven by the same signal source                                                                                                                                                                              ; On           ;    ;
; Rule S104: Clock port and any other port of a register should not be driven by the same signal source                                                                                                                                                                                ; On           ;    ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains                                                                                                                                                                                        ; On           ;    ;
; Rule D102: Multiple data bits that are transferred across asynchronous clock domains are synchronized, but not all bits may be aligned in the receiving clock domain                                                                                                                 ; On           ;    ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains                                                                                                                                                                              ; On           ;    ;
; Rule M101: Data bits are not synchronized when transferred to the state machine of asynchronous clock domains                                                                                                                                                                        ; Off          ;    ;
; Rule M102: No reset signal defined to initialize the state machine                                                                                                                                                                                                                   ; Off          ;    ;
; Rule M103: State machine should not contain an unreachable state                                                                                                                                                                                                                     ; Off          ;    ;
; Rule M104: State machine should not contain a deadlock state                                                                                                                                                                                                                         ; Off          ;    ;
; Rule M105: State machine should not contain a dead transition                                                                                                                                                                                                                        ; Off          ;    ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+----+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; High Violations                                                                                                                                                                       ;
+--------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------+
; Rule name                                                                                                    ; Name                                                                   ;
+--------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------+
; Rule R101: Combinational logic used as a reset signal should be synchronized                                 ; comb~1                                                                 ;
;  Reset signal destination node(s) list                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|mosi~en ;
; Rule R101: Combinational logic used as a reset signal should be synchronized                                 ; comb~0                                                                 ;
;  Reset signal destination node(s) list                                                                       ; atari5200core:atari5200|gtia:gtia1|HRCOLOUR_REG[7]                     ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 1  ;                                                                        ;
;  Source node(s) from clock "pll:pll|altpll:altpll_component|_clk0"                                           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                    ;
;  Destination node(s) from clock "pll:pll|altpll:altpll_component|_clk1"                                      ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 2  ;                                                                        ;
;  Source node(s) from clock "pll:pll|altpll:altpll_component|_clk0"                                           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                    ;
;  Destination node(s) from clock "pll:pll|altpll:altpll_component|_clk1"                                      ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 3  ;                                                                        ;
;  Source node(s) from clock "pll:pll|altpll:altpll_component|_clk0"                                           ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                    ;
;  Destination node(s) from clock "pll:pll|altpll:altpll_component|_clk1"                                      ; sdram_statemachine:sdram_adaptor|reset_client_n_reg                    ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 4  ;                                                                        ;
;  Source node(s) from clock "pll:pll|altpll:altpll_component|_clk1"                                           ; sdram_statemachine:sdram_adaptor|request_sreg                          ;
;  Destination node(s) from clock "pll:pll|altpll:altpll_component|_clk0"                                      ; sdram_statemachine:sdram_adaptor|sdram_state_reg[1]                    ;
;  Destination node(s) from clock "pll:pll|altpll:altpll_component|_clk0"                                      ; sdram_statemachine:sdram_adaptor|reply_reg                             ;
;  Destination node(s) from clock "pll:pll|altpll:altpll_component|_clk0"                                      ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                    ;
;  Destination node(s) from clock "pll:pll|altpll:altpll_component|_clk0"                                      ; sdram_statemachine:sdram_adaptor|sdram_state_reg[0]                    ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 5  ;                                                                        ;
;  Source node(s) from clock "pll:pll|altpll:altpll_component|_clk0"                                           ; sdram_statemachine:sdram_adaptor|reply_reg                             ;
;  Destination node(s) from clock "pll:pll|altpll:altpll_component|_clk1"                                      ; sdram_statemachine:sdram_adaptor|reply_sreg                            ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 6  ;                                                                        ;
;  Source node(s) from clock "pll:pll|altpll:altpll_component|_clk0"                                           ; sdram_statemachine:sdram_adaptor|data_out_reg[20]                      ;
;  Destination node(s) from clock "pll:pll|altpll:altpll_component|_clk1"                                      ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[20]                     ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 7  ;                                                                        ;
;  Source node(s) from clock "pll:pll|altpll:altpll_component|_clk1"                                           ; sdram_statemachine:sdram_adaptor|DATA_IN_sreg[4]                       ;
;  Destination node(s) from clock "pll:pll|altpll:altpll_component|_clk0"                                      ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]                        ;
;  Destination node(s) from clock "pll:pll|altpll:altpll_component|_clk0"                                      ; sdram_statemachine:sdram_adaptor|dq_out_reg[4]                         ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 8  ;                                                                        ;
;  Source node(s) from clock "pll:pll|altpll:altpll_component|_clk0"                                           ; sdram_statemachine:sdram_adaptor|data_out_reg[24]                      ;
;  Destination node(s) from clock "pll:pll|altpll:altpll_component|_clk1"                                      ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[24]                     ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 9  ;                                                                        ;
;  Source node(s) from clock "pll:pll|altpll:altpll_component|_clk1"                                           ; sdram_statemachine:sdram_adaptor|DATA_IN_sreg[24]                      ;
;  Destination node(s) from clock "pll:pll|altpll:altpll_component|_clk0"                                      ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]                         ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 10 ;                                                                        ;
;  Source node(s) from clock "pll:pll|altpll:altpll_component|_clk0"                                           ; sdram_statemachine:sdram_adaptor|data_out_reg[23]                      ;
;  Destination node(s) from clock "pll:pll|altpll:altpll_component|_clk1"                                      ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[23]                     ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 11 ;                                                                        ;
;  Source node(s) from clock "pll:pll|altpll:altpll_component|_clk1"                                           ; sdram_statemachine:sdram_adaptor|DATA_IN_sreg[7]                       ;
;  Destination node(s) from clock "pll:pll|altpll:altpll_component|_clk0"                                      ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                        ;
;  Destination node(s) from clock "pll:pll|altpll:altpll_component|_clk0"                                      ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                         ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 12 ;                                                                        ;
;  Source node(s) from clock "pll:pll|altpll:altpll_component|_clk1"                                           ; sdram_statemachine:sdram_adaptor|DATA_IN_sreg[23]                      ;
;  Destination node(s) from clock "pll:pll|altpll:altpll_component|_clk0"                                      ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                         ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 13 ;                                                                        ;
;  Source node(s) from clock "pll:pll|altpll:altpll_component|_clk1"                                           ; sdram_statemachine:sdram_adaptor|DATA_IN_sreg[15]                      ;
;  Destination node(s) from clock "pll:pll|altpll:altpll_component|_clk0"                                      ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                        ;
;  Destination node(s) from clock "pll:pll|altpll:altpll_component|_clk0"                                      ; sdram_statemachine:sdram_adaptor|dq_out_reg[7]                         ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 14 ;                                                                        ;
;  Source node(s) from clock "pll:pll|altpll:altpll_component|_clk1"                                           ; sdram_statemachine:sdram_adaptor|dqm_mask_sreg[0]                      ;
;  Destination node(s) from clock "pll:pll|altpll:altpll_component|_clk0"                                      ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]                        ;
;  Destination node(s) from clock "pll:pll|altpll:altpll_component|_clk0"                                      ; sdram_statemachine:sdram_adaptor|dq_out_reg[12]                        ;
;  Destination node(s) from clock "pll:pll|altpll:altpll_component|_clk0"                                      ; sdram_statemachine:sdram_adaptor|dq_out_reg[2]                         ;
;  Destination node(s) from clock "pll:pll|altpll:altpll_component|_clk0"                                      ; sdram_statemachine:sdram_adaptor|dq_out_reg[10]                        ;
;  Destination node(s) from clock "pll:pll|altpll:altpll_component|_clk0"                                      ; sdram_statemachine:sdram_adaptor|data_out_reg[2]                       ;
;  Destination node(s) from clock "pll:pll|altpll:altpll_component|_clk0"                                      ; sdram_statemachine:sdram_adaptor|dq_out_reg[0]                         ;
;  Destination node(s) from clock "pll:pll|altpll:altpll_component|_clk0"                                      ; sdram_statemachine:sdram_adaptor|data_out_reg[0]                       ;
;  Destination node(s) from clock "pll:pll|altpll:altpll_component|_clk0"                                      ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                         ;
;  Destination node(s) from clock "pll:pll|altpll:altpll_component|_clk0"                                      ; sdram_statemachine:sdram_adaptor|data_out_reg[6]                       ;
;  Destination node(s) from clock "pll:pll|altpll:altpll_component|_clk0"                                      ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                        ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 15 ;                                                                        ;
;  Source node(s) from clock "pll:pll|altpll:altpll_component|_clk0"                                           ; sdram_statemachine:sdram_adaptor|data_out_reg[19]                      ;
;  Destination node(s) from clock "pll:pll|altpll:altpll_component|_clk1"                                      ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[19]                     ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 16 ;                                                                        ;
;  Source node(s) from clock "pll:pll|altpll:altpll_component|_clk1"                                           ; sdram_statemachine:sdram_adaptor|DATA_IN_sreg[3]                       ;
;  Destination node(s) from clock "pll:pll|altpll:altpll_component|_clk0"                                      ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]                        ;
;  Destination node(s) from clock "pll:pll|altpll:altpll_component|_clk0"                                      ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                         ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 17 ;                                                                        ;
;  Source node(s) from clock "pll:pll|altpll:altpll_component|_clk1"                                           ; sdram_statemachine:sdram_adaptor|DATA_IN_sreg[19]                      ;
;  Destination node(s) from clock "pll:pll|altpll:altpll_component|_clk0"                                      ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                         ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 18 ;                                                                        ;
;  Source node(s) from clock "pll:pll|altpll:altpll_component|_clk1"                                           ; sdram_statemachine:sdram_adaptor|DATA_IN_sreg[11]                      ;
;  Destination node(s) from clock "pll:pll|altpll:altpll_component|_clk0"                                      ; sdram_statemachine:sdram_adaptor|dq_out_reg[11]                        ;
;  Destination node(s) from clock "pll:pll|altpll:altpll_component|_clk0"                                      ; sdram_statemachine:sdram_adaptor|dq_out_reg[3]                         ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 19 ;                                                                        ;
;  Source node(s) from clock "pll:pll|altpll:altpll_component|_clk0"                                           ; sdram_statemachine:sdram_adaptor|data_out_reg[30]                      ;
;  Destination node(s) from clock "pll:pll|altpll:altpll_component|_clk1"                                      ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[30]                     ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 20 ;                                                                        ;
;  Source node(s) from clock "pll:pll|altpll:altpll_component|_clk1"                                           ; sdram_statemachine:sdram_adaptor|DATA_IN_sreg[30]                      ;
;  Destination node(s) from clock "pll:pll|altpll:altpll_component|_clk0"                                      ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                        ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 21 ;                                                                        ;
;  Source node(s) from clock "pll:pll|altpll:altpll_component|_clk1"                                           ; sdram_statemachine:sdram_adaptor|DATA_IN_sreg[14]                      ;
;  Destination node(s) from clock "pll:pll|altpll:altpll_component|_clk0"                                      ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                         ;
;  Destination node(s) from clock "pll:pll|altpll:altpll_component|_clk0"                                      ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                        ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 22 ;                                                                        ;
;  Source node(s) from clock "pll:pll|altpll:altpll_component|_clk1"                                           ; sdram_statemachine:sdram_adaptor|DATA_IN_sreg[6]                       ;
;  Destination node(s) from clock "pll:pll|altpll:altpll_component|_clk0"                                      ; sdram_statemachine:sdram_adaptor|dq_out_reg[6]                         ;
;  Destination node(s) from clock "pll:pll|altpll:altpll_component|_clk0"                                      ; sdram_statemachine:sdram_adaptor|dq_out_reg[14]                        ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 23 ;                                                                        ;
;  Source node(s) from clock "pll:pll|altpll:altpll_component|_clk0"                                           ; sdram_statemachine:sdram_adaptor|data_out_reg[21]                      ;
;  Destination node(s) from clock "pll:pll|altpll:altpll_component|_clk1"                                      ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[21]                     ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 24 ;                                                                        ;
;  Source node(s) from clock "pll:pll|altpll:altpll_component|_clk1"                                           ; sdram_statemachine:sdram_adaptor|DATA_IN_sreg[5]                       ;
;  Destination node(s) from clock "pll:pll|altpll:altpll_component|_clk0"                                      ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]                         ;
;  Destination node(s) from clock "pll:pll|altpll:altpll_component|_clk0"                                      ; sdram_statemachine:sdram_adaptor|dq_out_reg[13]                        ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 25 ;                                                                        ;
;  Source node(s) from clock "pll:pll|altpll:altpll_component|_clk1"                                           ; sdram_statemachine:sdram_adaptor|DATA_IN_sreg[13]                      ;
;  Destination node(s) from clock "pll:pll|altpll:altpll_component|_clk0"                                      ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]                         ;
;  Destination node(s) from clock "pll:pll|altpll:altpll_component|_clk0"                                      ; sdram_statemachine:sdram_adaptor|dq_out_reg[13]                        ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 26 ;                                                                        ;
;  Source node(s) from clock "pll:pll|altpll:altpll_component|_clk1"                                           ; sdram_statemachine:sdram_adaptor|DATA_IN_sreg[21]                      ;
;  Destination node(s) from clock "pll:pll|altpll:altpll_component|_clk0"                                      ; sdram_statemachine:sdram_adaptor|dq_out_reg[5]                         ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 27 ;                                                                        ;
;  Source node(s) from clock "pll:pll|altpll:altpll_component|_clk0"                                           ; sdram_statemachine:sdram_adaptor|data_out_reg[31]                      ;
;  Destination node(s) from clock "pll:pll|altpll:altpll_component|_clk1"                                      ; sdram_statemachine:sdram_adaptor|DATA_OUT_sreg[31]                     ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 28 ;                                                                        ;
;  Source node(s) from clock "pll:pll|altpll:altpll_component|_clk1"                                           ; sdram_statemachine:sdram_adaptor|DATA_IN_sreg[31]                      ;
;  Destination node(s) from clock "pll:pll|altpll:altpll_component|_clk0"                                      ; sdram_statemachine:sdram_adaptor|dq_out_reg[15]                        ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 29 ;                                                                        ;
;  Source node(s) from clock "pll:pll|altpll:altpll_component|_clk1"                                           ; sdram_statemachine:sdram_adaptor|DATA_IN_sreg[8]                       ;
;  Destination node(s) from clock "pll:pll|altpll:altpll_component|_clk0"                                      ; sdram_statemachine:sdram_adaptor|dq_out_reg[0]                         ;
;  Destination node(s) from clock "pll:pll|altpll:altpll_component|_clk0"                                      ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]                         ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 30 ;                                                                        ;
;  Source node(s) from clock "pll:pll|altpll:altpll_component|_clk1"                                           ; sdram_statemachine:sdram_adaptor|DATA_IN_sreg[0]                       ;
;  Destination node(s) from clock "pll:pll|altpll:altpll_component|_clk0"                                      ; sdram_statemachine:sdram_adaptor|dq_out_reg[0]                         ;
;  Destination node(s) from clock "pll:pll|altpll:altpll_component|_clk0"                                      ; sdram_statemachine:sdram_adaptor|dq_out_reg[8]                         ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 31 ;                                                                        ;
;  Structure 31                                                                                                ; sdram_statemachine:sdram_adaptor|data_out_reg[5]                       ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 32 ;                                                                        ;
;  Structure 32                                                                                                ; sdram_statemachine:sdram_adaptor|DATA_IN_sreg[29]                      ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 33 ;                                                                        ;
;  Structure 33                                                                                                ; sdram_statemachine:sdram_adaptor|data_out_reg[7]                       ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 34 ;                                                                        ;
;  Structure 34                                                                                                ; sdram_statemachine:sdram_adaptor|data_out_reg[1]                       ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 35 ;                                                                        ;
;  Structure 35                                                                                                ; sdram_statemachine:sdram_adaptor|DATA_IN_sreg[1]                       ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 36 ;                                                                        ;
;  Structure 36                                                                                                ; sdram_statemachine:sdram_adaptor|DATA_IN_sreg[9]                       ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 37 ;                                                                        ;
;  Structure 37                                                                                                ; sdram_statemachine:sdram_adaptor|DATA_IN_sreg[17]                      ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 38 ;                                                                        ;
;  Structure 38                                                                                                ; sdram_statemachine:sdram_adaptor|DATA_IN_sreg[25]                      ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 39 ;                                                                        ;
;  Structure 39                                                                                                ; sdram_statemachine:sdram_adaptor|data_out_reg[6]                       ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 40 ;                                                                        ;
;  Structure 40                                                                                                ; sdram_statemachine:sdram_adaptor|DATA_IN_sreg[22]                      ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 41 ;                                                                        ;
;  Structure 41                                                                                                ; sdram_statemachine:sdram_adaptor|data_out_reg[0]                       ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 42 ;                                                                        ;
;  Structure 42                                                                                                ; sdram_statemachine:sdram_adaptor|DATA_IN_sreg[16]                      ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 43 ;                                                                        ;
;  Structure 43                                                                                                ; sdram_statemachine:sdram_adaptor|DATA_IN_sreg[12]                      ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 44 ;                                                                        ;
;  Structure 44                                                                                                ; sdram_statemachine:sdram_adaptor|DATA_IN_sreg[20]                      ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 45 ;                                                                        ;
;  Structure 45                                                                                                ; sdram_statemachine:sdram_adaptor|data_out_reg[2]                       ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 46 ;                                                                        ;
;  Structure 46                                                                                                ; sdram_statemachine:sdram_adaptor|DATA_IN_sreg[26]                      ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 47 ;                                                                        ;
;  Structure 47                                                                                                ; sdram_statemachine:sdram_adaptor|DATA_IN_sreg[10]                      ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 48 ;                                                                        ;
;  Structure 48                                                                                                ; sdram_statemachine:sdram_adaptor|DATA_IN_sreg[2]                       ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 49 ;                                                                        ;
;  Structure 49                                                                                                ; sdram_statemachine:sdram_adaptor|DATA_IN_sreg[18]                      ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 50 ;                                                                        ;
;  Structure 50                                                                                                ; sdram_statemachine:sdram_adaptor|data_out_reg[15]                      ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 51 ;                                                                        ;
;  Structure 51                                                                                                ; sdram_statemachine:sdram_adaptor|data_out_reg[29]                      ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 52 ;                                                                        ;
;  Structure 52                                                                                                ; sdram_statemachine:sdram_adaptor|data_out_reg[28]                      ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 53 ;                                                                        ;
;  Structure 53                                                                                                ; sdram_statemachine:sdram_adaptor|DATA_IN_sreg[28]                      ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 54 ;                                                                        ;
;  Structure 54                                                                                                ; sdram_statemachine:sdram_adaptor|data_out_reg[27]                      ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 55 ;                                                                        ;
;  Structure 55                                                                                                ; sdram_statemachine:sdram_adaptor|DATA_IN_sreg[27]                      ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 56 ;                                                                        ;
;  Structure 56                                                                                                ; sdram_statemachine:sdram_adaptor|data_out_reg[12]                      ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 57 ;                                                                        ;
;  Structure 57                                                                                                ; sdram_statemachine:sdram_adaptor|data_out_reg[9]                       ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 58 ;                                                                        ;
;  Structure 58                                                                                                ; sdram_statemachine:sdram_adaptor|data_out_reg[11]                      ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 59 ;                                                                        ;
;  Structure 59                                                                                                ; sdram_statemachine:sdram_adaptor|data_out_reg[13]                      ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 60 ;                                                                        ;
;  Structure 60                                                                                                ; sdram_statemachine:sdram_adaptor|data_out_reg[22]                      ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 61 ;                                                                        ;
;  Structure 61                                                                                                ; sdram_statemachine:sdram_adaptor|data_out_reg[3]                       ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 62 ;                                                                        ;
;  Structure 62                                                                                                ; sdram_statemachine:sdram_adaptor|data_out_reg[4]                       ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 63 ;                                                                        ;
;  Structure 63                                                                                                ; sdram_statemachine:sdram_adaptor|data_out_reg[14]                      ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 64 ;                                                                        ;
;  Structure 64                                                                                                ; sdram_statemachine:sdram_adaptor|data_out_reg[8]                       ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 65 ;                                                                        ;
;  Structure 65                                                                                                ; sdram_statemachine:sdram_adaptor|data_out_reg[10]                      ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 66 ;                                                                        ;
;  Structure 66                                                                                                ; sdram_statemachine:sdram_adaptor|data_out_reg[18]                      ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 67 ;                                                                        ;
;  Structure 67                                                                                                ; sdram_statemachine:sdram_adaptor|data_out_reg[16]                      ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 68 ;                                                                        ;
;  Structure 68                                                                                                ; sdram_statemachine:sdram_adaptor|data_out_reg[25]                      ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 69 ;                                                                        ;
;  Structure 69                                                                                                ; sdram_statemachine:sdram_adaptor|data_out_reg[26]                      ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 70 ;                                                                        ;
;  Structure 70                                                                                                ; sdram_statemachine:sdram_adaptor|data_out_reg[17]                      ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 71 ;                                                                        ;
;  Structure 71                                                                                                ; sdram_statemachine:sdram_adaptor|READ_EN_sreg                          ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 72 ;                                                                        ;
;  Structure 72                                                                                                ; sdram_statemachine:sdram_adaptor|WRITE_EN_sreg                         ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 73 ;                                                                        ;
;  Structure 73                                                                                                ; sdram_statemachine:sdram_adaptor|refresh_sreg                          ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 74 ;                                                                        ;
;  Structure 74                                                                                                ; sdram_statemachine:sdram_adaptor|ADDRESS_IN_sreg[11]                   ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 75 ;                                                                        ;
;  Structure 75                                                                                                ; sdram_statemachine:sdram_adaptor|ADDRESS_IN_sreg[12]                   ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 76 ;                                                                        ;
;  Structure 76                                                                                                ; sdram_statemachine:sdram_adaptor|ADDRESS_IN_sreg[14]                   ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 77 ;                                                                        ;
;  Structure 77                                                                                                ; sdram_statemachine:sdram_adaptor|ADDRESS_IN_sreg[20]                   ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 78 ;                                                                        ;
;  Structure 78                                                                                                ; sdram_statemachine:sdram_adaptor|ADDRESS_IN_sreg[21]                   ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 79 ;                                                                        ;
;  Structure 79                                                                                                ; sdram_statemachine:sdram_adaptor|dqm_mask_sreg[2]                      ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 80 ;                                                                        ;
;  Structure 80                                                                                                ; sdram_statemachine:sdram_adaptor|dqm_mask_sreg[3]                      ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 81 ;                                                                        ;
;  Structure 81                                                                                                ; sdram_statemachine:sdram_adaptor|dqm_mask_sreg[1]                      ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 82 ;                                                                        ;
;  Structure 82                                                                                                ; sdram_statemachine:sdram_adaptor|ADDRESS_IN_sreg[0]                    ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 83 ;                                                                        ;
;  Structure 83                                                                                                ; sdram_statemachine:sdram_adaptor|ADDRESS_IN_sreg[8]                    ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 84 ;                                                                        ;
;  Structure 84                                                                                                ; sdram_statemachine:sdram_adaptor|ADDRESS_IN_sreg[1]                    ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 85 ;                                                                        ;
;  Structure 85                                                                                                ; sdram_statemachine:sdram_adaptor|ADDRESS_IN_sreg[9]                    ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 86 ;                                                                        ;
;  Structure 86                                                                                                ; sdram_statemachine:sdram_adaptor|ADDRESS_IN_sreg[2]                    ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 87 ;                                                                        ;
;  Structure 87                                                                                                ; sdram_statemachine:sdram_adaptor|ADDRESS_IN_sreg[10]                   ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 88 ;                                                                        ;
;  Structure 88                                                                                                ; sdram_statemachine:sdram_adaptor|ADDRESS_IN_sreg[3]                    ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 89 ;                                                                        ;
;  Structure 89                                                                                                ; sdram_statemachine:sdram_adaptor|ADDRESS_IN_sreg[4]                    ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 90 ;                                                                        ;
;  Structure 90                                                                                                ; sdram_statemachine:sdram_adaptor|ADDRESS_IN_sreg[5]                    ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 91 ;                                                                        ;
;  Structure 91                                                                                                ; sdram_statemachine:sdram_adaptor|ADDRESS_IN_sreg[13]                   ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 92 ;                                                                        ;
;  Structure 92                                                                                                ; sdram_statemachine:sdram_adaptor|ADDRESS_IN_sreg[6]                    ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 93 ;                                                                        ;
;  Structure 93                                                                                                ; sdram_statemachine:sdram_adaptor|ADDRESS_IN_sreg[7]                    ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 94 ;                                                                        ;
;  Structure 94                                                                                                ; sdram_statemachine:sdram_adaptor|ADDRESS_IN_sreg[15]                   ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 95 ;                                                                        ;
;  Structure 95                                                                                                ; sdram_statemachine:sdram_adaptor|ADDRESS_IN_sreg[16]                   ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 96 ;                                                                        ;
;  Structure 96                                                                                                ; sdram_statemachine:sdram_adaptor|ADDRESS_IN_sreg[17]                   ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 97 ;                                                                        ;
;  Structure 97                                                                                                ; sdram_statemachine:sdram_adaptor|ADDRESS_IN_sreg[18]                   ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 98 ;                                                                        ;
;  Structure 98                                                                                                ; sdram_statemachine:sdram_adaptor|ADDRESS_IN_sreg[19]                   ;
+--------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Medium Violations                                                                                                                                 ;
+----------------------------------------------------------------------------------------------+----------------------------------------------------+
; Rule name                                                                                    ; Name                                               ;
+----------------------------------------------------------------------------------------------+----------------------------------------------------+
; Rule C104: Clock signal source should drive only clock input ports                           ; i2sslave:audio_codec_data|CLK_FAKE                 ;
;  Clock ports destination node(s) list                                                        ; i2sslave:audio_codec_data|shiftreg_reg[15]         ;
;  Clock ports destination node(s) list                                                        ; i2sslave:audio_codec_data|daclrc_reg               ;
;  Clock ports destination node(s) list                                                        ; i2sslave:audio_codec_data|bclk_last_reg            ;
;  Clock ports destination node(s) list                                                        ; i2sslave:audio_codec_data|bclk_reg                 ;
;  Clock ports destination node(s) list                                                        ; i2sslave:audio_codec_data|daclrc_last_reg          ;
;  Clock ports destination node(s) list                                                        ; i2sslave:audio_codec_data|shiftreg_reg[14]         ;
;  Clock ports destination node(s) list                                                        ; i2sslave:audio_codec_data|shiftreg_reg[13]         ;
;  Clock ports destination node(s) list                                                        ; i2sslave:audio_codec_data|shiftreg_reg[12]         ;
;  Clock ports destination node(s) list                                                        ; i2sslave:audio_codec_data|shiftreg_reg[11]         ;
;  Clock ports destination node(s) list                                                        ; i2sslave:audio_codec_data|shiftreg_reg[10]         ;
; Rule C106: Clock signal source should not drive registers triggered by different clock edges ; pll:pll|altpll:altpll_component|_clk1              ;
;  Positive edge destination node(s) list                                                      ; i2c_loader:audio_codec_config_over_i2c|shiftreg[5] ;
;  Positive edge destination node(s) list                                                      ; i2c_loader:audio_codec_config_over_i2c|nbyte[0]    ;
;  Positive edge destination node(s) list                                                      ; i2c_loader:audio_codec_config_over_i2c|nbit[0]     ;
;  Positive edge destination node(s) list                                                      ; i2c_loader:audio_codec_config_over_i2c|nbyte[1]    ;
;  Positive edge destination node(s) list                                                      ; i2c_loader:audio_codec_config_over_i2c|state.Stop  ;
;  Positive edge destination node(s) list                                                      ; i2c_loader:audio_codec_config_over_i2c|state.Pause ;
;  Negative edge destination node(s) list                                                      ; i2c_loader:audio_codec_config_over_i2c|divider[1]  ;
;  Negative edge destination node(s) list                                                      ; i2c_loader:audio_codec_config_over_i2c|divider[0]  ;
;  Negative edge destination node(s) list                                                      ; i2c_loader:audio_codec_config_over_i2c|divider[3]  ;
;  Negative edge destination node(s) list                                                      ; i2c_loader:audio_codec_config_over_i2c|divider[2]  ;
;  Negative edge destination node(s) list                                                      ; i2c_loader:audio_codec_config_over_i2c|divider[4]  ;
;  Negative edge destination node(s) list                                                      ; i2c_loader:audio_codec_config_over_i2c|divider[5]  ;
+----------------------------------------------------------------------------------------------+----------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Information only Violations                                                                                                                                                    ;
+------------------------------------------------------------------+---------------------------------------------------------------------------------------------------+---------+
; Rule name                                                        ; Name                                                                                              ; Fan-Out ;
+------------------------------------------------------------------+---------------------------------------------------------------------------------------------------+---------+
; Rule T101: Nodes with more than the specified number of fan-outs ; pll:pll|altpll:altpll_component|_clk1~clkctrl                                                     ; 4688    ;
; Rule T101: Nodes with more than the specified number of fan-outs ; pll:pll|altpll:altpll_component|_locked                                                           ; 359     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|pokey_mixer_mux:pokey_mixer|LEFT_CHANNEL_REG                              ; 33      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|Add2~6         ; 43      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|address_decoder:mmu1|POKEY_WR_ENABLE~1                                    ; 50      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|memORY_ACCESS                                                   ; 56      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; comb~1                                                                                            ; 146     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; sdram_statemachine:sdram_adaptor|sdram_state_reg[2]                                               ; 49      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; sdram_statemachine:sdram_adaptor|delay_reg[2]                                                     ; 34      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; pll:pll|altpll:altpll_component|_clk0~clkctrl                                                     ; 110     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; sdram_statemachine:sdram_adaptor|process_2~0                                                      ; 61      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_execute                            ; 126     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insn~47                                     ; 38      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|fetched_w_r[0]~1                            ; 33      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|Mux13~0                                                         ; 113     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                    ; 56      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|antic:antic1|vcount_reg[0]~9                                              ; 573     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; 38      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; comb~0clkctrl                                                                                     ; 2269    ;
; Rule T101: Nodes with more than the specified number of fan-outs ; comb~0                                                                                            ; 75      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]~0                                             ; 32      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|address_decoder:mmu1|Mux22~2                                              ; 98      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; comb~1clkctrl                                                                                     ; 509     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|Add2~2                                      ; 44      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|pc_r[0]                                     ; 72      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[0]~14                           ; 50      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|address_decoder:mmu1|Mux11~2                                              ; 33      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insns~164                                   ; 143     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[0]                                                   ; 70      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_mult5                              ; 62      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[2]                                                   ; 60      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|pc_r[1]                                     ; 72      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insn.dec_or                                 ; 37      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|Equal1~10                          ; 41      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|count[30]~2                        ; 32      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|address_decoder:mmu1|Mux20~0                                              ; 72      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|address_decoder:mmu1|Mux12~2                                              ; 33      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|address_decoder:mmu1|Mux21~2                                              ; 105     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[0]~0                                             ; 32      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|address_decoder:mmu1|Mux13~0                                              ; 34      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|address_decoder:mmu1|Mux14~0                                              ; 34      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|b_r[16]~31                                  ; 31      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insn.dec_im                                 ; 40      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|Selector100~0                               ; 47      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|fetched_w_r[4]                              ; 33      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|address_decoder:mmu1|Mux19~0                                              ; 66      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_reg                                               ; 66      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|busy                               ; 51      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|state                              ; 53      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insn.dec_store_sp                           ; 38      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|address_decoder:mmu1|Mux102~0                                             ; 41      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|antic:antic1|refresh_fetch_reg                                            ; 37      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|antic:antic1|hcount_reg[1]                                                ; 34      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|antic:antic1|hcount_reg[2]                                                ; 38      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|antic:antic1|hcount_reg[3]                                                ; 35      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|address_decoder:mmu1|Mux125~0                                             ; 76      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|address_decoder:mmu1|ADDR_reg[0]                                          ; 48      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|address_decoder:mmu1|Mux24~1                                              ; 49      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|cpu:cpu6502|CPU_ENABLE_RDY                                                ; 73      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[26]~0                         ; 44      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|address_decoder:mmu1|MEMORY_DATA[5]~2                                     ; 105     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|address_decoder:mmu1|state_reg[0]                                         ; 55      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; sdram_statemachine:sdram_adaptor|ADDRESS_IN_sreg[11]~0                                            ; 39      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|address_decoder:mmu1|MEMORY_DATA[4]~63                                    ; 32      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|address_decoder:mmu1|Mux122~0                                             ; 73      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|address_decoder:mmu1|state_reg[1]                                         ; 56      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|gtia:gtia1|grafm_reg[3]~0                                                 ; 103     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[0]~15                           ; 32      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insn.dec_lshr                               ; 45      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|address_decoder:mmu1|Mux15~0                                              ; 34      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[0]~0                                             ; 32      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|address_decoder:mmu1|Mux18~0                                              ; 51      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|address_decoder:mmu1|Mux16~0                                              ; 34      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[0]~1                                             ; 32      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|address_decoder:mmu1|Mux17~0                                              ; 34      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|fetched_w_r[12]                             ; 33      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|fetched_w_r[28]                             ; 33      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; sdram_statemachine:sdram_adaptor|ADDRESS_IN_sreg[12]~1                                            ; 45      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|address_decoder:mmu1|Mux124~0                                             ; 60      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|address_decoder:mmu1|Mux23~1                                              ; 50      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|fetched_w_r[20]                             ; 33      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|gtia:gtia1|grafm_reg[4]~5                                                 ; 112     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|cpu:cpu6502|cpu_65xx:cpu_6502_peter|nextOpcInfo[42]~1                     ; 33      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|gtia:gtia1|grafm_reg[0]~6                                                 ; 108     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|address_decoder:mmu1|MEMORY_DATA[5]~80                                    ; 32      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|gtia:gtia1|grafm_reg[5]~1                                                 ; 111     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|cpu:cpu6502|cpu_65xx:cpu_6502_peter|\calcNextOpcode:myNextOpcode[4]~0     ; 35      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|cpu:cpu6502|cpu_65xx:cpu_6502_peter|\calcNextOpcode:myNextOpcode[6]~0     ; 43      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|cpu:cpu6502|cpu_65xx:cpu_6502_peter|\calcNextOpcode:myNextOpcode[3]~0     ; 44      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|cpu:cpu6502|cpu_65xx:cpu_6502_peter|\calcNextOpcode:myNextOpcode[2]~0     ; 56      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|gtia:gtia1|grafp1_reg[6]~1                                                ; 114     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|cpu:cpu6502|cpu_65xx:cpu_6502_peter|\calcNextOpcode:myNextOpcode[1]~1     ; 39      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|address_decoder:mmu1|Mux123~0                                             ; 82      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|gtia:gtia1|grafm_reg[1]~2                                                 ; 111     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|gtia:gtia1|grafp1_reg[7]~0                                                ; 110     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|cpu:cpu6502|cpu_65xx:cpu_6502_peter|\calcNextOpcode:myNextOpcode[7]~0     ; 38      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|cpu:cpu6502|cpu_65xx:cpu_6502_peter|\calcNextOpcode:myNextOpcode[6]~1     ; 37      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[41]                           ; 37      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[40]                           ; 40      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[39]                           ; 35      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[1]                                                   ; 31      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insn.dec_and                                ; 33      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|Add2~0                                      ; 79      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insn.dec_sub                                ; 33      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insn.dec_shift                              ; 32      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insn.dec_not                                ; 33      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insn.dec_flip                               ; 33      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|address_decoder:mmu1|ADDR_reg[1]                                          ; 64      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|gtia:gtia1|grafm_reg[2]~4                                                 ; 106     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|shared_enable:enables|oldcpu_enable~1                                     ; 80      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|address_decoder:mmu1|Mux121~2                                             ; 82      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|antic:antic1|simple_counter:antic_counter_line_buffer|value_reg[2]        ; 105     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|antic:antic1|simple_counter:antic_counter_line_buffer|value_reg[0]        ; 96      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|antic:antic1|simple_counter:antic_counter_line_buffer|value_reg[1]        ; 139     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|antic:antic1|simple_counter:antic_counter_line_buffer|value_reg[3]        ; 132     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|antic:antic1|simple_counter:antic_counter_line_buffer|value_reg[5]        ; 48      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|antic:antic1|line_buffer_data_in[1]~2                                     ; 48      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serial_reset~1                               ; 36      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; enable_divider:enable_179_clock_div_zpu_pokey|enabled_out_reg                                     ; 68      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|antic:antic1|Mux5~1                                                       ; 33      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|antic:antic1|Mux5~2                                                       ; 81      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|antic:antic1|line_buffer_data_in[7]~8                                     ; 48      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|antic:antic1|line_buffer_data_in[5]~6                                     ; 48      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|antic:antic1|line_buffer_data_in[3]~4                                     ; 48      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|antic:antic1|line_buffer_data_in[0]~1                                     ; 48      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|antic:antic1|line_buffer_data_in[2]~3                                     ; 48      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|antic:antic1|line_buffer_data_in[4]~5                                     ; 48      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|antic:antic1|line_buffer_data_in[6]~7                                     ; 48      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|gtia:gtia1|hitclr_write~1                                                 ; 62      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[11]~46                                               ; 48      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[11]~44                                               ; 48      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[11]~47                                               ; 48      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[11]~39                                               ; 48      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[11]~49                                               ; 32      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[11]~22                                               ; 48      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[11]~29                                               ; 48      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[11]~27                                               ; 48      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[11]~30                                               ; 48      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[11]~32                                               ; 32      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[7]~35                                           ; 32      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[7]~34                                           ; 33      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|Add2~10        ; 39      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|Add2~0         ; 52      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|Add2~4         ; 50      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|Add2~2         ; 42      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari5200core:atari5200|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|Add2~8         ; 37      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; pll:pll|altpll:altpll_component|_clk1~clkctrl                                                     ; 4688    ;
; Rule T102: Top nodes with the highest number of fan-outs         ; comb~0clkctrl                                                                                     ; 2269    ;
; Rule T102: Top nodes with the highest number of fan-outs         ; atari5200core:atari5200|antic:antic1|vcount_reg[0]~9                                              ; 573     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; comb~1clkctrl                                                                                     ; 509     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; pll:pll|altpll:altpll_component|_locked                                                           ; 359     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; comb~1                                                                                            ; 146     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insns~164                                   ; 143     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; atari5200core:atari5200|antic:antic1|simple_counter:antic_counter_line_buffer|value_reg[1]        ; 139     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; atari5200core:atari5200|antic:antic1|simple_counter:antic_counter_line_buffer|value_reg[3]        ; 132     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_execute                            ; 126     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; atari5200core:atari5200|gtia:gtia1|grafp1_reg[6]~1                                                ; 114     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; zpucore:zpu|zpu_glue:zpu_and_glue|Mux13~0                                                         ; 113     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; atari5200core:atari5200|gtia:gtia1|grafm_reg[4]~5                                                 ; 112     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; atari5200core:atari5200|gtia:gtia1|grafm_reg[1]~2                                                 ; 111     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; atari5200core:atari5200|gtia:gtia1|grafm_reg[5]~1                                                 ; 111     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; atari5200core:atari5200|gtia:gtia1|grafp1_reg[7]~0                                                ; 110     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; pll:pll|altpll:altpll_component|_clk0~clkctrl                                                     ; 110     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; atari5200core:atari5200|gtia:gtia1|grafm_reg[0]~6                                                 ; 108     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; atari5200core:atari5200|gtia:gtia1|grafm_reg[2]~4                                                 ; 106     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; atari5200core:atari5200|address_decoder:mmu1|Mux21~2                                              ; 105     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; atari5200core:atari5200|antic:antic1|simple_counter:antic_counter_line_buffer|value_reg[2]        ; 105     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; atari5200core:atari5200|address_decoder:mmu1|MEMORY_DATA[5]~2                                     ; 105     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; atari5200core:atari5200|gtia:gtia1|grafm_reg[3]~0                                                 ; 103     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; atari5200core:atari5200|address_decoder:mmu1|Mux22~2                                              ; 98      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; atari5200core:atari5200|antic:antic1|simple_counter:antic_counter_line_buffer|value_reg[0]        ; 96      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; atari5200core:atari5200|address_decoder:mmu1|Mux121~2                                             ; 82      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; atari5200core:atari5200|address_decoder:mmu1|Mux123~0                                             ; 82      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; atari5200core:atari5200|antic:antic1|Mux5~2                                                       ; 81      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; atari5200core:atari5200|shared_enable:enables|oldcpu_enable~1                                     ; 80      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|Add2~0                                      ; 79      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; atari5200core:atari5200|address_decoder:mmu1|Mux125~0                                             ; 76      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; comb~0                                                                                            ; 75      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; atari5200core:atari5200|cpu:cpu6502|CPU_ENABLE_RDY                                                ; 73      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; atari5200core:atari5200|address_decoder:mmu1|Mux122~0                                             ; 73      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; atari5200core:atari5200|address_decoder:mmu1|Mux20~0                                              ; 72      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|pc_r[0]                                     ; 72      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|pc_r[1]                                     ; 72      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[0]                                                   ; 70      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; enable_divider:enable_179_clock_div_zpu_pokey|enabled_out_reg                                     ; 68      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_reg                                               ; 66      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; atari5200core:atari5200|address_decoder:mmu1|Mux19~0                                              ; 66      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; atari5200core:atari5200|address_decoder:mmu1|ADDR_reg[1]                                          ; 64      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; atari5200core:atari5200|gtia:gtia1|hitclr_write~1                                                 ; 62      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_mult5                              ; 62      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; sdram_statemachine:sdram_adaptor|process_2~0                                                      ; 61      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[2]                                                   ; 60      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; atari5200core:atari5200|address_decoder:mmu1|Mux124~0                                             ; 60      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; atari5200core:atari5200|cpu:cpu6502|cpu_65xx:cpu_6502_peter|\calcNextOpcode:myNextOpcode[2]~0     ; 56      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                    ; 56      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; atari5200core:atari5200|address_decoder:mmu1|state_reg[1]                                         ; 56      ;
+------------------------------------------------------------------+---------------------------------------------------------------------------------------------------+---------+


+---------------------------+
; Design Assistant Messages ;
+---------------------------+
Info: *******************************************************************
Info: Running Quartus II 32-bit Design Assistant
    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
    Info: Processing started: Sat Nov  8 23:23:31 2014
Info: Command: quartus_drc --read_settings_files=off --write_settings_files=off atari5200core -c atari5200core
Info (332104): Reading SDC File: 'atari5200core.sdc'
Info (332110): Deriving PLL clocks
    Info (332110): create_generated_clock -source {pll|altpll_component|pll|inclk[0]} -divide_by 10 -multiply_by 23 -duty_cycle 50.00 -name {pll|altpll_component|pll|clk[0]} {pll|altpll_component|pll|clk[0]}
    Info (332110): create_generated_clock -source {pll|altpll_component|pll|inclk[0]} -divide_by 20 -multiply_by 23 -duty_cycle 50.00 -name {pll|altpll_component|pll|clk[1]} {pll|altpll_component|pll|clk[1]}
    Info (332110): create_generated_clock -source {pll|altpll_component|pll|inclk[0]} -divide_by 10 -multiply_by 23 -phase -54.00 -duty_cycle 50.00 -name {pll|altpll_component|pll|clk[2]} {pll|altpll_component|pll|clk[2]}
Warning (332060): Node: i2sslave:audio_codec_data|CLK_FAKE was determined to be a clock but was found without an associated clock assignment.
Critical Warning (308024): (High) Rule R101: Combinational logic used as a reset signal should be synchronized. Found 2 node(s) related to this rule.
    Critical Warning (308012): Node  "comb~1"
    Critical Warning (308012): Node  "comb~0"
Critical Warning (308060): (High) Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains. (Value defined:2). Found 98 asynchronous clock domain interface structure(s) related to this rule.
    Critical Warning (308012): Node  "sdram_statemachine:sdram_adaptor|sdram_state_reg[0]"
    Critical Warning (308012): Node  "sdram_statemachine:sdram_adaptor|sdram_state_reg[2]"
    Critical Warning (308012): Node  "sdram_statemachine:sdram_adaptor|sdram_state_reg[1]"
    Critical Warning (308012): Node  "sdram_statemachine:sdram_adaptor|request_sreg"
    Critical Warning (308012): Node  "sdram_statemachine:sdram_adaptor|reply_reg"
    Critical Warning (308012): Node  "sdram_statemachine:sdram_adaptor|data_out_reg[20]"
    Critical Warning (308012): Node  "sdram_statemachine:sdram_adaptor|DATA_IN_sreg[4]"
    Critical Warning (308012): Node  "sdram_statemachine:sdram_adaptor|data_out_reg[24]"
    Critical Warning (308012): Node  "sdram_statemachine:sdram_adaptor|DATA_IN_sreg[24]"
    Critical Warning (308012): Node  "sdram_statemachine:sdram_adaptor|data_out_reg[23]"
    Critical Warning (308012): Node  "sdram_statemachine:sdram_adaptor|DATA_IN_sreg[7]"
    Critical Warning (308012): Node  "sdram_statemachine:sdram_adaptor|DATA_IN_sreg[23]"
    Critical Warning (308012): Node  "sdram_statemachine:sdram_adaptor|DATA_IN_sreg[15]"
    Critical Warning (308012): Node  "sdram_statemachine:sdram_adaptor|dqm_mask_sreg[0]"
    Critical Warning (308012): Node  "sdram_statemachine:sdram_adaptor|data_out_reg[19]"
    Critical Warning (308012): Node  "sdram_statemachine:sdram_adaptor|DATA_IN_sreg[3]"
    Critical Warning (308012): Node  "sdram_statemachine:sdram_adaptor|DATA_IN_sreg[19]"
    Critical Warning (308012): Node  "sdram_statemachine:sdram_adaptor|DATA_IN_sreg[11]"
    Critical Warning (308012): Node  "sdram_statemachine:sdram_adaptor|data_out_reg[30]"
    Critical Warning (308012): Node  "sdram_statemachine:sdram_adaptor|DATA_IN_sreg[30]"
    Critical Warning (308012): Node  "sdram_statemachine:sdram_adaptor|DATA_IN_sreg[14]"
    Critical Warning (308012): Node  "sdram_statemachine:sdram_adaptor|DATA_IN_sreg[6]"
    Critical Warning (308012): Node  "sdram_statemachine:sdram_adaptor|data_out_reg[21]"
    Critical Warning (308012): Node  "sdram_statemachine:sdram_adaptor|DATA_IN_sreg[5]"
    Critical Warning (308012): Node  "sdram_statemachine:sdram_adaptor|DATA_IN_sreg[13]"
    Critical Warning (308012): Node  "sdram_statemachine:sdram_adaptor|DATA_IN_sreg[21]"
    Critical Warning (308012): Node  "sdram_statemachine:sdram_adaptor|data_out_reg[31]"
    Critical Warning (308012): Node  "sdram_statemachine:sdram_adaptor|DATA_IN_sreg[31]"
    Critical Warning (308012): Node  "sdram_statemachine:sdram_adaptor|DATA_IN_sreg[8]"
    Critical Warning (308012): Node  "sdram_statemachine:sdram_adaptor|DATA_IN_sreg[0]"
    Info (308002): Truncated list of Design Assistant messages to 30 messages. Go to sections under Design Assistant section of Compilation Report for complete lists of Design Assistant messages generated.
Warning (308040): (Medium) Rule C104: Clock signal source should drive only clock input ports. Found 1 nodes related to this rule.
    Warning (308010): Node  "i2sslave:audio_codec_data|CLK_FAKE"
Warning (308022): (Medium) Rule C106: Clock signal source should not drive registers triggered by different clock edges. Found 1 node(s) related to this rule.
    Warning (308010): Node  "pll:pll|altpll:altpll_component|_clk1"
Info (308046): (Information) Rule T101: Nodes with more than the specified number of fan-outs. (Value defined:30). Found 146 node(s) with highest fan-out.
    Info (308011): Node  "pll:pll|altpll:altpll_component|_clk1~clkctrl"
    Info (308011): Node  "pll:pll|altpll:altpll_component|_locked"
    Info (308011): Node  "atari5200core:atari5200|pokey_mixer_mux:pokey_mixer|LEFT_CHANNEL_REG"
    Info (308011): Node  "atari5200core:atari5200|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|Add2~6"
    Info (308011): Node  "atari5200core:atari5200|address_decoder:mmu1|POKEY_WR_ENABLE~1"
    Info (308011): Node  "zpucore:zpu|zpu_glue:zpu_and_glue|memORY_ACCESS"
    Info (308011): Node  "comb~1"
    Info (308011): Node  "sdram_statemachine:sdram_adaptor|sdram_state_reg[2]"
    Info (308011): Node  "sdram_statemachine:sdram_adaptor|delay_reg[2]"
    Info (308011): Node  "pll:pll|altpll:altpll_component|_clk0~clkctrl"
    Info (308011): Node  "sdram_statemachine:sdram_adaptor|process_2~0"
    Info (308011): Node  "zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_execute"
    Info (308011): Node  "zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insn~47"
    Info (308011): Node  "zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|fetched_w_r[0]~1"
    Info (308011): Node  "zpucore:zpu|zpu_glue:zpu_and_glue|Mux13~0"
    Info (308011): Node  "zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg"
    Info (308011): Node  "atari5200core:atari5200|antic:antic1|vcount_reg[0]~9"
    Info (308011): Node  "atari5200core:atari5200|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg"
    Info (308011): Node  "comb~0clkctrl"
    Info (308011): Node  "comb~0"
    Info (308011): Node  "zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]~0"
    Info (308011): Node  "atari5200core:atari5200|address_decoder:mmu1|Mux22~2"
    Info (308011): Node  "comb~1clkctrl"
    Info (308011): Node  "zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|Add2~2"
    Info (308011): Node  "zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|pc_r[0]"
    Info (308011): Node  "zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[0]~14"
    Info (308011): Node  "atari5200core:atari5200|address_decoder:mmu1|Mux11~2"
    Info (308011): Node  "zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insns~164"
    Info (308011): Node  "zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[0]"
    Info (308011): Node  "zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_mult5"
    Info (308002): Truncated list of Design Assistant messages to 30 messages. Go to sections under Design Assistant section of Compilation Report for complete lists of Design Assistant messages generated.
Info (308044): (Information) Rule T102: Top nodes with the highest number of fan-outs. (Value defined:50). Found 50 node(s) with highest fan-out.
    Info (308011): Node  "pll:pll|altpll:altpll_component|_clk1~clkctrl"
    Info (308011): Node  "comb~0clkctrl"
    Info (308011): Node  "atari5200core:atari5200|antic:antic1|vcount_reg[0]~9"
    Info (308011): Node  "comb~1clkctrl"
    Info (308011): Node  "pll:pll|altpll:altpll_component|_locked"
    Info (308011): Node  "comb~1"
    Info (308011): Node  "zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insns~164"
    Info (308011): Node  "atari5200core:atari5200|antic:antic1|simple_counter:antic_counter_line_buffer|value_reg[1]"
    Info (308011): Node  "atari5200core:atari5200|antic:antic1|simple_counter:antic_counter_line_buffer|value_reg[3]"
    Info (308011): Node  "zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_execute"
    Info (308011): Node  "atari5200core:atari5200|gtia:gtia1|grafp1_reg[6]~1"
    Info (308011): Node  "zpucore:zpu|zpu_glue:zpu_and_glue|Mux13~0"
    Info (308011): Node  "atari5200core:atari5200|gtia:gtia1|grafm_reg[4]~5"
    Info (308011): Node  "atari5200core:atari5200|gtia:gtia1|grafm_reg[1]~2"
    Info (308011): Node  "atari5200core:atari5200|gtia:gtia1|grafm_reg[5]~1"
    Info (308011): Node  "atari5200core:atari5200|gtia:gtia1|grafp1_reg[7]~0"
    Info (308011): Node  "pll:pll|altpll:altpll_component|_clk0~clkctrl"
    Info (308011): Node  "atari5200core:atari5200|gtia:gtia1|grafm_reg[0]~6"
    Info (308011): Node  "atari5200core:atari5200|gtia:gtia1|grafm_reg[2]~4"
    Info (308011): Node  "atari5200core:atari5200|address_decoder:mmu1|Mux21~2"
    Info (308011): Node  "atari5200core:atari5200|antic:antic1|simple_counter:antic_counter_line_buffer|value_reg[2]"
    Info (308011): Node  "atari5200core:atari5200|address_decoder:mmu1|MEMORY_DATA[5]~2"
    Info (308011): Node  "atari5200core:atari5200|gtia:gtia1|grafm_reg[3]~0"
    Info (308011): Node  "atari5200core:atari5200|address_decoder:mmu1|Mux22~2"
    Info (308011): Node  "atari5200core:atari5200|antic:antic1|simple_counter:antic_counter_line_buffer|value_reg[0]"
    Info (308011): Node  "atari5200core:atari5200|address_decoder:mmu1|Mux121~2"
    Info (308011): Node  "atari5200core:atari5200|address_decoder:mmu1|Mux123~0"
    Info (308011): Node  "atari5200core:atari5200|antic:antic1|Mux5~2"
    Info (308011): Node  "atari5200core:atari5200|shared_enable:enables|oldcpu_enable~1"
    Info (308011): Node  "zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|Add2~0"
    Info (308002): Truncated list of Design Assistant messages to 30 messages. Go to sections under Design Assistant section of Compilation Report for complete lists of Design Assistant messages generated.
Info (308007): Design Assistant information: finished post-fitting analysis of current design -- generated 196 information messages and 102 warning messages
Info: Quartus II 32-bit Design Assistant was successful. 0 errors, 39 warnings
    Info: Peak virtual memory: 364 megabytes
    Info: Processing ended: Sat Nov  8 23:23:46 2014
    Info: Elapsed time: 00:00:15
    Info: Total CPU time (on all processors): 00:00:07


