TimeQuest Timing Analyzer report for atari800core
Sat Nov  1 22:41:07 2014
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Parallel Compilation
  4. SDC File List
  5. Clocks
  6. Slow 1200mV 85C Model Fmax Summary
  7. Timing Closure Recommendations
  8. Slow 1200mV 85C Model Setup Summary
  9. Slow 1200mV 85C Model Hold Summary
 10. Slow 1200mV 85C Model Recovery Summary
 11. Slow 1200mV 85C Model Removal Summary
 12. Slow 1200mV 85C Model Minimum Pulse Width Summary
 13. Slow 1200mV 85C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 14. Slow 1200mV 85C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 15. Slow 1200mV 85C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 16. Slow 1200mV 85C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 17. Slow 1200mV 85C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 18. Slow 1200mV 85C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 19. Slow 1200mV 85C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 20. Slow 1200mV 85C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 21. Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 22. Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 23. Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]'
 24. Slow 1200mV 85C Model Minimum Pulse Width: 'FPGA_CLK'
 25. Setup Times
 26. Hold Times
 27. Clock to Output Times
 28. Minimum Clock to Output Times
 29. Output Enable Times
 30. Minimum Output Enable Times
 31. Output Disable Times
 32. Minimum Output Disable Times
 33. Slow 1200mV 85C Model Metastability Report
 34. Slow 1200mV 0C Model Fmax Summary
 35. Slow 1200mV 0C Model Setup Summary
 36. Slow 1200mV 0C Model Hold Summary
 37. Slow 1200mV 0C Model Recovery Summary
 38. Slow 1200mV 0C Model Removal Summary
 39. Slow 1200mV 0C Model Minimum Pulse Width Summary
 40. Slow 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 41. Slow 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 42. Slow 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 43. Slow 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 44. Slow 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 45. Slow 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 46. Slow 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 47. Slow 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 48. Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 49. Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 50. Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]'
 51. Slow 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'
 52. Setup Times
 53. Hold Times
 54. Clock to Output Times
 55. Minimum Clock to Output Times
 56. Output Enable Times
 57. Minimum Output Enable Times
 58. Output Disable Times
 59. Minimum Output Disable Times
 60. Slow 1200mV 0C Model Metastability Report
 61. Fast 1200mV 0C Model Setup Summary
 62. Fast 1200mV 0C Model Hold Summary
 63. Fast 1200mV 0C Model Recovery Summary
 64. Fast 1200mV 0C Model Removal Summary
 65. Fast 1200mV 0C Model Minimum Pulse Width Summary
 66. Fast 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 67. Fast 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 68. Fast 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 69. Fast 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 70. Fast 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 71. Fast 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 72. Fast 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 73. Fast 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 74. Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 75. Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 76. Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]'
 77. Fast 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'
 78. Setup Times
 79. Hold Times
 80. Clock to Output Times
 81. Minimum Clock to Output Times
 82. Output Enable Times
 83. Minimum Output Enable Times
 84. Output Disable Times
 85. Minimum Output Disable Times
 86. Fast 1200mV 0C Model Metastability Report
 87. Multicorner Timing Analysis Summary
 88. Setup Times
 89. Hold Times
 90. Clock to Output Times
 91. Minimum Clock to Output Times
 92. Board Trace Model Assignments
 93. Input Transition Times
 94. Slow Corner Signal Integrity Metrics
 95. Fast Corner Signal Integrity Metrics
 96. Setup Transfers
 97. Hold Transfers
 98. Recovery Transfers
 99. Removal Transfers
100. Report TCCS
101. Report RSKM
102. Unconstrained Paths
103. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                                      ;
+--------------------+-------------------------------------------------------------------+
; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ;
; Revision Name      ; atari800core                                                      ;
; Device Family      ; Cyclone III                                                       ;
; Device Name        ; EP3C16E144C8                                                      ;
; Timing Models      ; Final                                                             ;
; Delay Model        ; Combined                                                          ;
; Rise/Fall Delays   ; Enabled                                                           ;
+--------------------+-------------------------------------------------------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 4           ;
; Maximum allowed            ; 2           ;
;                            ;             ;
; Average used               ; 1.26        ;
; Maximum used               ; 2           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processor 2            ;  26.1%      ;
;     Processors 3-4         ;   0.0%      ;
+----------------------------+-------------+


+------------------------------------------------------+
; SDC File List                                        ;
+------------------+--------+--------------------------+
; SDC File Path    ; Status ; Read at                  ;
+------------------+--------+--------------------------+
; atari800core.sdc ; OK     ; Sat Nov  1 22:40:46 2014 ;
+------------------+--------+--------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                                                                                                                                                                                                                                                                                                                             ;
+-------------------------------------------------------------------------------+-----------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+------------------------------------------------------------------------------+---------------------------------------------------------------------------------+-----------------------------------------------------------------------------------+
; Clock Name                                                                    ; Type      ; Period  ; Frequency ; Rise  ; Fall    ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master                                                                       ; Source                                                                          ; Targets                                                                           ;
+-------------------------------------------------------------------------------+-----------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+------------------------------------------------------------------------------+---------------------------------------------------------------------------------+-----------------------------------------------------------------------------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Generated ; 11.747  ; 85.13 MHz ; 0.000 ; 5.873   ; 50.00      ; 1         ; 3           ;       ;        ;           ;            ; false    ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] } ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Generated ; 35.242  ; 28.38 MHz ; 0.000 ; 17.621  ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] } ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ; Generated ; 11.747  ; 85.13 MHz ; 7.635 ; 13.508  ; 50.00      ; 1         ; 3           ; 234.0 ;        ;           ;            ; false    ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] } ;
; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]  ; Generated ; 35.242  ; 28.38 MHz ; 0.000 ; 17.621  ; 50.00      ; 40        ; 227         ;       ;        ;           ;            ; false    ; FPGA_CLK                                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]  ; { \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] }  ;
; FPGA_CLK                                                                      ; Base      ; 200.000 ; 5.0 MHz   ; 0.000 ; 100.000 ;            ;           ;             ;       ;        ;           ;            ;          ;                                                                              ;                                                                                 ; { FPGA_CLK }                                                                      ;
+-------------------------------------------------------------------------------+-----------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+------------------------------------------------------------------------------+---------------------------------------------------------------------------------+-----------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Fmax Summary                                                                                  ;
+------------+-----------------+-------------------------------------------------------------------------------+------+
; Fmax       ; Restricted Fmax ; Clock Name                                                                    ; Note ;
+------------+-----------------+-------------------------------------------------------------------------------+------+
; 45.8 MHz   ; 45.8 MHz        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;      ;
; 118.78 MHz ; 118.78 MHz      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;      ;
+------------+-----------------+-------------------------------------------------------------------------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


----------------------------------
; Timing Closure Recommendations ;
----------------------------------
HTML report is unavailable in plain text report export.


+--------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup Summary                                                                    ;
+-------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                         ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -1.087 ; -6.454        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 2.861  ; 0.000         ;
+-------------------------------------------------------------------------------+--------+---------------+


+-------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold Summary                                                                    ;
+-------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                         ; Slack ; End Point TNS ;
+-------------------------------------------------------------------------------+-------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.437 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.453 ; 0.000         ;
+-------------------------------------------------------------------------------+-------+---------------+


+-------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery Summary                                                                ;
+-------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                         ; Slack ; End Point TNS ;
+-------------------------------------------------------------------------------+-------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 5.267 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 7.731 ; 0.000         ;
+-------------------------------------------------------------------------------+-------+---------------+


+-------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal Summary                                                                 ;
+-------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                         ; Slack ; End Point TNS ;
+-------------------------------------------------------------------------------+-------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 2.154 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 3.646 ; 0.000         ;
+-------------------------------------------------------------------------------+-------+---------------+


+--------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width Summary                                                      ;
+-------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                         ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.544  ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.297 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]  ; 17.584 ; 0.000         ;
; FPGA_CLK                                                                      ; 99.862 ; 0.000         ;
+-------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                       ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                         ; To Node                                      ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; -1.087 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.198     ; 12.507     ;
; -1.080 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 12.516     ;
; -1.074 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.224     ; 12.468     ;
; -1.012 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.224     ; 12.406     ;
; -0.963 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.198     ; 12.383     ;
; -0.937 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.196     ; 12.359     ;
; -0.891 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[17]                                                                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.191     ; 12.318     ;
; -0.865 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.225     ; 12.258     ;
; -0.838 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.239     ; 12.217     ;
; -0.821 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.227     ; 12.212     ;
; -0.802 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.198     ; 12.222     ;
; -0.800 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.227     ; 12.191     ;
; -0.795 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.212     ; 12.201     ;
; -0.788 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.196     ; 12.210     ;
; -0.782 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.238     ; 12.162     ;
; -0.767 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.225     ; 12.160     ;
; -0.760 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.197     ; 12.181     ;
; -0.753 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[22]                                                                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.191     ; 12.180     ;
; -0.753 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.181     ; 12.190     ;
; -0.747 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.223     ; 12.142     ;
; -0.721 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.196     ; 12.143     ;
; -0.720 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.238     ; 12.100     ;
; -0.713 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.198     ; 12.133     ;
; -0.706 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 12.142     ;
; -0.700 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.224     ; 12.094     ;
; -0.685 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.223     ; 12.080     ;
; -0.671 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.212     ; 12.077     ;
; -0.667 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.212     ; 12.073     ;
; -0.654 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.198     ; 12.074     ;
; -0.654 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.238     ; 12.034     ;
; -0.653 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.212     ; 12.059     ;
; -0.646 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.196     ; 12.068     ;
; -0.645 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.210     ; 12.053     ;
; -0.640 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.238     ; 12.020     ;
; -0.638 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.224     ; 12.032     ;
; -0.636 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.197     ; 12.057     ;
; -0.630 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[18]                                                                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.191     ; 12.057     ;
; -0.617 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.226     ; 12.009     ;
; -0.610 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.195     ; 12.033     ;
; -0.599 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[17]                                                                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.205     ; 12.012     ;
; -0.592 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.238     ; 11.972     ;
; -0.590 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[19]                                                                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.191     ; 12.017     ;
; -0.589 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.198     ; 12.009     ;
; -0.578 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.238     ; 11.958     ;
; -0.573 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.239     ; 11.952     ;
; -0.570 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.224     ; 11.964     ;
; -0.564 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[13]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.225     ; 11.957     ;
; -0.564 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[17]                                                                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.190     ; 11.992     ;
; -0.563 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.196     ; 11.985     ;
; -0.558 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[13]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.202     ; 11.974     ;
; -0.543 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.212     ; 11.949     ;
; -0.542 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.239     ; 11.921     ;
; -0.529 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.212     ; 11.935     ;
; -0.529 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.241     ; 11.906     ;
; -0.517 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[17]                                                                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.191     ; 11.944     ;
; -0.517 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.210     ; 11.925     ;
; -0.515 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.199     ; 11.934     ;
; -0.510 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.212     ; 11.916     ;
; -0.508 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.241     ; 11.885     ;
; -0.508 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.183     ; 11.943     ;
; -0.503 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.210     ; 11.911     ;
; -0.502 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.225     ; 11.895     ;
; -0.494 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.226     ; 11.886     ;
; -0.491 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.225     ; 11.884     ;
; -0.487 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[13]                                                                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.224     ; 11.881     ;
; -0.475 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.239     ; 11.854     ;
; -0.475 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.197     ; 11.896     ;
; -0.473 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.226     ; 11.865     ;
; -0.471 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[17]                                                                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.205     ; 11.884     ;
; -0.461 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[22]                                                                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.205     ; 11.874     ;
; -0.457 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[17]                                                                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.205     ; 11.870     ;
; -0.450 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.201     ; 11.867     ;
; -0.447 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.227     ; 11.838     ;
; -0.442 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.202     ; 11.858     ;
; -0.440 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.224     ; 11.834     ;
; -0.440 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.225     ; 11.833     ;
; -0.428 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.198     ; 11.848     ;
; -0.426 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[22]                                                                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.190     ; 11.854     ;
; -0.426 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.227     ; 11.817     ;
; -0.421 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.241     ; 11.798     ;
; -0.417 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.241     ; 11.794     ;
; -0.393 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.225     ; 11.786     ;
; -0.391 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.199     ; 11.810     ;
; -0.387 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.241     ; 11.764     ;
; -0.382 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.212     ; 11.788     ;
; -0.379 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|oss_bank[1]                       ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.184     ; 11.813     ;
; -0.379 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[22]                                                                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.191     ; 11.806     ;
; -0.368 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.212     ; 11.774     ;
; -0.366 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.241     ; 11.743     ;
; -0.365 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.197     ; 11.786     ;
; -0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.212     ; 11.768     ;
; -0.361 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.212     ; 11.767     ;
; -0.360 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[20]                                                                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.191     ; 11.787     ;
; -0.354 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.196     ; 11.776     ;
; -0.348 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.238     ; 11.728     ;
; -0.347 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.239     ; 11.726     ;
; -0.342 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|sic_axxx_enable                   ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.191     ; 11.769     ;
; -0.338 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[18]                                                                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.205     ; 11.751     ;
; -0.333 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.239     ; 11.712     ;
; -0.333 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[22]                                                                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.205     ; 11.746     ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                           ;
+-------+----------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                  ; To Node                                                                                                                                                  ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 2.861 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.200     ; 8.688      ;
; 2.961 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.200     ; 8.588      ;
; 3.095 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.187     ; 8.467      ;
; 3.153 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[29]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.200     ; 8.396      ;
; 3.168 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[0]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.200     ; 8.381      ;
; 3.186 ; ram_do_reg[1]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.201     ; 8.362      ;
; 3.285 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[2]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.184     ; 8.280      ;
; 3.285 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[3]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.184     ; 8.280      ;
; 3.340 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.200     ; 8.209      ;
; 3.372 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[4]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 8.203      ;
; 3.378 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[41]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.187     ; 8.184      ;
; 3.468 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.187     ; 8.094      ;
; 3.473 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[38]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.188     ; 8.088      ;
; 3.512 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_noise_filter:pokey_noise_filter0|out_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 8.059      ;
; 3.532 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.201     ; 8.016      ;
; 3.539 ; ram_do_reg[1]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[27]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.201     ; 8.009      ;
; 3.546 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.189     ; 8.014      ;
; 3.604 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[7]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.187     ; 7.958      ;
; 3.604 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[4]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.187     ; 7.958      ;
; 3.604 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[2]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.187     ; 7.958      ;
; 3.604 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[1]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.187     ; 7.958      ;
; 3.604 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[0]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.187     ; 7.958      ;
; 3.604 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[3]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.187     ; 7.958      ;
; 3.604 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[5]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.187     ; 7.958      ;
; 3.604 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[6]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.187     ; 7.958      ;
; 3.623 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.187     ; 7.939      ;
; 3.628 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.187     ; 7.934      ;
; 3.631 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[7]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.173     ; 7.945      ;
; 3.631 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[6]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.173     ; 7.945      ;
; 3.631 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[5]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.173     ; 7.945      ;
; 3.631 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[3]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.173     ; 7.945      ;
; 3.631 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[1]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.173     ; 7.945      ;
; 3.631 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[0]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.173     ; 7.945      ;
; 3.631 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[2]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.173     ; 7.945      ;
; 3.666 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_noise_filter:pokey_noise_filter1|out_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.200     ; 7.883      ;
; 3.699 ; ram_do_reg[1]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.188     ; 7.862      ;
; 3.730 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[2]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.173     ; 7.846      ;
; 3.744 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[0]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.200     ; 7.805      ;
; 3.774 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.190     ; 7.785      ;
; 3.801 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 7.773      ;
; 3.801 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 7.773      ;
; 3.801 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 7.773      ;
; 3.801 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 7.773      ;
; 3.801 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 7.773      ;
; 3.801 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[5] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 7.773      ;
; 3.826 ; ram_do_reg[1]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.190     ; 7.733      ;
; 3.827 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[39]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.200     ; 7.722      ;
; 3.846 ; ram_do_reg[0]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.189     ; 7.714      ;
; 3.876 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[19]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.187     ; 7.686      ;
; 3.906 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.189     ; 7.654      ;
; 3.922 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.187     ; 7.640      ;
; 3.932 ; ram_do_reg[1]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.188     ; 7.629      ;
; 3.935 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.188     ; 7.626      ;
; 3.941 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[0]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.201     ; 7.607      ;
; 3.946 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.202     ; 7.601      ;
; 3.946 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[1]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.202     ; 7.601      ;
; 3.946 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[2]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.202     ; 7.601      ;
; 3.946 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[3]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.202     ; 7.601      ;
; 3.946 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[4]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.202     ; 7.601      ;
; 3.946 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[5]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.202     ; 7.601      ;
; 3.946 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[6]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.202     ; 7.601      ;
; 3.946 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[7]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.202     ; 7.601      ;
; 3.948 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[38]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.189     ; 7.612      ;
; 3.972 ; ram_do_reg[0]              ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[0]                                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.168     ; 7.609      ;
; 3.973 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_noise_filter:pokey_noise_filter3|out_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.190     ; 7.586      ;
; 3.979 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[7]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.187     ; 7.583      ;
; 3.979 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[5]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.187     ; 7.583      ;
; 3.979 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[4]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.187     ; 7.583      ;
; 3.979 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[2]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.187     ; 7.583      ;
; 3.979 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[1]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.187     ; 7.583      ;
; 3.979 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[0]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.187     ; 7.583      ;
; 3.979 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[3]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.187     ; 7.583      ;
; 3.979 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[6]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.187     ; 7.583      ;
; 3.986 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[14]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.200     ; 7.563      ;
; 3.999 ; ram_do_reg[1]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[0]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.201     ; 7.549      ;
; 4.000 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[37]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.187     ; 7.562      ;
; 4.024 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[6]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 7.551      ;
; 4.024 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[5]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 7.551      ;
; 4.024 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[1]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 7.551      ;
; 4.024 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[0]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 7.551      ;
; 4.024 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[3]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 7.551      ;
; 4.024 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[4]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 7.551      ;
; 4.024 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[7]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 7.551      ;
; 4.057 ; ram_do_reg[0]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.200     ; 7.492      ;
; 4.072 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer1|count_reg[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.204     ; 7.473      ;
; 4.072 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer1|count_reg[1]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.204     ; 7.473      ;
; 4.072 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer1|count_reg[2]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.204     ; 7.473      ;
; 4.072 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer1|count_reg[3]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.204     ; 7.473      ;
; 4.072 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer1|count_reg[4]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.204     ; 7.473      ;
; 4.072 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer1|count_reg[5]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.204     ; 7.473      ;
; 4.072 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer1|count_reg[6]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.204     ; 7.473      ;
; 4.072 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer1|count_reg[7]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.204     ; 7.473      ;
; 4.073 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[27]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.201     ; 7.475      ;
; 4.076 ; ram_do_reg[1]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[5]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.190     ; 7.483      ;
; 4.085 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|highpass1_reg                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.201     ; 7.463      ;
; 4.087 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_noise_filter:pokey_noise_filter0|out_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.187     ; 7.475      ;
; 4.099 ; ram_do_reg[0]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[38]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.188     ; 7.462      ;
; 4.114 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[41]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.188     ; 7.447      ;
; 4.122 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.170     ; 7.457      ;
; 4.122 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.170     ; 7.457      ;
+-------+----------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                              ;
+-------+-----------------------------------------------------------------------------------------------------------------+-------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                       ; To Node                                               ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------+-------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 0.437 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                           ; sdram_ctrl:sdram_controller|sdram_rdy                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.097      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                                      ; sdram_ctrl:sdram_controller|r_init_tmr[10]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[0]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_refr_act                                                                          ; sdram_ctrl:sdram_controller|r_refr_act                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_wr_act                                                                            ; sdram_ctrl:sdram_controller|r_wr_act                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_wr_bctr[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                                                                        ; sdram_ctrl:sdram_controller|r_bst_stp[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_rd_bctr[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_rd_act                                                                            ; sdram_ctrl:sdram_controller|r_rd_act                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_request_complete_reg                                                                                      ; sdram_request_complete_reg                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.467 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[0]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.758      ;
; 0.500 ; seq_reg[10]                                                                                                     ; seq_reg[11]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.097      ; 0.809      ;
; 0.514 ; sdram_ctrl:sdram_controller|r_rd_act                                                                            ; sdram_ctrl:sdram_controller|ap1_rd_bst_act            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.805      ;
; 0.519 ; seq_reg[10]                                                                                                     ; sdram_ctrl:sdram_controller|sdram_rdy                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.097      ; 0.828      ;
; 0.526 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.817      ;
; 0.535 ; seq_reg[11]                                                                                                     ; seq_reg[0]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.097      ; 0.844      ;
; 0.547 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.838      ;
; 0.564 ; sdram_ctrl:sdram_controller|r_rd_reg                                                                            ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.855      ;
; 0.690 ; sdram_ctrl:sdram_controller|r_refr_act                                                                          ; sdram_ctrl:sdram_controller|r_wr_reg                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.981      ;
; 0.691 ; sdram_ctrl:sdram_controller|r_refr_act                                                                          ; sdram_ctrl:sdram_controller|r_rd_reg                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.982      ;
; 0.703 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[19] ; ram_di_reg[3]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.190      ; 1.124      ;
; 0.703 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[25] ; ram_di_reg[9]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.190      ; 1.124      ;
; 0.704 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[21] ; ram_di_reg[5]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.190      ; 1.125      ;
; 0.735 ; seq_reg[8]                                                                                                      ; seq_reg[9]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.097      ; 1.044      ;
; 0.737 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.028      ;
; 0.737 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.028      ;
; 0.740 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.031      ;
; 0.740 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.031      ;
; 0.740 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.031      ;
; 0.740 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.031      ;
; 0.741 ; seq_reg[9]                                                                                                      ; seq_reg[10]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.097      ; 1.050      ;
; 0.741 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.032      ;
; 0.742 ; seq_reg[5]                                                                                                      ; seq_reg[6]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.033      ;
; 0.742 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.033      ;
; 0.742 ; sdram_ctrl:sdram_controller|r_psel_dly[0]                                                                       ; sdram_ctrl:sdram_controller|ap1_rd_bst_act            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.033      ;
; 0.743 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                                                                        ; sdram_ctrl:sdram_controller|r_rd_bctr[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.034      ;
; 0.746 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_rd_act                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.037      ;
; 0.758 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.049      ;
; 0.759 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.050      ;
; 0.765 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_wr_act                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.056      ;
; 0.800 ; sdram_ctrl:sdram_controller|r_rd_reg                                                                            ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.091      ;
; 0.804 ; sdram_ctrl:sdram_controller|r_rd_act                                                                            ; sdram_ctrl:sdram_controller|r_rd_bctr[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.095      ;
; 0.835 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                                      ; sdram_ctrl:sdram_controller|r_init_fsm[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.126      ;
; 0.871 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[10]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.162      ;
; 0.879 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[26] ; ram_di_reg[10]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.191      ; 1.301      ;
; 0.880 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[23] ; ram_di_reg[7]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.190      ; 1.301      ;
; 0.894 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[0]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.185      ;
; 0.902 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                                      ; sdram_ctrl:sdram_controller|r_init_fsm[0]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.193      ;
; 0.931 ; seq_reg[6]                                                                                                      ; seq_reg[7]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.222      ;
; 0.962 ; seq_reg[2]                                                                                                      ; seq_reg[3]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.253      ;
; 0.962 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[18] ; ram_di_reg[2]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.191      ; 1.384      ;
; 0.963 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[24] ; ram_di_reg[8]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.191      ; 1.385      ;
; 0.968 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                                      ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.259      ;
; 0.972 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[16] ; ram_di_reg[0]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.191      ; 1.394      ;
; 0.975 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[20] ; ram_di_reg[4]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.190      ; 1.396      ;
; 0.977 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[17] ; ram_di_reg[1]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.190      ; 1.398      ;
; 0.993 ; sdram_ctrl:sdram_controller|r_psel[0]                                                                           ; sdram_ctrl:sdram_controller|r_psel_dly[0]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.285      ;
; 1.009 ; sdram_ctrl:sdram_controller|r_wr_act                                                                            ; sdram_ctrl:sdram_controller|r_wr_bctr[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.300      ;
; 1.022 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[22] ; ram_di_reg[6]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.190      ; 1.443      ;
; 1.039 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[28] ; ram_di_reg[12]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.190      ; 1.460      ;
; 1.092 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.383      ;
; 1.092 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.383      ;
; 1.094 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.385      ;
; 1.094 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.385      ;
; 1.100 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.391      ;
; 1.101 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.392      ;
; 1.102 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.393      ;
; 1.102 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.393      ;
; 1.103 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.394      ;
; 1.109 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.400      ;
; 1.110 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.401      ;
; 1.111 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.402      ;
; 1.111 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.402      ;
; 1.111 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[27] ; ram_di_reg[11]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.190      ; 1.532      ;
; 1.112 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.403      ;
; 1.174 ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1                                                           ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.465      ;
; 1.183 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                                       ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.474      ;
; 1.191 ; seq_reg[1]                                                                                                      ; seq_reg[2]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.482      ;
; 1.223 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.514      ;
; 1.225 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.516      ;
; 1.225 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.516      ;
; 1.232 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.523      ;
; 1.234 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.525      ;
; 1.234 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.525      ;
; 1.240 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.531      ;
; 1.241 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.532      ;
; 1.241 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[29] ; ram_di_reg[13]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.190      ; 1.662      ;
; 1.242 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.533      ;
; 1.243 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.534      ;
; 1.245 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[30] ; ram_di_reg[14]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.190      ; 1.666      ;
; 1.249 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.540      ;
; 1.250 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.541      ;
; 1.251 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.542      ;
; 1.252 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.543      ;
; 1.258 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[12] ; ram_di_reg[12]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.190      ; 1.679      ;
; 1.271 ; sdram_request_reg                                                                                               ; sdram_ctrl:sdram_controller|r_psel[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -0.359     ; 1.124      ;
; 1.309 ; ram_bena_reg[1]                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.599      ;
; 1.315 ; sdram_ctrl:sdram_controller|r_rd_reg                                                                            ; sdram_ctrl:sdram_controller|r_rd_act                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.596      ;
+-------+-----------------------------------------------------------------------------------------------------------------+-------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                              ;
+-------+----------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                  ; To Node                                                                                                                    ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[14]                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[14]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[15]                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[15]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[6]      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[6]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[12]                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[12]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[11]                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[11]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[7]      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[7]      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wsync_reg                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wsync_reg                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_pending_reg                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_pending_reg                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_count_reg[1]             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_count_reg[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_count_reg[2]             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_count_reg[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_count_reg[3]             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_count_reg[3]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vblank_reg                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vblank_reg                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|bitcount_reg[2]                                                       ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|bitcount_reg[2]                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|bitcount_reg[3]                                                       ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|bitcount_reg[3]                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|idle_reg[1]                                                           ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|idle_reg[1]                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|idle_reg[2]                                                           ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|idle_reg[2]                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|idle_reg[3]                                                           ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|idle_reg[3]                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|bitcount_reg[0]                                                       ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|bitcount_reg[0]                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|bitcount_reg[1]                                                       ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|bitcount_reg[1]                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|pending_keyup_reg                                                     ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|pending_keyup_reg                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|pending_extended_reg                                                  ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|pending_extended_reg                                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_ready_reg                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_ready_reg                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|first_line_of_instruction_reg         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|first_line_of_instruction_reg         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vscrol_last_enabled_reg               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vscrol_last_enabled_reg               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[29]                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[29]                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[84]                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[84]                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[27]                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[27]                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[273]                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[273]                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[85]                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[85]                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[93]                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[93]                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[21]                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[21]                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[6]                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[6]                                                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[67]                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[67]                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[46]                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[46]                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[12]                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[12]                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[13]                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[13]                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[70]                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[70]                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[75]                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[75]                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[65]                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[65]                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[42]                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[42]                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[59]                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[59]                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[3]                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[3]                                                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[364]                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[364]                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[43]                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[43]                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[68]                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[68]                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[45]                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[45]                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[76]                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[76]                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[77]                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[77]                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[73]                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[73]                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[61]                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[61]                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[69]                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[69]                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[2]                                                                 ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[2]                                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[3]                                                                 ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[3]                                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|skctl_reg[0]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|skctl_reg[0]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|syncreset_enable_divider:enable_15_div|count_reg[0]                   ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|syncreset_enable_divider:enable_15_div|count_reg[0]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|syncreset_enable_divider:enable_15_div|count_reg[2]                   ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|syncreset_enable_divider:enable_15_div|count_reg[2]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|syncreset_enable_divider:enable_15_div|count_reg[3]                   ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|syncreset_enable_divider:enable_15_div|count_reg[3]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|syncreset_enable_divider:enable_64_div|count_reg[0]                   ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|syncreset_enable_divider:enable_64_div|count_reg[0]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|syncreset_enable_divider:enable_64_div|count_reg[1]                   ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|syncreset_enable_divider:enable_64_div|count_reg[1]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[0]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[0]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[1]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[1]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[2]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[2]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[3]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[3]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[7]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[7]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[4]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[4]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[5]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[5]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[6]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[6]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[0]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[0]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[3]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[3]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[1]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[1]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[2]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[2]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[5]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[5]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[4]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[4]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[6]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[6]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[7]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[7]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer1|delay_line:underflow0_delay|shift_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer1|delay_line:underflow0_delay|shift_reg[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serin_clock_reg                                                       ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serin_clock_reg                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serin_bitcount_reg[0]                                                 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serin_bitcount_reg[0]                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serin_bitcount_reg[2]                                                 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serin_bitcount_reg[2]                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serin_bitcount_reg[3]                                                 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serin_bitcount_reg[3]                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[1]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[1]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[0]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[0]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[2]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[2]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[3]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[3]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[6]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[6]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[4]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[4]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[5]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[5]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[7]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[7]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer2|delay_line:underflow0_delay|shift_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer2|delay_line:underflow0_delay|shift_reg[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[2]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[2]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[0]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[0]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[1]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[1]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[3]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[3]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[6]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[6]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[4]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[4]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[5]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[5]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[7]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[7]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
+-------+----------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                         ;
+-------+---------------------------------------+----------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                                                        ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+----------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 5.267 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[14]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.627     ; 5.855      ;
; 5.293 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[22]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.640     ; 5.816      ;
; 5.293 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[19]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.640     ; 5.816      ;
; 5.294 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[8]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.625     ; 5.830      ;
; 5.294 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_8BIT_WRITE_ENABLE_reg    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.629     ; 5.826      ;
; 5.294 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_READ_reg                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.629     ; 5.826      ;
; 5.325 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[18]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.640     ; 5.784      ;
; 5.325 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[21]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.640     ; 5.784      ;
; 5.325 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[23]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.640     ; 5.784      ;
; 5.325 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[20]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.640     ; 5.784      ;
; 5.325 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[16]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.640     ; 5.784      ;
; 5.325 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[17]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.640     ; 5.784      ;
; 5.328 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.624     ; 5.797      ;
; 5.332 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[8]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.598     ; 5.819      ;
; 5.385 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[14]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.600     ; 5.764      ;
; 5.385 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[15]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.600     ; 5.764      ;
; 5.778 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[17]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.641     ; 5.330      ;
; 5.778 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[13]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.627     ; 5.344      ;
; 5.778 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[1]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.624     ; 5.347      ;
; 5.778 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[4]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.624     ; 5.347      ;
; 5.778 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[5]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.624     ; 5.347      ;
; 5.778 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[10]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.629     ; 5.342      ;
; 5.778 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[12]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.627     ; 5.344      ;
; 5.778 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[11]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.629     ; 5.342      ;
; 5.778 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.641     ; 5.330      ;
; 5.779 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[8]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.626     ; 5.344      ;
; 5.779 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[12]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.626     ; 5.344      ;
; 5.779 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[10]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.626     ; 5.344      ;
; 5.779 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[11]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.626     ; 5.344      ;
; 5.779 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[13]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.626     ; 5.344      ;
; 5.779 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[14]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.626     ; 5.344      ;
; 5.779 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[9]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.626     ; 5.344      ;
; 5.779 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[15]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.626     ; 5.344      ;
; 5.780 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[11]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.626     ; 5.343      ;
; 5.780 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.626     ; 5.343      ;
; 5.780 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.626     ; 5.343      ;
; 5.780 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[25]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.625     ; 5.344      ;
; 5.780 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.626     ; 5.343      ;
; 5.781 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[3]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.637     ; 5.331      ;
; 5.781 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[6]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.637     ; 5.331      ;
; 5.781 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[1]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.636     ; 5.332      ;
; 5.781 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[7]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.637     ; 5.331      ;
; 5.781 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|memory_ready_reg             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.636     ; 5.332      ;
; 5.789 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[22]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.630     ; 5.330      ;
; 5.789 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[27]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.616     ; 5.344      ;
; 5.789 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[27]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.616     ; 5.344      ;
; 5.789 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[0]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.619     ; 5.341      ;
; 5.789 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[3]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.619     ; 5.341      ;
; 5.789 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[23]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.616     ; 5.344      ;
; 5.789 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[23]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.616     ; 5.344      ;
; 5.789 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[2]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.630     ; 5.330      ;
; 5.789 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[30]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.616     ; 5.344      ;
; 5.789 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[1]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.619     ; 5.341      ;
; 5.789 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[9]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.616     ; 5.344      ;
; 5.789 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[2]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.619     ; 5.341      ;
; 5.789 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[19]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.616     ; 5.344      ;
; 5.789 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[20]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.633     ; 5.327      ;
; 5.790 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[4]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.631     ; 5.328      ;
; 5.790 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[5]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.620     ; 5.339      ;
; 5.790 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[16]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.618     ; 5.341      ;
; 5.790 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[21]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.618     ; 5.341      ;
; 5.790 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[31]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.630     ; 5.329      ;
; 5.790 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[22]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.618     ; 5.341      ;
; 5.790 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[25]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.618     ; 5.341      ;
; 5.790 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[22]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.635     ; 5.324      ;
; 5.790 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[22]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.615     ; 5.344      ;
; 5.790 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[22]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.615     ; 5.344      ;
; 5.790 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[8]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.615     ; 5.344      ;
; 5.790 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[8]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.615     ; 5.344      ;
; 5.790 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[8]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.618     ; 5.341      ;
; 5.790 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[2]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.620     ; 5.339      ;
; 5.790 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[27]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.618     ; 5.341      ;
; 5.790 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[18]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.615     ; 5.344      ;
; 5.790 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[18]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.618     ; 5.341      ;
; 5.790 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[10]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.615     ; 5.344      ;
; 5.790 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[5]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.630     ; 5.329      ;
; 5.790 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[0]    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.615     ; 5.344      ;
; 5.790 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[16]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.620     ; 5.339      ;
; 5.790 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[16]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.635     ; 5.324      ;
; 5.790 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[24]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.618     ; 5.341      ;
; 5.790 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[26]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.618     ; 5.341      ;
; 5.790 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[0]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.615     ; 5.344      ;
; 5.790 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[23]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.618     ; 5.341      ;
; 5.790 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[30]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.618     ; 5.341      ;
; 5.790 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[4]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.630     ; 5.329      ;
; 5.790 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[9]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.615     ; 5.344      ;
; 5.790 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[9]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.615     ; 5.344      ;
; 5.790 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[15]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.634     ; 5.325      ;
; 5.790 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[19]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.615     ; 5.344      ;
; 5.790 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[19]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.615     ; 5.344      ;
; 5.790 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[19]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.618     ; 5.341      ;
; 5.790 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[20]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.618     ; 5.341      ;
; 5.790 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[20]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.615     ; 5.344      ;
; 5.790 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[20]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.615     ; 5.344      ;
; 5.791 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[17]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.631     ; 5.327      ;
; 5.791 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[22]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.631     ; 5.327      ;
; 5.791 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[18]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.631     ; 5.327      ;
; 5.791 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[21]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.631     ; 5.327      ;
; 5.791 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[20]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.631     ; 5.327      ;
; 5.791 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[19]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.631     ; 5.327      ;
+-------+---------------------------------------+----------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                    ;
+-------+------------------------+----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                                  ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 7.731 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.397     ; 3.478      ;
; 7.731 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[1]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.397     ; 3.478      ;
; 7.731 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[2]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.397     ; 3.478      ;
; 7.733 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[7]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.398     ; 3.475      ;
; 7.733 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[3]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.398     ; 3.475      ;
; 7.738 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[5]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.400     ; 3.468      ;
; 7.739 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[6]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.396     ; 3.471      ;
; 7.739 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[4]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.402     ; 3.465      ;
; 7.743 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.270     ; 3.605      ;
; 7.743 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.270     ; 3.605      ;
; 7.743 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[2]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.270     ; 3.605      ;
; 7.745 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[3]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.271     ; 3.602      ;
; 7.745 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[7]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.271     ; 3.602      ;
; 7.750 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[5]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.273     ; 3.595      ;
; 7.751 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[4]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.275     ; 3.592      ;
; 7.751 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[6]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.269     ; 3.598      ;
; 7.756 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[0]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.213     ; 3.649      ;
; 7.756 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.215     ; 3.647      ;
; 7.756 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.215     ; 3.647      ;
; 7.756 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[2]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.215     ; 3.647      ;
; 7.756 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[3]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.215     ; 3.647      ;
; 7.756 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[1]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.215     ; 3.647      ;
; 7.756 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.215     ; 3.647      ;
; 7.757 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[10]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.388     ; 3.461      ;
; 7.757 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[12]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.388     ; 3.461      ;
; 7.757 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[11]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.388     ; 3.461      ;
; 7.758 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[15]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.386     ; 3.462      ;
; 7.758 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[13]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.386     ; 3.462      ;
; 7.758 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[14]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.386     ; 3.462      ;
; 7.759 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[8]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.384     ; 3.463      ;
; 7.761 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[9]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.388     ; 3.457      ;
; 7.769 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[10]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.261     ; 3.588      ;
; 7.769 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[11]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.261     ; 3.588      ;
; 7.769 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[12]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.261     ; 3.588      ;
; 7.770 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[13]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.259     ; 3.589      ;
; 7.770 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[14]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.259     ; 3.589      ;
; 7.770 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[15]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.259     ; 3.589      ;
; 7.771 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[8]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.257     ; 3.590      ;
; 7.773 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[9]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.261     ; 3.584      ;
; 7.780 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[4]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.200     ; 3.638      ;
; 7.781 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[5]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.201     ; 3.636      ;
; 7.781 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[6]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.202     ; 3.635      ;
; 7.781 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[7]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.202     ; 3.635      ;
; 7.781 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[8]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.201     ; 3.636      ;
; 7.781 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.201     ; 3.636      ;
; 8.039 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.213     ; 3.366      ;
; 8.039 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.213     ; 3.366      ;
; 8.039 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.213     ; 3.366      ;
; 8.039 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.213     ; 3.366      ;
; 8.351 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.206     ; 3.191      ;
; 8.351 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.206     ; 3.191      ;
; 8.351 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.206     ; 3.191      ;
; 8.351 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.206     ; 3.191      ;
; 8.351 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.206     ; 3.191      ;
; 8.351 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.206     ; 3.191      ;
; 8.351 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.214     ; 3.183      ;
; 8.351 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.214     ; 3.183      ;
; 8.351 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.214     ; 3.183      ;
; 8.351 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.214     ; 3.183      ;
; 8.351 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.214     ; 3.183      ;
; 8.351 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.214     ; 3.183      ;
; 8.351 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.215     ; 3.182      ;
; 8.351 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.206     ; 3.191      ;
; 8.351 ; sdram_reset_ctrl_n_reg ; ram_do_reg[8]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.206     ; 3.191      ;
; 8.351 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.206     ; 3.191      ;
; 8.351 ; sdram_reset_ctrl_n_reg ; ram_do_reg[11]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.206     ; 3.191      ;
; 8.351 ; sdram_reset_ctrl_n_reg ; ram_do_reg[14]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.206     ; 3.191      ;
; 8.351 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.206     ; 3.191      ;
; 8.351 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.206     ; 3.191      ;
; 8.351 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.206     ; 3.191      ;
; 8.351 ; sdram_reset_ctrl_n_reg ; ram_do_reg[15]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.206     ; 3.191      ;
; 8.351 ; sdram_reset_ctrl_n_reg ; ram_do_reg[19]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.206     ; 3.191      ;
; 8.351 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[0]                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.194      ;
; 8.351 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[1]                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.194      ;
; 8.352 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.204     ; 3.192      ;
; 8.352 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.204     ; 3.192      ;
; 8.352 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.204     ; 3.192      ;
; 8.352 ; sdram_reset_ctrl_n_reg ; seq_reg[5]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.204     ; 3.192      ;
; 8.352 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.204     ; 3.192      ;
; 8.352 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.204     ; 3.192      ;
; 8.352 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.205     ; 3.191      ;
; 8.352 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.205     ; 3.191      ;
; 8.352 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.205     ; 3.191      ;
; 8.352 ; sdram_reset_ctrl_n_reg ; ram_do_reg[25]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.205     ; 3.191      ;
; 8.352 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.205     ; 3.191      ;
; 8.352 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.205     ; 3.191      ;
; 8.352 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.205     ; 3.191      ;
; 8.352 ; sdram_reset_ctrl_n_reg ; ram_do_reg[5]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.205     ; 3.191      ;
; 8.352 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.205     ; 3.191      ;
; 8.352 ; sdram_reset_ctrl_n_reg ; ram_do_reg[12]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.205     ; 3.191      ;
; 8.352 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.205     ; 3.191      ;
; 8.352 ; sdram_reset_ctrl_n_reg ; ram_do_reg[13]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.205     ; 3.191      ;
; 8.352 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.205     ; 3.191      ;
; 8.352 ; sdram_reset_ctrl_n_reg ; ram_do_reg[9]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.205     ; 3.191      ;
; 8.352 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.205     ; 3.191      ;
; 8.352 ; sdram_reset_ctrl_n_reg ; ram_do_reg[20]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.205     ; 3.191      ;
; 8.352 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.214     ; 3.182      ;
; 8.354 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.206     ; 3.188      ;
; 8.354 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.206     ; 3.188      ;
; 8.354 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.206     ; 3.188      ;
+-------+------------------------+----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                      ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                                   ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 2.154 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.622      ; 3.007      ;
; 2.154 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.622      ; 3.007      ;
; 2.154 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.622      ; 3.007      ;
; 2.154 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.622      ; 3.007      ;
; 2.154 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.622      ; 3.007      ;
; 2.154 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.622      ; 3.007      ;
; 2.154 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.622      ; 3.007      ;
; 2.604 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.010      ;
; 2.604 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.010      ;
; 2.604 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.010      ;
; 2.604 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[0]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 3.014      ;
; 2.604 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[1]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.179      ; 3.014      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 3.013      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 3.013      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 3.013      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; seq_reg[5]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 3.013      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 3.013      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 3.013      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.011      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 3.012      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.011      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 3.012      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.011      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 3.012      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; ram_do_reg[25]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 3.012      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.011      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 3.012      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.011      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 3.012      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 3.012      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.011      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; ram_do_reg[5]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 3.012      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.011      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; ram_do_reg[8]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.011      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.011      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 3.012      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; ram_do_reg[12]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 3.012      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 3.012      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; ram_do_reg[11]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.011      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; ram_do_reg[13]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 3.012      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; ram_do_reg[14]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.011      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.011      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 3.012      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; ram_do_reg[9]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 3.012      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.011      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 3.012      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.011      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; ram_do_reg[15]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.011      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; ram_do_reg[19]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.011      ;
; 2.605 ; sdram_reset_ctrl_n_reg ; ram_do_reg[20]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 3.012      ;
; 2.606 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 3.013      ;
; 2.606 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 3.013      ;
; 2.606 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 3.013      ;
; 2.606 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 3.013      ;
; 2.606 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 3.013      ;
; 2.607 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 3.015      ;
; 2.607 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 3.015      ;
; 2.607 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 3.015      ;
; 2.607 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 3.015      ;
; 2.607 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 3.015      ;
; 2.607 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 3.015      ;
; 2.607 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 3.015      ;
; 2.607 ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.013      ;
; 2.607 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.013      ;
; 2.607 ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.013      ;
; 2.607 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.178      ; 3.016      ;
; 2.607 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 3.015      ;
; 2.607 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 3.015      ;
; 2.607 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.177      ; 3.015      ;
; 2.607 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.013      ;
; 2.608 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.014      ;
; 2.608 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.014      ;
; 2.608 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.014      ;
; 2.608 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.014      ;
; 2.608 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.014      ;
; 2.608 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.014      ;
; 2.608 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.014      ;
; 2.608 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.014      ;
; 2.608 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.014      ;
; 2.608 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.014      ;
; 2.608 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.014      ;
; 2.608 ; sdram_reset_ctrl_n_reg ; ram_di_reg[6]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.014      ;
; 2.608 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.014      ;
; 2.608 ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.014      ;
; 2.608 ; sdram_reset_ctrl_n_reg ; ram_di_reg[11]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.014      ;
; 2.608 ; sdram_reset_ctrl_n_reg ; ram_di_reg[12]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.014      ;
; 2.608 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.014      ;
; 2.608 ; sdram_reset_ctrl_n_reg ; ram_di_reg[14]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.014      ;
; 2.608 ; sdram_reset_ctrl_n_reg ; ram_di_reg[15]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.014      ;
; 2.609 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 3.007      ;
; 2.610 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 3.008      ;
; 2.610 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 3.008      ;
; 2.610 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 3.008      ;
; 2.610 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 3.008      ;
; 2.610 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 3.008      ;
; 2.610 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 3.008      ;
; 2.610 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.166      ; 3.007      ;
; 2.869 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.173      ; 3.187      ;
; 2.869 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.173      ; 3.187      ;
; 2.870 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.172      ; 3.187      ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                               ;
+-------+-------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node         ; To Node                                                                                                                                                 ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 3.646 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[0]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.629      ; 4.487      ;
; 3.646 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[4]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.629      ; 4.487      ;
; 3.670 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[4]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.600      ; 4.482      ;
; 4.131 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[1][0]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 4.447      ;
; 4.131 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[0][0]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 4.447      ;
; 4.131 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[3][7]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 4.447      ;
; 4.131 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[2][7]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 4.447      ;
; 4.131 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[1][7]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 4.447      ;
; 4.131 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[0][7]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 4.447      ;
; 4.131 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[4][4]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 4.447      ;
; 4.131 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[3][4]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 4.447      ;
; 4.131 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[2][4]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 4.447      ;
; 4.131 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[1][4]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 4.447      ;
; 4.131 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[0][4]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 4.447      ;
; 4.131 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[4][1]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 4.447      ;
; 4.131 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp0_delay|shift_reg[4][7]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 4.447      ;
; 4.131 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp0_delay|shift_reg[3][0]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 4.447      ;
; 4.131 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm1_delay|shift_reg[4][6]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 4.447      ;
; 4.131 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm1_delay|shift_reg[4][2]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 4.447      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|bincnt_reg[0]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.115      ; 4.459      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|bincnt_reg[1]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.115      ; 4.459      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|bincnt_reg[2]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.115      ; 4.459      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|bincnt_reg[3]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.115      ; 4.459      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|bincnt_reg[4]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.115      ; 4.459      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|bincnt_reg[5]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.115      ; 4.459      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[0]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 4.448      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[4][0]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 4.448      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[3][0]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 4.448      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[2][0]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 4.448      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[7]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 4.448      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[4][7]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 4.448      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[4]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 4.448      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_raw_reg[7]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 4.449      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_raw_reg[0]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 4.449      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_raw_reg[3]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 4.448      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[4][3]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 4.448      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[3][3]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 4.448      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[2][3]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 4.448      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[1][3]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 4.448      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp0_delay|shift_reg[3][7]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.103      ; 4.447      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp0_delay|shift_reg[2][7]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.103      ; 4.447      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp0_delay|shift_reg[1][7]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.103      ; 4.447      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp0_delay|shift_reg[0][7]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.103      ; 4.447      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp0_delay|shift_reg[4][6]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.103      ; 4.447      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp0_delay|shift_reg[3][6]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.103      ; 4.447      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp0_delay|shift_reg[2][6]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.103      ; 4.447      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp0_delay|shift_reg[1][6]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.103      ; 4.447      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp0_delay|shift_reg[0][6]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.103      ; 4.447      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp0_delay|shift_reg[4][3]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 4.448      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp0_delay|shift_reg[3][3]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 4.448      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp0_delay|shift_reg[2][3]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 4.448      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp0_delay|shift_reg[1][3]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 4.448      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp0_delay|shift_reg[4][0]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 4.448      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp0_delay|shift_reg[2][0]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.103      ; 4.447      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp3_delay|shift_reg[4][3]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 4.448      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp3_delay|shift_reg[3][3]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 4.448      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp3_delay|shift_reg[2][3]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 4.448      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp3_delay|shift_reg[1][3]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 4.448      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_raw_reg[2]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 4.449      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp3_delay|shift_reg[4][2]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 4.448      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_raw_reg[7]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 4.449      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp3_delay|shift_reg[4][7]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 4.448      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp3_delay|shift_reg[3][7]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 4.448      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp3_delay|shift_reg[2][7]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 4.448      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp3_delay|shift_reg[1][7]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 4.448      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp3_delay|shift_reg[0][7]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.103      ; 4.447      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp3_delay|shift_reg[1][6]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.103      ; 4.447      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp3_delay|shift_reg[0][6]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.103      ; 4.447      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm1_delay|shift_reg[3][6]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 4.448      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm1_delay|shift_reg[2][6]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 4.448      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm1_delay|shift_reg[1][6]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 4.448      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_raw_reg[7]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.103      ; 4.447      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[4][7]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.103      ; 4.447      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[3][7]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.103      ; 4.447      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[2][7]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.103      ; 4.447      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[1][7]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.103      ; 4.447      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[0][7]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.103      ; 4.447      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_raw_reg[6]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.103      ; 4.447      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[4][6]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.103      ; 4.447      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[3][6]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.103      ; 4.447      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[2][6]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.103      ; 4.447      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[1][6]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.103      ; 4.447      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[0][6]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.103      ; 4.447      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_raw_reg[5]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.103      ; 4.447      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[4][5]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.103      ; 4.447      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[3][5]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.103      ; 4.447      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[2][5]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.103      ; 4.447      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizep1_delay|shift_reg[3][1]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 4.448      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizep1_delay|shift_reg[2][1]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 4.448      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizep1_delay|shift_reg[1][1]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 4.448      ;
; 4.132 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:prior_short_delay|shift_reg[1][3]                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.103      ; 4.447      ;
; 4.133 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|control_pressed_reg ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.113      ; 4.458      ;
; 4.133 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|break_pressed_reg   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.114      ; 4.459      ;
; 4.133 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|shift_pressed_reg   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.114      ; 4.459      ;
; 4.133 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[4][3]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 4.450      ;
; 4.133 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[3][3]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 4.450      ;
; 4.133 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[2][3]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 4.450      ;
; 4.133 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[1][3]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 4.450      ;
; 4.133 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[1]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.099      ; 4.444      ;
; 4.133 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[1][1]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.101      ; 4.446      ;
+-------+-------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                        ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                         ; Clock Edge ; Target                                                    ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; 5.544 ; 5.764        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|sdram_rdy                     ;
; 5.544 ; 5.764        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_reg                                         ;
; 5.544 ; 5.764        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[0]                                                ;
; 5.544 ; 5.764        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[10]                                               ;
; 5.544 ; 5.764        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[11]                                               ;
; 5.544 ; 5.764        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[8]                                                ;
; 5.544 ; 5.764        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[9]                                                ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[0]                                             ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[10]                                            ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[2]                                             ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[3]                                             ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[4]                                             ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[5]                                             ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[8]                                             ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_reg                      ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_act                    ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_reg                      ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[4]                                                ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[11]                                            ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[12]                                            ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[13]                                            ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[14]                                            ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[15]                                            ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[1]                                             ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[6]                                             ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[7]                                             ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[9]                                             ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ;
; 5.572 ; 5.792        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ;
; 5.572 ; 5.792        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ;
; 5.572 ; 5.792        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel[0]                     ;
; 5.572 ; 5.792        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ;
; 5.572 ; 5.792        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_act                      ;
; 5.572 ; 5.792        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ;
; 5.572 ; 5.792        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_req                    ;
; 5.572 ; 5.792        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_act                      ;
; 5.572 ; 5.792        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ;
; 5.572 ; 5.792        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_complete_reg                                ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[0]                                           ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[1]                                           ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[10]                                            ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[12]                                            ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[13]                                            ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[17]                                            ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[18]                                            ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[1]                                             ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[20]                                            ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[21]                                            ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[25]                                            ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[26]                                            ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[28]                                            ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[29]                                            ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[2]                                             ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[4]                                             ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[5]                                             ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[9]                                             ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[1]                                                ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[2]                                                ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[3]                                                ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[5]                                                ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[6]                                                ;
; 5.573 ; 5.793        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[7]                                                ;
; 5.574 ; 5.794        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[0]                                             ;
; 5.574 ; 5.794        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[11]                                            ;
; 5.574 ; 5.794        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[14]                                            ;
; 5.574 ; 5.794        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[15]                                            ;
; 5.574 ; 5.794        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[16]                                            ;
; 5.574 ; 5.794        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[19]                                            ;
; 5.574 ; 5.794        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[22]                                            ;
; 5.574 ; 5.794        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[23]                                            ;
; 5.574 ; 5.794        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[24]                                            ;
; 5.574 ; 5.794        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[27]                                            ;
; 5.574 ; 5.794        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[30]                                            ;
; 5.574 ; 5.794        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[31]                                            ;
; 5.574 ; 5.794        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[3]                                             ;
; 5.574 ; 5.794        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[6]                                             ;
; 5.574 ; 5.794        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[7]                                             ;
; 5.574 ; 5.794        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[8]                                             ;
; 5.662 ; 5.820        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[0]                   ;
; 5.662 ; 5.820        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[1]                   ;
; 5.662 ; 5.820        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[2]                   ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                 ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                         ; Clock Edge ; Target                                                                                                                                            ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------+
; 17.297 ; 17.517       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|addr_r[4]                                                                                   ;
; 17.298 ; 17.518       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[0]                                                                                                 ;
; 17.299 ; 17.519       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|addr_r[3]                                                                                   ;
; 17.309 ; 17.529       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                                                                                ;
; 17.310 ; 17.530       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[3]                                                                                                 ;
; 17.312 ; 17.532       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[4]                                              ;
; 17.317 ; 17.537       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|cfg_bank[13]                      ;
; 17.317 ; 17.537       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|cfg_bank[14]                      ;
; 17.317 ; 17.537       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|cfg_bank[15]                      ;
; 17.317 ; 17.537       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|cfg_bank[16]                      ;
; 17.317 ; 17.537       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|cfg_bank[17]                      ;
; 17.317 ; 17.537       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|cfg_bank[18]                      ;
; 17.317 ; 17.537       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|cfg_bank[19]                      ;
; 17.317 ; 17.537       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|ram_bank[13]                    ;
; 17.317 ; 17.537       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|ram_bank[14]                    ;
; 17.317 ; 17.537       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|ram_bank[15]                    ;
; 17.317 ; 17.537       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|rom_bank[13]                    ;
; 17.317 ; 17.537       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|rom_bank[14]                    ;
; 17.317 ; 17.537       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|rom_bank[15]                    ;
; 17.317 ; 17.537       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_input_reg[0]                                               ;
; 17.317 ; 17.537       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[14]                                                                                              ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|cart_mode_prev[0]                 ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|cart_mode_prev[1]                 ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|cart_mode_prev[2]                 ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|cart_mode_prev[3]                 ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|cart_mode_prev[4]                 ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|cart_mode_prev[5]                 ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|cfg_bank[20]                      ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|oss_bank[0]                       ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|oss_bank[1]                       ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[10]                                   ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[11]                                   ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[12]                                   ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[13]                                   ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[15]                                   ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[16]                                   ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[18]                                   ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[19]                                   ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[1]                                    ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[20]                                   ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[21]                                   ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[22]                                   ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[24]                                   ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[26]                                   ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[27]                                   ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[28]                                   ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[29]                                   ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[30]                                   ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[31]                                   ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[5]                                    ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[8]                                    ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[9]                                    ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|cpu_fetch_real_reg                                   ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg                                       ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|write_enable_reg                                     ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[18][5]                ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[19][5]                ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[20][5]                ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[21][5]                ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[22][5]                ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[23][5]                ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[24][5]                ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[25][5]                ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[26][5]                ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[27][5]                ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[28][5]                ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[29][5]                ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[30][5]                ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|PC[10]                                ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|PC[13]                                ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|PC[2]                                 ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cycle2                    ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cycleBranchTaken          ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cycleJump                 ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cycleStack1               ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cycleStack2               ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.opcodeFetch               ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[0]                                              ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|delay_line:delay_line_phase|shift_reg[10]           ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|delay_line:delay_line_phase|shift_reg[11]           ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|delay_line:delay_line_phase|shift_reg[12]           ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|delay_line:delay_line_phase|shift_reg[13]           ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|delay_line:delay_line_phase|shift_reg[14]           ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|delay_line:delay_line_phase|shift_reg[6]            ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|delay_line:delay_line_phase|shift_reg[7]            ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|delay_line:delay_line_phase|shift_reg[8]            ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|delay_line:delay_line_phase|shift_reg[9]            ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|oldcpu_pending_reg                                  ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[10]                                 ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[11]                                 ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[12]                                 ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[13]                                 ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[14]                                 ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[15]                                 ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[1]                                  ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[2]                                  ;
; 17.318 ; 17.538       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[3]                                  ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                  ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                        ; Clock Edge ; Target                                                                                             ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------+
; 17.584 ; 17.584       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.584 ; 17.584       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.584 ; 17.584       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.584 ; 17.584       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 17.589 ; 17.589       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.589 ; 17.589       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.596 ; 17.596       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.645 ; 17.645       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.652 ; 17.652       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.652 ; 17.652       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.657 ; 17.657       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.657 ; 17.657       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.657 ; 17.657       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.657 ; 17.657       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'FPGA_CLK'                                                                                                                       ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------+
; Slack   ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                                                 ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------+
; 99.862  ; 99.862       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 99.862  ; 99.862       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 99.888  ; 99.888       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                       ;
; 99.929  ; 99.929       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 100.000 ; 100.000      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                       ;
; 100.000 ; 100.000      ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                       ;
; 100.070 ; 100.070      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 100.112 ; 100.112      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                       ;
; 100.137 ; 100.137      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 100.137 ; 100.137      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 196.000 ; 200.000      ; 4.000          ; Port Rate        ; FPGA_CLK ; Rise       ; FPGA_CLK                                                                               ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                             ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 3.046 ; 3.153 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.025 ; 3.132 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.025 ; 3.132 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.025 ; 3.132 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.036 ; 3.143 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.040 ; 3.147 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.038 ; 3.145 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.034 ; 3.141 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.046 ; 3.153 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.032 ; 3.139 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.036 ; 3.143 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.036 ; 3.143 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.036 ; 3.143 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.026 ; 3.133 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 3.024 ; 3.131 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 3.014 ; 3.121 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 3.024 ; 3.131 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; 5.841 ; 6.163 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; 4.788 ; 5.026 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; 4.106 ; 4.367 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; 3.866 ; 4.062 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; 4.172 ; 4.382 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; 5.841 ; 6.163 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; 6.428 ; 6.805 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; 4.218 ; 4.394 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; 4.607 ; 4.792 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; 4.560 ; 4.798 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; 4.473 ; 4.762 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; 6.428 ; 6.805 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; 6.695 ; 6.984 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; 5.667 ; 5.990 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; 4.278 ; 4.492 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; -2.018 ; -2.125 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; -2.030 ; -2.137 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; -2.030 ; -2.137 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; -2.030 ; -2.137 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; -2.040 ; -2.147 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; -2.045 ; -2.152 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; -2.042 ; -2.149 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; -2.039 ; -2.146 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; -2.050 ; -2.157 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; -2.036 ; -2.143 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; -2.040 ; -2.147 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; -2.040 ; -2.147 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; -2.040 ; -2.147 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; -2.030 ; -2.137 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; -2.028 ; -2.135 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; -2.018 ; -2.125 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; -2.028 ; -2.135 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; -2.799 ; -2.979 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; -3.650 ; -3.846 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; -2.948 ; -3.176 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; -2.799 ; -2.979 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; -3.030 ; -3.202 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; -3.049 ; -3.219 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; -3.134 ; -3.296 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; -3.134 ; -3.296 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; -3.508 ; -3.681 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; -3.431 ; -3.628 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; -3.381 ; -3.652 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; -3.301 ; -3.537 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; -5.503 ; -5.773 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; -4.523 ; -4.821 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; -3.194 ; -3.392 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                       ;
+-----------------+------------+--------+--------+------------+-------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                               ;
+-----------------+------------+--------+--------+------------+-------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 4.389  ; 3.932  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 3.289  ; 3.000  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 3.279  ; 2.990  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 3.279  ; 2.990  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 3.279  ; 2.990  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 3.284  ; 2.995  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 3.293  ; 3.004  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 3.302  ; 3.013  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 4.389  ; 3.932  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 3.303  ; 3.014  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 3.313  ; 3.024  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 3.289  ; 3.000  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 4.376  ; 3.919  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 3.290  ; 3.001  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 4.376  ; 3.919  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 4.388  ; 3.931  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 3.300  ; 3.011  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 4.450  ; 3.995  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 3.574  ; 3.263  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 3.574  ; 3.263  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 3.574  ; 3.263  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 4.430  ; 3.975  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 4.425  ; 3.970  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 2.356  ; 2.151  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 3.477  ; 3.180  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 3.486  ; 3.189  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 3.608  ; 3.297  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 4.450  ; 3.995  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 3.604  ; 3.293  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 3.604  ; 3.293  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 3.594  ; 3.283  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 4.442  ; 3.987  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 3.586  ; 3.275  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 3.596  ; 3.285  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 3.591  ; 3.845  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 3.591  ; 3.845  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 2.907  ; 3.119  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 3.300  ; 3.011  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 3.311  ; 3.022  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 7.751  ; 7.919  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 2.919  ; 2.917  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 4.404  ; 4.223  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 6.842  ; 7.052  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 3.466  ; 3.623  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]        ; FPGA_CLK   ; 11.927 ; 11.996 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]       ; FPGA_CLK   ; 10.040 ; 9.901  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]       ; FPGA_CLK   ; 11.927 ; 11.996 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]       ; FPGA_CLK   ; 9.345  ; 9.019  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]       ; FPGA_CLK   ; 11.131 ; 11.421 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]        ; FPGA_CLK   ; 11.306 ; 11.485 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]       ; FPGA_CLK   ; 11.306 ; 11.485 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]       ; FPGA_CLK   ; 9.184  ; 8.904  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]       ; FPGA_CLK   ; 8.549  ; 8.351  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]       ; FPGA_CLK   ; 7.727  ; 7.380  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS          ; FPGA_CLK   ; 9.228  ; 9.156  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]        ; FPGA_CLK   ; 9.794  ; 9.496  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]       ; FPGA_CLK   ; 8.957  ; 8.709  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]       ; FPGA_CLK   ; 9.794  ; 9.496  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]       ; FPGA_CLK   ; 8.931  ; 8.536  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]       ; FPGA_CLK   ; 8.791  ; 8.493  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS          ; FPGA_CLK   ; 2.284  ; 2.160  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 9.086  ;        ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;        ; 8.846  ; Fall       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+-----------------+------------+--------+--------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                             ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 2.417 ; 2.133 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 2.427 ; 2.143 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 2.417 ; 2.133 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 2.417 ; 2.133 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 2.417 ; 2.133 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 2.422 ; 2.138 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 2.431 ; 2.147 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 2.440 ; 2.156 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 3.573 ; 3.117 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 2.441 ; 2.157 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 2.451 ; 2.167 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 2.427 ; 2.143 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 2.429 ; 2.145 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 2.429 ; 2.145 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 3.560 ; 3.104 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 3.572 ; 3.116 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 2.439 ; 2.155 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 1.542 ; 1.338 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 2.712 ; 2.407 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 2.712 ; 2.407 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 2.712 ; 2.407 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 3.616 ; 3.162 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 3.612 ; 3.158 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 1.542 ; 1.338 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 2.615 ; 2.324 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 2.623 ; 2.332 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 2.745 ; 2.440 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 3.636 ; 3.182 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 2.741 ; 2.436 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 2.741 ; 2.436 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 2.731 ; 2.426 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 3.628 ; 3.174 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 2.723 ; 2.418 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 2.733 ; 2.428 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 2.061 ; 2.271 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 2.717 ; 2.967 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 2.061 ; 2.271 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 2.439 ; 2.155 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 2.449 ; 2.165 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 6.839 ; 7.015 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 2.097 ; 2.095 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 3.509 ; 3.332 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 5.960 ; 6.174 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 2.605 ; 2.760 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]        ; FPGA_CLK   ; 4.987 ; 4.782 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]       ; FPGA_CLK   ; 5.177 ; 4.977 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]       ; FPGA_CLK   ; 7.496 ; 7.690 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]       ; FPGA_CLK   ; 4.987 ; 4.782 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]       ; FPGA_CLK   ; 7.593 ; 7.758 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]        ; FPGA_CLK   ; 4.572 ; 4.340 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]       ; FPGA_CLK   ; 7.335 ; 7.503 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]       ; FPGA_CLK   ; 4.572 ; 4.340 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]       ; FPGA_CLK   ; 4.686 ; 4.475 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]       ; FPGA_CLK   ; 4.708 ; 4.359 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS          ; FPGA_CLK   ; 6.838 ; 6.736 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]        ; FPGA_CLK   ; 4.769 ; 4.427 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]       ; FPGA_CLK   ; 5.050 ; 4.722 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]       ; FPGA_CLK   ; 4.769 ; 4.427 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]       ; FPGA_CLK   ; 5.362 ; 5.090 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]       ; FPGA_CLK   ; 5.244 ; 4.967 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS          ; FPGA_CLK   ; 1.468 ; 1.345 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 8.316 ;       ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 8.080 ; Fall       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 3.169 ; 3.169 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.177 ; 3.177 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.177 ; 3.177 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.177 ; 3.177 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.624 ; 3.624 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 4.038 ; 4.038 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 4.071 ; 4.071 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 4.165 ; 4.165 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 4.311 ; 4.311 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.948 ; 3.948 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.587 ; 3.587 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.210 ; 3.210 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.210 ; 3.210 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.200 ; 3.200 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 3.179 ; 3.179 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 3.169 ; 3.169 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 3.179 ; 3.179 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 4.864 ; 4.480 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                             ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.819 ; 1.848 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.827 ; 1.856 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.827 ; 1.856 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.827 ; 1.856 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.256 ; 2.285 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.653 ; 2.682 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.685 ; 2.714 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.776 ; 2.805 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.916 ; 2.945 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.568 ; 2.597 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.221 ; 2.250 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.859 ; 1.888 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.859 ; 1.888 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.849 ; 1.878 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 1.829 ; 1.858 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.819 ; 1.848 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.829 ; 1.858 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.854 ; 3.486 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                            ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.857     ; 3.097     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.902     ; 3.142     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.902     ; 3.142     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.902     ; 3.142     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.326     ; 3.566     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.717     ; 3.957     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.746     ; 3.986     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.815     ; 4.055     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.962     ; 4.202     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.570     ; 3.810     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.235     ; 3.475     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.887     ; 3.127     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.887     ; 3.127     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.877     ; 3.117     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.867     ; 3.107     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.857     ; 3.097     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.867     ; 3.107     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 4.265     ; 4.649     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                                    ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.750     ; 1.750     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.793     ; 1.793     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.793     ; 1.793     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.793     ; 1.793     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.201     ; 2.201     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.576     ; 2.576     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.604     ; 2.604     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.670     ; 2.670     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.811     ; 2.811     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.435     ; 2.435     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.114     ; 2.114     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.780     ; 1.780     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.780     ; 1.780     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.770     ; 1.770     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 1.760     ; 1.760     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.750     ; 1.750     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.760     ; 1.760     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.280     ; 3.648     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+


----------------------------------------------
; Slow 1200mV 85C Model Metastability Report ;
----------------------------------------------
No synchronizer chains to report.


+---------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Fmax Summary                                                                                   ;
+------------+-----------------+-------------------------------------------------------------------------------+------+
; Fmax       ; Restricted Fmax ; Clock Name                                                                    ; Note ;
+------------+-----------------+-------------------------------------------------------------------------------+------+
; 48.37 MHz  ; 48.37 MHz       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;      ;
; 128.34 MHz ; 128.34 MHz      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;      ;
+------------+-----------------+-------------------------------------------------------------------------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+--------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup Summary                                                                     ;
+-------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                         ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.402 ; -0.874        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 3.355  ; 0.000         ;
+-------------------------------------------------------------------------------+--------+---------------+


+-------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold Summary                                                                     ;
+-------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                         ; Slack ; End Point TNS ;
+-------------------------------------------------------------------------------+-------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.387 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.402 ; 0.000         ;
+-------------------------------------------------------------------------------+-------+---------------+


+-------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery Summary                                                                 ;
+-------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                         ; Slack ; End Point TNS ;
+-------------------------------------------------------------------------------+-------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 5.816 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.123 ; 0.000         ;
+-------------------------------------------------------------------------------+-------+---------------+


+-------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal Summary                                                                  ;
+-------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                         ; Slack ; End Point TNS ;
+-------------------------------------------------------------------------------+-------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1.923 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 3.282 ; 0.000         ;
+-------------------------------------------------------------------------------+-------+---------------+


+--------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width Summary                                                       ;
+-------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                         ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.532  ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.272 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]  ; 17.587 ; 0.000         ;
; FPGA_CLK                                                                      ; 99.837 ; 0.000         ;
+-------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                        ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                         ; To Node                                      ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; -0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.161     ; 11.864     ;
; -0.299 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.177     ; 11.745     ;
; -0.277 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.199     ; 11.701     ;
; -0.269 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[17]                                                                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.170     ; 11.722     ;
; -0.221 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.177     ; 11.667     ;
; -0.218 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.199     ; 11.642     ;
; -0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.200     ; 11.610     ;
; -0.184 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 11.604     ;
; -0.171 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.212     ; 11.582     ;
; -0.163 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 11.610     ;
; -0.135 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[22]                                                                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.170     ; 11.588     ;
; -0.133 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.173     ; 11.583     ;
; -0.128 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.173     ; 11.578     ;
; -0.107 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.159     ; 11.571     ;
; -0.072 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 11.520     ;
; -0.070 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.177     ; 11.516     ;
; -0.061 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.160     ; 11.524     ;
; -0.025 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 11.459     ;
; -0.013 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 11.433     ;
; -0.003 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.211     ; 11.415     ;
; 0.005  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[17]                                                                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 11.436     ;
; 0.006  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.200     ; 11.417     ;
; 0.006  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 11.442     ;
; 0.007  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.173     ; 11.443     ;
; 0.012  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[18]                                                                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.170     ; 11.441     ;
; 0.014  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.188     ; 11.421     ;
; 0.018  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.197     ; 11.408     ;
; 0.020  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 11.414     ;
; 0.026  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[17]                                                                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.168     ; 11.429     ;
; 0.035  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[19]                                                                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.170     ; 11.418     ;
; 0.042  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 11.405     ;
; 0.053  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 11.381     ;
; 0.056  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.211     ; 11.356     ;
; 0.064  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.198     ; 11.361     ;
; 0.067  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.177     ; 11.379     ;
; 0.071  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.200     ; 11.352     ;
; 0.072  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[17]                                                                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.169     ; 11.382     ;
; 0.077  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.197     ; 11.349     ;
; 0.082  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.212     ; 11.329     ;
; 0.090  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.215     ; 11.318     ;
; 0.092  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.198     ; 11.333     ;
; 0.098  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[13]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 11.343     ;
; 0.098  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 11.336     ;
; 0.110  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 11.324     ;
; 0.111  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.201     ; 11.311     ;
; 0.112  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.188     ; 11.323     ;
; 0.114  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.161     ; 11.348     ;
; 0.120  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 11.327     ;
; 0.123  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.198     ; 11.302     ;
; 0.124  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[13]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.200     ; 11.299     ;
; 0.125  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.215     ; 11.283     ;
; 0.130  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.215     ; 11.278     ;
; 0.132  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 11.317     ;
; 0.132  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.211     ; 11.280     ;
; 0.133  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.212     ; 11.278     ;
; 0.135  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.215     ; 11.273     ;
; 0.139  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[22]                                                                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 11.302     ;
; 0.140  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[17]                                                                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 11.301     ;
; 0.154  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.199     ; 11.270     ;
; 0.157  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 11.291     ;
; 0.157  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.202     ; 11.264     ;
; 0.160  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[22]                                                                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.168     ; 11.295     ;
; 0.178  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 11.270     ;
; 0.180  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[13]                                                                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.200     ; 11.243     ;
; 0.185  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 11.256     ;
; 0.188  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 11.246     ;
; 0.191  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.211     ; 11.221     ;
; 0.204  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 11.230     ;
; 0.206  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[22]                                                                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.169     ; 11.248     ;
; 0.216  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.211     ; 11.196     ;
; 0.225  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.215     ; 11.183     ;
; 0.243  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.201     ; 11.179     ;
; 0.244  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|oss_bank[1]                       ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.163     ; 11.216     ;
; 0.246  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.198     ; 11.179     ;
; 0.246  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.188     ; 11.189     ;
; 0.249  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[4]                             ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.185     ; 11.189     ;
; 0.249  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 11.185     ;
; 0.262  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.177     ; 11.184     ;
; 0.271  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 11.176     ;
; 0.271  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.211     ; 11.141     ;
; 0.274  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[22]                                                                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 11.167     ;
; 0.280  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.212     ; 11.131     ;
; 0.281  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[20]                                                                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.170     ; 11.172     ;
; 0.285  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.181     ; 11.157     ;
; 0.286  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[18]                                                                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 11.155     ;
; 0.290  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.199     ; 11.134     ;
; 0.294  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.173     ; 11.156     ;
; 0.294  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.175     ; 11.154     ;
; 0.298  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[17]                                                                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.170     ; 11.155     ;
; 0.307  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[18]                                                                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.168     ; 11.148     ;
; 0.309  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[19]                                                                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 11.132     ;
; 0.312  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[17]                                                                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 11.129     ;
; 0.326  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|sic_axxx_enable                   ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.170     ; 11.127     ;
; 0.328  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.202     ; 11.093     ;
; 0.330  ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[19]                                                                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.168     ; 11.125     ;
; 0.330  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[13]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.200     ; 11.093     ;
; 0.339  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 11.095     ;
; 0.340  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.212     ; 11.071     ;
; 0.340  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.177     ; 11.106     ;
; 0.341  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 11.093     ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                            ;
+-------+----------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                  ; To Node                                                                                                                                                  ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 3.355 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.180     ; 8.215      ;
; 3.424 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.180     ; 8.146      ;
; 3.542 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 8.043      ;
; 3.660 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[2]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.161     ; 7.929      ;
; 3.660 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[3]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.161     ; 7.929      ;
; 3.673 ; ram_do_reg[1]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.180     ; 7.897      ;
; 3.686 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[29]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.179     ; 7.885      ;
; 3.749 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[0]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 7.825      ;
; 3.779 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.180     ; 7.791      ;
; 3.789 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[4]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.150     ; 7.811      ;
; 3.862 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.180     ; 7.708      ;
; 3.912 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 7.673      ;
; 3.921 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[41]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.167     ; 7.662      ;
; 3.933 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_noise_filter:pokey_noise_filter0|out_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 7.661      ;
; 3.941 ; ram_do_reg[1]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[27]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 7.634      ;
; 3.984 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[38]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.168     ; 7.598      ;
; 4.031 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[7]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 7.555      ;
; 4.031 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[4]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 7.555      ;
; 4.031 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[2]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 7.555      ;
; 4.031 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[1]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 7.555      ;
; 4.031 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[0]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 7.555      ;
; 4.031 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[3]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 7.555      ;
; 4.031 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[5]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 7.555      ;
; 4.031 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[6]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 7.555      ;
; 4.050 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[7]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.149     ; 7.551      ;
; 4.050 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[6]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.149     ; 7.551      ;
; 4.050 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[5]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.149     ; 7.551      ;
; 4.050 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[3]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.149     ; 7.551      ;
; 4.050 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[1]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.149     ; 7.551      ;
; 4.050 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[0]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.149     ; 7.551      ;
; 4.050 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[2]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.149     ; 7.551      ;
; 4.058 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.169     ; 7.523      ;
; 4.058 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 7.527      ;
; 4.072 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_noise_filter:pokey_noise_filter1|out_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 7.502      ;
; 4.080 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 7.505      ;
; 4.102 ; ram_do_reg[1]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 7.483      ;
; 4.126 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[2]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.149     ; 7.475      ;
; 4.165 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.154     ; 7.431      ;
; 4.165 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.154     ; 7.431      ;
; 4.165 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.154     ; 7.431      ;
; 4.165 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.154     ; 7.431      ;
; 4.165 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.154     ; 7.431      ;
; 4.165 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[5] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.154     ; 7.431      ;
; 4.190 ; ram_do_reg[1]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.169     ; 7.391      ;
; 4.219 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[0]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 7.355      ;
; 4.238 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.169     ; 7.343      ;
; 4.268 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 7.317      ;
; 4.276 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[19]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 7.309      ;
; 4.278 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[39]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 7.297      ;
; 4.345 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 7.228      ;
; 4.345 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[1]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 7.228      ;
; 4.345 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[2]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 7.228      ;
; 4.345 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[3]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 7.228      ;
; 4.345 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[4]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 7.228      ;
; 4.345 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[5]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 7.228      ;
; 4.345 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[6]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 7.228      ;
; 4.345 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[7]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 7.228      ;
; 4.347 ; ram_do_reg[0]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.169     ; 7.234      ;
; 4.348 ; ram_do_reg[0]              ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[0]                                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.149     ; 7.253      ;
; 4.356 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[0]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 7.218      ;
; 4.366 ; ram_do_reg[1]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[0]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.176     ; 7.208      ;
; 4.376 ; ram_do_reg[1]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 7.209      ;
; 4.384 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[37]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.167     ; 7.199      ;
; 4.387 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[7]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 7.199      ;
; 4.387 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[5]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 7.199      ;
; 4.387 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[4]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 7.199      ;
; 4.387 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[2]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 7.199      ;
; 4.387 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[1]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 7.199      ;
; 4.387 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[0]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 7.199      ;
; 4.387 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[3]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 7.199      ;
; 4.387 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[6]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 7.199      ;
; 4.390 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.169     ; 7.191      ;
; 4.404 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 7.181      ;
; 4.407 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_noise_filter:pokey_noise_filter3|out_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.167     ; 7.176      ;
; 4.425 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[6]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.150     ; 7.175      ;
; 4.425 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[5]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.150     ; 7.175      ;
; 4.425 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[1]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.150     ; 7.175      ;
; 4.425 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[0]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.150     ; 7.175      ;
; 4.425 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[3]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.150     ; 7.175      ;
; 4.425 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[4]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.150     ; 7.175      ;
; 4.425 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[7]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.150     ; 7.175      ;
; 4.427 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[38]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.168     ; 7.155      ;
; 4.458 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_noise_filter:pokey_noise_filter0|out_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 7.128      ;
; 4.469 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[27]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 7.106      ;
; 4.470 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer1|count_reg[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.180     ; 7.100      ;
; 4.470 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer1|count_reg[1]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.180     ; 7.100      ;
; 4.470 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer1|count_reg[2]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.180     ; 7.100      ;
; 4.470 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer1|count_reg[3]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.180     ; 7.100      ;
; 4.470 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer1|count_reg[4]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.180     ; 7.100      ;
; 4.470 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer1|count_reg[5]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.180     ; 7.100      ;
; 4.470 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer1|count_reg[6]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.180     ; 7.100      ;
; 4.470 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer1|count_reg[7]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.180     ; 7.100      ;
; 4.480 ; ram_do_reg[1]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[5]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.169     ; 7.101      ;
; 4.489 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|highpass1_reg                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.177     ; 7.084      ;
; 4.492 ; ram_do_reg[0]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[38]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.168     ; 7.090      ;
; 4.495 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[14]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 7.080      ;
; 4.497 ; ram_do_reg[1]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[41]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.167     ; 7.086      ;
; 4.499 ; ram_do_reg[0]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.180     ; 7.071      ;
; 4.508 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.149     ; 7.093      ;
; 4.508 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.149     ; 7.093      ;
+-------+----------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                               ;
+-------+-----------------------------------------------------------------------------------------------------------------+-------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                       ; To Node                                               ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------+-------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 0.387 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                           ; sdram_ctrl:sdram_controller|sdram_rdy                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.087      ; 0.669      ;
; 0.403 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                                      ; sdram_ctrl:sdram_controller|r_init_tmr[10]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[0]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; sdram_ctrl:sdram_controller|r_refr_act                                                                          ; sdram_ctrl:sdram_controller|r_refr_act                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.404 ; sdram_ctrl:sdram_controller|r_wr_act                                                                            ; sdram_ctrl:sdram_controller|r_wr_act                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_wr_bctr[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                                                                        ; sdram_ctrl:sdram_controller|r_bst_stp[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_rd_bctr[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; sdram_ctrl:sdram_controller|r_rd_act                                                                            ; sdram_ctrl:sdram_controller|r_rd_act                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; sdram_request_complete_reg                                                                                      ; sdram_request_complete_reg                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.419 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[0]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.684      ;
; 0.465 ; seq_reg[10]                                                                                                     ; seq_reg[11]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.087      ; 0.747      ;
; 0.482 ; sdram_ctrl:sdram_controller|r_rd_act                                                                            ; sdram_ctrl:sdram_controller|ap1_rd_bst_act            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.747      ;
; 0.484 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.750      ;
; 0.486 ; seq_reg[10]                                                                                                     ; sdram_ctrl:sdram_controller|sdram_rdy                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.087      ; 0.768      ;
; 0.501 ; seq_reg[11]                                                                                                     ; seq_reg[0]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.087      ; 0.783      ;
; 0.508 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.774      ;
; 0.529 ; sdram_ctrl:sdram_controller|r_rd_reg                                                                            ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.795      ;
; 0.627 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[19] ; ram_di_reg[3]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 1.008      ;
; 0.627 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[25] ; ram_di_reg[9]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 1.008      ;
; 0.628 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[21] ; ram_di_reg[5]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 1.009      ;
; 0.640 ; sdram_ctrl:sdram_controller|r_refr_act                                                                          ; sdram_ctrl:sdram_controller|r_wr_reg                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.906      ;
; 0.641 ; sdram_ctrl:sdram_controller|r_refr_act                                                                          ; sdram_ctrl:sdram_controller|r_rd_reg                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.907      ;
; 0.678 ; seq_reg[8]                                                                                                      ; seq_reg[9]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.087      ; 0.960      ;
; 0.685 ; seq_reg[5]                                                                                                      ; seq_reg[6]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.951      ;
; 0.686 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.951      ;
; 0.686 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.951      ;
; 0.687 ; seq_reg[9]                                                                                                      ; seq_reg[10]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.087      ; 0.969      ;
; 0.688 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.953      ;
; 0.689 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.954      ;
; 0.689 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.954      ;
; 0.691 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.956      ;
; 0.691 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                                                                        ; sdram_ctrl:sdram_controller|r_rd_bctr[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.956      ;
; 0.691 ; sdram_ctrl:sdram_controller|r_psel_dly[0]                                                                       ; sdram_ctrl:sdram_controller|ap1_rd_bst_act            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.956      ;
; 0.692 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.957      ;
; 0.692 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.957      ;
; 0.694 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_rd_act                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.959      ;
; 0.711 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.976      ;
; 0.711 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.976      ;
; 0.715 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_wr_act                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.980      ;
; 0.743 ; sdram_ctrl:sdram_controller|r_rd_reg                                                                            ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.009      ;
; 0.747 ; sdram_ctrl:sdram_controller|r_rd_act                                                                            ; sdram_ctrl:sdram_controller|r_rd_bctr[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.012      ;
; 0.786 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                                      ; sdram_ctrl:sdram_controller|r_init_fsm[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.052      ;
; 0.792 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[23] ; ram_di_reg[7]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 1.173      ;
; 0.792 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[26] ; ram_di_reg[10]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 1.173      ;
; 0.812 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[10]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.078      ;
; 0.830 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[0]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.096      ;
; 0.856 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                                      ; sdram_ctrl:sdram_controller|r_init_fsm[0]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.122      ;
; 0.858 ; seq_reg[6]                                                                                                      ; seq_reg[7]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.124      ;
; 0.860 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[18] ; ram_di_reg[2]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 1.241      ;
; 0.861 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[24] ; ram_di_reg[8]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 1.242      ;
; 0.868 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[16] ; ram_di_reg[0]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 1.249      ;
; 0.877 ; sdram_ctrl:sdram_controller|r_psel[0]                                                                           ; sdram_ctrl:sdram_controller|r_psel_dly[0]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.143      ;
; 0.878 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                                      ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.144      ;
; 0.890 ; seq_reg[2]                                                                                                      ; seq_reg[3]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.156      ;
; 0.894 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[20] ; ram_di_reg[4]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 1.275      ;
; 0.895 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[17] ; ram_di_reg[1]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 1.276      ;
; 0.910 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[22] ; ram_di_reg[6]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 1.291      ;
; 0.925 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[28] ; ram_di_reg[12]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 1.306      ;
; 0.938 ; sdram_ctrl:sdram_controller|r_wr_act                                                                            ; sdram_ctrl:sdram_controller|r_wr_bctr[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.203      ;
; 0.988 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[27] ; ram_di_reg[11]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 1.369      ;
; 1.007 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.272      ;
; 1.007 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.272      ;
; 1.008 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.273      ;
; 1.008 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.273      ;
; 1.009 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.274      ;
; 1.009 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.274      ;
; 1.010 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.275      ;
; 1.013 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.278      ;
; 1.013 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.278      ;
; 1.022 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.287      ;
; 1.022 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.287      ;
; 1.026 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.291      ;
; 1.026 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.291      ;
; 1.026 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.291      ;
; 1.062 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                                       ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.328      ;
; 1.074 ; seq_reg[1]                                                                                                      ; seq_reg[2]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.340      ;
; 1.085 ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1                                                           ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.351      ;
; 1.102 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.367      ;
; 1.106 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[29] ; ram_di_reg[13]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 1.487      ;
; 1.107 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.372      ;
; 1.107 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.372      ;
; 1.108 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[30] ; ram_di_reg[14]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 1.489      ;
; 1.115 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[12] ; ram_di_reg[12]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 1.496      ;
; 1.129 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.394      ;
; 1.129 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.394      ;
; 1.130 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.395      ;
; 1.131 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.396      ;
; 1.131 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.396      ;
; 1.135 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.400      ;
; 1.135 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.400      ;
; 1.144 ; sdram_request_reg                                                                                               ; sdram_ctrl:sdram_controller|r_psel[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -0.331     ; 1.008      ;
; 1.144 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.409      ;
; 1.144 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.409      ;
; 1.148 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.413      ;
; 1.148 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.413      ;
; 1.169 ; sdram_ctrl:sdram_controller|r_psel[0]                                                                           ; sdram_ctrl:sdram_controller|r_bst_stp[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.435      ;
; 1.177 ; ram_bena_reg[1]                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 1.439      ;
+-------+-----------------------------------------------------------------------------------------------------------------+-------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                           ;
+-------+--------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                        ; To Node                                                                                                                                          ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|skctl_reg[0]                                                                                ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|skctl_reg[0]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[5]                                                                                ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[5]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[4]                                                                                ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[4]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[6]                                                                                ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[6]                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serin_clock_reg                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serin_clock_reg                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_load2                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_load2                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_loadb2                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_loadb2                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[6]                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[6]                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[6]                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[6]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[7]                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[7]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[5]                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[5]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|use_status_as_ram_address      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|use_status_as_ram_address      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[12]                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[12]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[11]                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[11]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[7]                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[7]                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wsync_reg                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wsync_reg                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[8]                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[8]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[1]   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[1]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[2]   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[2]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[3]   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[3]   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_count_reg[1]                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_count_reg[1]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_count_reg[2]                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_count_reg[2]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_count_reg[3]                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_count_reg[3]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vblank_reg                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vblank_reg                                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[31]                                                                                                 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[31]                                                                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|bitcount_reg[2]                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|bitcount_reg[2]                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|bitcount_reg[3]                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|bitcount_reg[3]                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|idle_reg[1]                                                                                 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|idle_reg[1]                                                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|idle_reg[2]                                                                                 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|idle_reg[2]                                                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|idle_reg[3]                                                                                 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|idle_reg[3]                                                                                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|bitcount_reg[0]                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|bitcount_reg[0]                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|bitcount_reg[1]                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|bitcount_reg[1]                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[120]                                                                                                  ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[120]                                                                                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[1]                                                                                                    ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[1]                                                                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_ready_reg                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_ready_reg                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|first_line_of_instruction_reg                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|first_line_of_instruction_reg                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vscrol_last_enabled_reg                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vscrol_last_enabled_reg                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[30]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[30]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[29]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[29]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[84]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[84]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[27]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[27]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[78]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[78]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[74]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[74]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[34]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[34]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[82]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[82]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[273]                                                                                                  ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[273]                                                                                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[85]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[85]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[93]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[93]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[26]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[26]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[22]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[22]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[21]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[21]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[91]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[91]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[28]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[28]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[88]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[88]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[52]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[52]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[62]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[62]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[102]                                                                                                  ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[102]                                                                                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[66]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[66]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[6]                                                                                                    ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[6]                                                                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[90]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[90]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[67]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[67]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[50]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[50]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[46]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[46]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[118]                                                                                                  ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[118]                                                                                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[12]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[12]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[44]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[44]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[58]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[58]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[13]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[13]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[70]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[70]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[75]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[75]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[65]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[65]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[42]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[42]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[41]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[41]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[59]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[59]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[3]                                                                                                    ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[3]                                                                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[364]                                                                                                  ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[364]                                                                                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[43]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[43]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[37]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[37]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[68]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[68]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[45]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[45]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[51]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[51]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[60]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[60]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[5]                                                                                                    ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[5]                                                                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[76]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[76]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[77]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[77]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[36]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[36]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[49]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[49]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[73]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[73]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[53]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[53]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[54]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[54]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[4]                                                                                                    ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[4]                                                                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[38]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[38]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[33]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[33]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[61]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[61]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[69]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[69]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[35]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[35]                                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|state_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|state_reg[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|state_reg[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[2]                                                                                       ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[2]                                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[3]                                                                                       ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[3]                                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
+-------+--------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                          ;
+-------+---------------------------------------+----------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                                                        ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+----------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 5.816 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[14]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.568     ; 5.366      ;
; 5.847 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[8]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.564     ; 5.339      ;
; 5.847 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_8BIT_WRITE_ENABLE_reg    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.570     ; 5.333      ;
; 5.847 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_READ_reg                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.570     ; 5.333      ;
; 5.851 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[22]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.580     ; 5.319      ;
; 5.851 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[19]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.580     ; 5.319      ;
; 5.880 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.565     ; 5.305      ;
; 5.885 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[18]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.579     ; 5.286      ;
; 5.885 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[21]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.579     ; 5.286      ;
; 5.885 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[23]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.579     ; 5.286      ;
; 5.885 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[20]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.579     ; 5.286      ;
; 5.885 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[16]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.579     ; 5.286      ;
; 5.885 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[17]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.579     ; 5.286      ;
; 5.887 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[8]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.542     ; 5.321      ;
; 5.937 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[14]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.543     ; 5.270      ;
; 5.937 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[15]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.543     ; 5.270      ;
; 6.300 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[1]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.565     ; 4.885      ;
; 6.300 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[4]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.565     ; 4.885      ;
; 6.300 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[5]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.565     ; 4.885      ;
; 6.300 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[12]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.568     ; 4.882      ;
; 6.300 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[3]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.577     ; 4.873      ;
; 6.300 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[6]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.577     ; 4.873      ;
; 6.300 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[1]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.576     ; 4.874      ;
; 6.300 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[7]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.577     ; 4.873      ;
; 6.301 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[17]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.580     ; 4.869      ;
; 6.301 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[13]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.568     ; 4.881      ;
; 6.301 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[10]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.569     ; 4.880      ;
; 6.301 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[8]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.567     ; 4.882      ;
; 6.301 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[12]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.567     ; 4.882      ;
; 6.301 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[10]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.567     ; 4.882      ;
; 6.301 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[11]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.567     ; 4.882      ;
; 6.301 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[11]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.569     ; 4.880      ;
; 6.301 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[13]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.567     ; 4.882      ;
; 6.301 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[14]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.567     ; 4.882      ;
; 6.301 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[9]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.567     ; 4.882      ;
; 6.301 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[15]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.567     ; 4.882      ;
; 6.301 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.580     ; 4.869      ;
; 6.303 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[11]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.566     ; 4.881      ;
; 6.303 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.566     ; 4.881      ;
; 6.303 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.566     ; 4.881      ;
; 6.303 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[25]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.564     ; 4.883      ;
; 6.303 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.566     ; 4.881      ;
; 6.305 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|memory_ready_reg             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.574     ; 4.871      ;
; 6.310 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[5]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.571     ; 4.869      ;
; 6.310 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[4]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.571     ; 4.869      ;
; 6.311 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[4]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.571     ; 4.868      ;
; 6.311 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[5]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.561     ; 4.878      ;
; 6.311 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[16]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.559     ; 4.880      ;
; 6.311 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[21]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.559     ; 4.880      ;
; 6.311 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[31]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.571     ; 4.868      ;
; 6.311 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[22]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.559     ; 4.880      ;
; 6.311 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[25]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.559     ; 4.880      ;
; 6.311 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[22]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.575     ; 4.864      ;
; 6.311 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[22]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.556     ; 4.883      ;
; 6.311 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[22]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.556     ; 4.883      ;
; 6.311 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[22]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.570     ; 4.869      ;
; 6.311 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[8]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.556     ; 4.883      ;
; 6.311 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[8]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.556     ; 4.883      ;
; 6.311 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[8]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.559     ; 4.880      ;
; 6.311 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[2]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.561     ; 4.878      ;
; 6.311 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[27]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.556     ; 4.883      ;
; 6.311 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[27]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.556     ; 4.883      ;
; 6.311 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[27]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.559     ; 4.880      ;
; 6.311 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[18]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.556     ; 4.883      ;
; 6.311 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[18]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.559     ; 4.880      ;
; 6.311 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[10]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.556     ; 4.883      ;
; 6.311 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[0]    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.556     ; 4.883      ;
; 6.311 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[16]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.561     ; 4.878      ;
; 6.311 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[16]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.575     ; 4.864      ;
; 6.311 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[24]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.559     ; 4.880      ;
; 6.311 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[26]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.559     ; 4.880      ;
; 6.311 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[0]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.556     ; 4.883      ;
; 6.311 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[0]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.560     ; 4.879      ;
; 6.311 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[3]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.560     ; 4.879      ;
; 6.311 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[23]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.559     ; 4.880      ;
; 6.311 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[23]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.556     ; 4.883      ;
; 6.311 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[23]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.556     ; 4.883      ;
; 6.311 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[2]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.570     ; 4.869      ;
; 6.311 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[30]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.559     ; 4.880      ;
; 6.311 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[30]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.556     ; 4.883      ;
; 6.311 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[1]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.560     ; 4.879      ;
; 6.311 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[9]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.556     ; 4.883      ;
; 6.311 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[9]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.556     ; 4.883      ;
; 6.311 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[9]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.556     ; 4.883      ;
; 6.311 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[2]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.560     ; 4.879      ;
; 6.311 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[15]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.575     ; 4.864      ;
; 6.311 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[19]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.556     ; 4.883      ;
; 6.311 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[19]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.556     ; 4.883      ;
; 6.311 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[19]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.556     ; 4.883      ;
; 6.311 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[19]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.559     ; 4.880      ;
; 6.311 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[20]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.559     ; 4.880      ;
; 6.311 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[20]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.573     ; 4.866      ;
; 6.311 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[20]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.556     ; 4.883      ;
; 6.311 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[20]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.556     ; 4.883      ;
; 6.312 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[17]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.571     ; 4.867      ;
; 6.312 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[22]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.571     ; 4.867      ;
; 6.312 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[18]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.571     ; 4.867      ;
; 6.312 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[21]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.571     ; 4.867      ;
; 6.312 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[20]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.571     ; 4.867      ;
; 6.312 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[19]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.571     ; 4.867      ;
+-------+---------------------------------------+----------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                      ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                                   ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 8.123 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[3]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.362     ; 3.127      ;
; 8.127 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[0]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.358     ; 3.127      ;
; 8.127 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[1]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.358     ; 3.127      ;
; 8.127 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[6]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.359     ; 3.126      ;
; 8.127 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[7]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.358     ; 3.127      ;
; 8.127 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[2]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.358     ; 3.127      ;
; 8.128 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[5]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.363     ; 3.121      ;
; 8.129 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[4]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.365     ; 3.118      ;
; 8.134 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 3.300      ;
; 8.134 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[0]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.191     ; 3.298      ;
; 8.134 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[1]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.191     ; 3.298      ;
; 8.134 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[2]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.191     ; 3.298      ;
; 8.134 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[3]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.191     ; 3.298      ;
; 8.134 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.191     ; 3.298      ;
; 8.134 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.191     ; 3.298      ;
; 8.145 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[15]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.351     ; 3.116      ;
; 8.145 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[13]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.351     ; 3.116      ;
; 8.145 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[10]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.352     ; 3.115      ;
; 8.145 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[12]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.352     ; 3.115      ;
; 8.145 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[14]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.351     ; 3.116      ;
; 8.145 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[11]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.352     ; 3.115      ;
; 8.145 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[3]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.242     ; 3.236      ;
; 8.149 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[9]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.352     ; 3.111      ;
; 8.149 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[8]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.346     ; 3.117      ;
; 8.149 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[0]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.238     ; 3.236      ;
; 8.149 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[1]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.238     ; 3.236      ;
; 8.149 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[2]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.238     ; 3.236      ;
; 8.149 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[6]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.239     ; 3.235      ;
; 8.149 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[7]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.238     ; 3.236      ;
; 8.150 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[5]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.243     ; 3.230      ;
; 8.151 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[4]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.245     ; 3.227      ;
; 8.158 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[4]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.177     ; 3.288      ;
; 8.158 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[5]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.179     ; 3.286      ;
; 8.159 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[6]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.179     ; 3.285      ;
; 8.159 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[7]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.179     ; 3.285      ;
; 8.159 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[8]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 3.286      ;
; 8.159 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 3.286      ;
; 8.167 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[10]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.232     ; 3.224      ;
; 8.167 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[11]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.232     ; 3.224      ;
; 8.167 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[12]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.232     ; 3.224      ;
; 8.167 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[13]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.231     ; 3.225      ;
; 8.167 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[14]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.231     ; 3.225      ;
; 8.167 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[15]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.231     ; 3.225      ;
; 8.171 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[8]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.226     ; 3.226      ;
; 8.171 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[9]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.232     ; 3.220      ;
; 8.366 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 3.068      ;
; 8.366 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 3.068      ;
; 8.366 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 3.068      ;
; 8.366 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 3.068      ;
; 8.681 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 2.879      ;
; 8.681 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.181     ; 2.887      ;
; 8.681 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.181     ; 2.887      ;
; 8.681 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.181     ; 2.887      ;
; 8.681 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 2.879      ;
; 8.681 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 2.879      ;
; 8.681 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 2.879      ;
; 8.681 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 2.879      ;
; 8.681 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 2.879      ;
; 8.681 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.190     ; 2.878      ;
; 8.681 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.180     ; 2.888      ;
; 8.681 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.181     ; 2.887      ;
; 8.681 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.181     ; 2.887      ;
; 8.681 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.181     ; 2.887      ;
; 8.681 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.190     ; 2.878      ;
; 8.682 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 2.885      ;
; 8.682 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 2.885      ;
; 8.682 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 2.885      ;
; 8.682 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 2.885      ;
; 8.682 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 2.885      ;
; 8.682 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 2.885      ;
; 8.682 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 2.885      ;
; 8.682 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 2.885      ;
; 8.682 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 2.885      ;
; 8.682 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 2.885      ;
; 8.682 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 2.885      ;
; 8.682 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.181     ; 2.886      ;
; 8.682 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.181     ; 2.886      ;
; 8.682 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.181     ; 2.886      ;
; 8.682 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.181     ; 2.886      ;
; 8.682 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 2.885      ;
; 8.682 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 2.885      ;
; 8.682 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 2.885      ;
; 8.682 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 2.885      ;
; 8.682 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 2.885      ;
; 8.682 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 2.885      ;
; 8.682 ; sdram_reset_ctrl_n_reg ; ram_di_reg[6]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 2.885      ;
; 8.682 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 2.885      ;
; 8.682 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 2.885      ;
; 8.682 ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 2.885      ;
; 8.682 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 2.885      ;
; 8.682 ; sdram_reset_ctrl_n_reg ; ram_di_reg[11]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 2.885      ;
; 8.682 ; sdram_reset_ctrl_n_reg ; ram_di_reg[12]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 2.885      ;
; 8.682 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 2.885      ;
; 8.682 ; sdram_reset_ctrl_n_reg ; ram_di_reg[14]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 2.885      ;
; 8.682 ; sdram_reset_ctrl_n_reg ; ram_di_reg[15]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 2.885      ;
; 8.682 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.183     ; 2.884      ;
; 8.683 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.180     ; 2.886      ;
; 8.683 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.180     ; 2.886      ;
; 8.683 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.180     ; 2.886      ;
; 8.683 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.180     ; 2.886      ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                       ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                                   ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 1.923 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.563      ; 2.700      ;
; 1.923 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.563      ; 2.700      ;
; 1.923 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.563      ; 2.700      ;
; 1.923 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.563      ; 2.700      ;
; 1.923 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.563      ; 2.700      ;
; 1.923 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.563      ; 2.700      ;
; 1.923 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.563      ; 2.700      ;
; 2.336 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 2.708      ;
; 2.336 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 2.708      ;
; 2.336 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 2.708      ;
; 2.336 ; sdram_reset_ctrl_n_reg ; seq_reg[5]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 2.708      ;
; 2.336 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 2.708      ;
; 2.336 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 2.708      ;
; 2.336 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.706      ;
; 2.336 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.706      ;
; 2.336 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.706      ;
; 2.336 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.706      ;
; 2.336 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.706      ;
; 2.336 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.706      ;
; 2.336 ; sdram_reset_ctrl_n_reg ; ram_do_reg[25]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.706      ;
; 2.336 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.706      ;
; 2.336 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.706      ;
; 2.336 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.706      ;
; 2.336 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.706      ;
; 2.336 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.706      ;
; 2.336 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.706      ;
; 2.336 ; sdram_reset_ctrl_n_reg ; ram_do_reg[5]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.706      ;
; 2.336 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.706      ;
; 2.336 ; sdram_reset_ctrl_n_reg ; ram_do_reg[8]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.706      ;
; 2.336 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.706      ;
; 2.336 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.706      ;
; 2.336 ; sdram_reset_ctrl_n_reg ; ram_do_reg[12]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.706      ;
; 2.336 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.706      ;
; 2.336 ; sdram_reset_ctrl_n_reg ; ram_do_reg[11]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.706      ;
; 2.336 ; sdram_reset_ctrl_n_reg ; ram_do_reg[13]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.706      ;
; 2.336 ; sdram_reset_ctrl_n_reg ; ram_do_reg[14]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.706      ;
; 2.336 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.706      ;
; 2.336 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.706      ;
; 2.336 ; sdram_reset_ctrl_n_reg ; ram_do_reg[9]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.706      ;
; 2.336 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.706      ;
; 2.336 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.706      ;
; 2.336 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.706      ;
; 2.336 ; sdram_reset_ctrl_n_reg ; ram_do_reg[15]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.706      ;
; 2.336 ; sdram_reset_ctrl_n_reg ; ram_do_reg[19]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.706      ;
; 2.336 ; sdram_reset_ctrl_n_reg ; ram_do_reg[20]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.706      ;
; 2.336 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[0]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 2.709      ;
; 2.336 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[1]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 2.709      ;
; 2.338 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 2.707      ;
; 2.338 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 2.707      ;
; 2.338 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 2.707      ;
; 2.338 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 2.707      ;
; 2.338 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.705      ;
; 2.338 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.705      ;
; 2.338 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.705      ;
; 2.338 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 2.708      ;
; 2.338 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.705      ;
; 2.339 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.706      ;
; 2.339 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 2.708      ;
; 2.339 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 2.708      ;
; 2.339 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 2.708      ;
; 2.339 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.706      ;
; 2.339 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.706      ;
; 2.339 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.706      ;
; 2.339 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.706      ;
; 2.339 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 2.708      ;
; 2.339 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 2.708      ;
; 2.339 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 2.708      ;
; 2.340 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.707      ;
; 2.340 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.707      ;
; 2.340 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.707      ;
; 2.340 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.707      ;
; 2.340 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.707      ;
; 2.340 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.707      ;
; 2.340 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.707      ;
; 2.340 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.707      ;
; 2.340 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.707      ;
; 2.340 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.707      ;
; 2.340 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.707      ;
; 2.340 ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.707      ;
; 2.340 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.707      ;
; 2.340 ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.707      ;
; 2.340 ; sdram_reset_ctrl_n_reg ; ram_di_reg[6]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.707      ;
; 2.340 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.707      ;
; 2.340 ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.707      ;
; 2.340 ; sdram_reset_ctrl_n_reg ; ram_di_reg[11]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.707      ;
; 2.340 ; sdram_reset_ctrl_n_reg ; ram_di_reg[12]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.707      ;
; 2.340 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.707      ;
; 2.340 ; sdram_reset_ctrl_n_reg ; ram_di_reg[14]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.707      ;
; 2.340 ; sdram_reset_ctrl_n_reg ; ram_di_reg[15]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 2.707      ;
; 2.341 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 2.701      ;
; 2.341 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 2.701      ;
; 2.341 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 2.701      ;
; 2.341 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 2.701      ;
; 2.341 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 2.701      ;
; 2.341 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 2.701      ;
; 2.341 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.145      ; 2.700      ;
; 2.341 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.145      ; 2.700      ;
; 2.573 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.152      ; 2.856      ;
; 2.573 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.152      ; 2.856      ;
; 2.574 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.152      ; 2.857      ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                ;
+-------+-------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node         ; To Node                                                                                                                                                 ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 3.282 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[0]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.590      ; 4.067      ;
; 3.282 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[4]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.590      ; 4.067      ;
; 3.303 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[4]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.564      ; 4.062      ;
; 3.744 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|bincnt_reg[0]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 4.043      ;
; 3.744 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|bincnt_reg[1]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 4.043      ;
; 3.744 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|bincnt_reg[2]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 4.043      ;
; 3.744 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|bincnt_reg[3]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 4.043      ;
; 3.744 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|bincnt_reg[4]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 4.043      ;
; 3.744 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|bincnt_reg[5]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 4.043      ;
; 3.744 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|control_pressed_reg ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.102      ; 4.041      ;
; 3.744 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|break_pressed_reg   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.103      ; 4.042      ;
; 3.744 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|shift_pressed_reg   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.103      ; 4.042      ;
; 3.744 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[4][3]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.096      ; 4.035      ;
; 3.744 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[3][3]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.096      ; 4.035      ;
; 3.744 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[2][3]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.096      ; 4.035      ;
; 3.744 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[1][3]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.096      ; 4.035      ;
; 3.744 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[0][3]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 4.034      ;
; 3.744 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[4][2]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 4.034      ;
; 3.744 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[3][2]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 4.034      ;
; 3.744 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[2][2]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 4.034      ;
; 3.744 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[1][2]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 4.034      ;
; 3.744 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[0][2]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 4.034      ;
; 3.744 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp0_delay|shift_reg[2][5]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 4.034      ;
; 3.744 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|sizem_raw_reg[7]                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.096      ; 4.035      ;
; 3.744 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|shift_reg[3][7]                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.096      ; 4.035      ;
; 3.744 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|shift_reg[2][7]                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.096      ; 4.035      ;
; 3.744 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|sizem_raw_reg[6]                                                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.096      ; 4.035      ;
; 3.744 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|shift_reg[3][6]                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.096      ; 4.035      ;
; 3.744 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|shift_reg[2][6]                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.096      ; 4.035      ;
; 3.744 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm1_delay|shift_reg[4][7]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 4.034      ;
; 3.744 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm1_delay|shift_reg[2][2]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 4.034      ;
; 3.744 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm1_delay|shift_reg[1][2]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 4.034      ;
; 3.744 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm1_delay|shift_reg[0][2]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 4.034      ;
; 3.744 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm1_delay|shift_reg[1][3]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 4.034      ;
; 3.744 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm1_delay|shift_reg[0][3]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 4.034      ;
; 3.744 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_raw_reg[3]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.096      ; 4.035      ;
; 3.744 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[4][3]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.096      ; 4.035      ;
; 3.744 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[3][3]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.096      ; 4.035      ;
; 3.744 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[2][3]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.096      ; 4.035      ;
; 3.744 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[1][3]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 4.034      ;
; 3.744 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[0][3]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 4.034      ;
; 3.744 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_raw_reg[2]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.096      ; 4.035      ;
; 3.744 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[4][2]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.096      ; 4.035      ;
; 3.744 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[3][2]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.096      ; 4.035      ;
; 3.744 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[2][2]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.096      ; 4.035      ;
; 3.744 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[1][2]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 4.034      ;
; 3.744 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[0][2]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 4.034      ;
; 3.744 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_raw_reg[4]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.096      ; 4.035      ;
; 3.744 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[4][4]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.096      ; 4.035      ;
; 3.744 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[3][4]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.096      ; 4.035      ;
; 3.744 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[2][4]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.096      ; 4.035      ;
; 3.744 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[1][4]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.096      ; 4.035      ;
; 3.744 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[0][4]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 4.034      ;
; 3.746 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[3]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 4.027      ;
; 3.746 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[2]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 4.027      ;
; 3.746 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[1]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.088      ; 4.029      ;
; 3.746 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[4][1]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.090      ; 4.031      ;
; 3.746 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[3][1]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.090      ; 4.031      ;
; 3.746 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[1][1]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.090      ; 4.031      ;
; 3.746 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[0][1]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.090      ; 4.031      ;
; 3.746 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[0]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.092      ; 4.033      ;
; 3.746 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[4][0]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.092      ; 4.033      ;
; 3.746 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[3][0]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.092      ; 4.033      ;
; 3.746 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[2][0]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.092      ; 4.033      ;
; 3.746 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[1][0]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.092      ; 4.033      ;
; 3.746 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[0][0]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.092      ; 4.033      ;
; 3.746 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[6]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 4.027      ;
; 3.746 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[4][6]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.085      ; 4.026      ;
; 3.746 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[3][6]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.085      ; 4.026      ;
; 3.746 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[2][6]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.085      ; 4.026      ;
; 3.746 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[1][6]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.085      ; 4.026      ;
; 3.746 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[0][6]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.085      ; 4.026      ;
; 3.746 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[7]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.092      ; 4.033      ;
; 3.746 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[4][7]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.092      ; 4.033      ;
; 3.746 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[3][7]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.092      ; 4.033      ;
; 3.746 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[2][7]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.092      ; 4.033      ;
; 3.746 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[1][7]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.092      ; 4.033      ;
; 3.746 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[0][7]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.092      ; 4.033      ;
; 3.746 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[4]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.092      ; 4.033      ;
; 3.746 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[4][4]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.092      ; 4.033      ;
; 3.746 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[3][4]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.092      ; 4.033      ;
; 3.746 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[2][4]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.092      ; 4.033      ;
; 3.746 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[1][4]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.092      ; 4.033      ;
; 3.746 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[0][4]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.092      ; 4.033      ;
; 3.746 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[5]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 4.027      ;
; 3.746 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[4][5]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.085      ; 4.026      ;
; 3.746 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[3][5]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.085      ; 4.026      ;
; 3.746 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[2][5]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.085      ; 4.026      ;
; 3.746 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[1][5]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.085      ; 4.026      ;
; 3.746 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[0][5]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.085      ; 4.026      ;
; 3.746 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_raw_reg[7]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.093      ; 4.034      ;
; 3.746 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_raw_reg[6]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.091      ; 4.032      ;
; 3.746 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_raw_reg[3]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.091      ; 4.032      ;
; 3.746 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_raw_reg[0]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.093      ; 4.034      ;
; 3.746 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_raw_reg[4]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.091      ; 4.032      ;
; 3.746 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_raw_reg[5]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.091      ; 4.032      ;
; 3.746 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_raw_reg[1]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.088      ; 4.029      ;
; 3.746 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[4][1]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.092      ; 4.033      ;
; 3.746 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_raw_reg[0]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.088      ; 4.029      ;
; 3.746 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_raw_reg[5]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.088      ; 4.029      ;
+-------+-------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                         ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                         ; Clock Edge ; Target                                                    ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; 5.532 ; 5.748        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|sdram_rdy                     ;
; 5.532 ; 5.748        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_reg                                         ;
; 5.532 ; 5.748        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[0]                                                ;
; 5.532 ; 5.748        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[10]                                               ;
; 5.532 ; 5.748        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[11]                                               ;
; 5.532 ; 5.748        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[8]                                                ;
; 5.532 ; 5.748        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[9]                                                ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[3]                                             ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[4]                                             ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[5]                                             ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[0]                                             ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[11]                                            ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[14]                                            ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[15]                                            ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[16]                                            ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[19]                                            ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[22]                                            ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[23]                                            ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[24]                                            ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[27]                                            ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[30]                                            ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[31]                                            ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[3]                                             ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[6]                                             ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[7]                                             ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[8]                                             ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel[0]                     ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_act                      ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_reg                      ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_act                    ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_req                    ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_reg                      ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[1]                                                ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[2]                                                ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[3]                                                ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[5]                                                ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[6]                                                ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[7]                                                ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[0]                                           ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[1]                                           ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[0]                                             ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[10]                                            ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[11]                                            ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[12]                                            ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[13]                                            ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[14]                                            ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[15]                                            ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[1]                                             ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[2]                                             ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[6]                                             ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[7]                                             ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[8]                                             ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[9]                                             ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[10]                                            ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[12]                                            ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[13]                                            ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[17]                                            ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[18]                                            ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[1]                                             ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[20]                                            ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[21]                                            ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[25]                                            ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[26]                                            ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[28]                                            ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[29]                                            ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[2]                                             ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[4]                                             ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[5]                                             ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[9]                                             ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_act                      ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_complete_reg                                ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[4]                                                ;
; 5.677 ; 5.832        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[3]                   ;
; 5.678 ; 5.833        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[5]                   ;
; 5.679 ; 5.834        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[0]                   ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                 ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                         ; Clock Edge ; Target                                                                                                                           ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------+
; 17.272 ; 17.488       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                                                               ;
; 17.273 ; 17.489       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[4]                             ;
; 17.273 ; 17.489       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[0]                                                                                ;
; 17.281 ; 17.497       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[0]                         ;
; 17.281 ; 17.497       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[4]                         ;
; 17.281 ; 17.497       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|addr_r[4]                                                                  ;
; 17.281 ; 17.497       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[3]                                                                                ;
; 17.284 ; 17.500       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|addr_r[3]                                                                  ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|cfg_bank[13]     ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|cfg_bank[19]     ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[2]                   ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[3]                   ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|ram_bank[13]   ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|ram_bank[14]   ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|ram_bank[15]   ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|rom_bank[13]   ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|rom_bank[14]   ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|rom_bank[15]   ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|cpu_fetch_real_reg                  ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg                      ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|write_enable_reg                    ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[2]                           ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[3]                           ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[4]                           ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|pmbase_reg[2]                               ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|pmbase_reg[3]                               ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|pmbase_reg[4]                               ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:nmien_delay|shift_reg[1][0] ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|covox:covox1|channel0_reg[0]                             ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|covox:covox1|channel0_reg[1]                             ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|covox:covox1|channel0_reg[2]                             ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|covox:covox1|channel0_reg[3]                             ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|covox:covox1|channel0_reg[4]                             ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|covox:covox1|channel0_reg[5]                             ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|covox:covox1|channel0_reg[6]                             ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|covox:covox1|channel0_reg[7]                             ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|covox:covox1|channel1_reg[0]                             ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|covox:covox1|channel1_reg[1]                             ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|covox:covox1|channel1_reg[2]                             ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|covox:covox1|channel1_reg[3]                             ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|covox:covox1|channel1_reg[4]                             ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|covox:covox1|channel1_reg[5]                             ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|covox:covox1|channel1_reg[6]                             ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|covox:covox1|channel1_reg[7]                             ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|covox:covox1|channel2_reg[0]                             ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|covox:covox1|channel2_reg[1]                             ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|covox:covox1|channel2_reg[2]                             ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|covox:covox1|channel2_reg[3]                             ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|covox:covox1|channel2_reg[4]                             ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|covox:covox1|channel2_reg[5]                             ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|covox:covox1|channel2_reg[6]                             ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|covox:covox1|channel2_reg[7]                             ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|covox:covox1|channel3_reg[0]                             ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|covox:covox1|channel3_reg[1]                             ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|covox:covox1|channel3_reg[2]                             ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|covox:covox1|channel3_reg[3]                             ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|covox:covox1|channel3_reg[4]                             ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|covox:covox1|channel3_reg[5]                             ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|covox:covox1|channel3_reg[6]                             ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|covox:covox1|channel3_reg[7]                             ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gractl_reg[2]                                 ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_raw_reg[0]                             ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_raw_reg[1]                             ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_raw_reg[0]                             ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_raw_reg[1]                             ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pl_reg[1]                                   ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pl_reg[2]                                   ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pl_reg[1]                                   ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pl_reg[1]                                   ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pl_reg[2]                                   ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pf_reg[0]                                   ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p2pf_reg[0]                                   ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|sizep2_raw_reg[0]                             ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|sizep2_raw_reg[1]                             ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[0]                                   ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[1]                                   ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[3]                                   ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[0][0]  ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[0][1]  ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[1][1]  ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[2][1]  ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm3_delay|shift_reg[0][0]  ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm3_delay|shift_reg[0][1]  ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm3_delay|shift_reg[1][0]  ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm3_delay|shift_reg[1][1]  ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm3_delay|shift_reg[2][0]  ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm3_delay|shift_reg[2][1]  ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm3_delay|shift_reg[3][0]  ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm3_delay|shift_reg[3][1]  ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm3_delay|shift_reg[4][0]  ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm3_delay|shift_reg[4][1]  ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[0][0]  ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[0][1]  ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[1][0]  ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[1][1]  ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[2][0]  ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[2][1]  ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[3][0]  ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[3][1]  ;
; 17.319 ; 17.535       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[4][0]  ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                   ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                        ; Clock Edge ; Target                                                                                             ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------+
; 17.587 ; 17.587       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.587 ; 17.587       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.587 ; 17.587       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.587 ; 17.587       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 17.589 ; 17.589       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.589 ; 17.589       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.598 ; 17.598       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.643 ; 17.643       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.652 ; 17.652       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.652 ; 17.652       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.654 ; 17.654       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.654 ; 17.654       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.654 ; 17.654       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.654 ; 17.654       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'                                                                                                                        ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------+
; Slack   ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                                                 ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------+
; 99.837  ; 99.837       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 99.837  ; 99.837       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 99.888  ; 99.888       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                       ;
; 99.920  ; 99.920       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 100.000 ; 100.000      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                       ;
; 100.000 ; 100.000      ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                       ;
; 100.079 ; 100.079      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 100.112 ; 100.112      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                       ;
; 100.162 ; 100.162      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 100.162 ; 100.162      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 196.000 ; 200.000      ; 4.000          ; Port Rate        ; FPGA_CLK ; Rise       ; FPGA_CLK                                                                               ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                             ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.654 ; 2.761 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.634 ; 2.741 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.634 ; 2.741 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.634 ; 2.741 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.648 ; 2.755 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.651 ; 2.758 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.649 ; 2.756 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.645 ; 2.752 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.654 ; 2.761 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.642 ; 2.749 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.648 ; 2.755 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.648 ; 2.755 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.648 ; 2.755 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.638 ; 2.745 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.637 ; 2.744 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.627 ; 2.734 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.637 ; 2.744 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; 5.177 ; 5.639 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; 4.186 ; 4.568 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; 3.598 ; 3.927 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; 3.368 ; 3.654 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; 3.651 ; 3.942 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; 5.177 ; 5.639 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; 5.694 ; 6.237 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; 3.691 ; 3.958 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; 4.036 ; 4.333 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; 4.005 ; 4.338 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; 3.910 ; 4.328 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; 5.694 ; 6.237 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; 5.916 ; 6.027 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; 4.923 ; 5.151 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; 3.732 ; 4.081 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; -1.742 ; -1.850 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; -1.749 ; -1.857 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; -1.749 ; -1.857 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; -1.749 ; -1.857 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; -1.763 ; -1.871 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; -1.767 ; -1.875 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; -1.765 ; -1.873 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; -1.761 ; -1.869 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; -1.769 ; -1.877 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; -1.757 ; -1.865 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; -1.763 ; -1.871 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; -1.763 ; -1.871 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; -1.763 ; -1.871 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; -1.753 ; -1.861 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; -1.752 ; -1.860 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; -1.742 ; -1.850 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; -1.752 ; -1.860 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; -2.422 ; -2.691 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; -3.170 ; -3.516 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; -2.563 ; -2.864 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; -2.422 ; -2.691 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; -2.635 ; -2.888 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; -2.656 ; -2.900 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; -2.730 ; -2.981 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; -2.730 ; -2.981 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; -3.060 ; -3.342 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; -2.999 ; -3.297 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; -2.942 ; -3.339 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; -2.868 ; -3.209 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; -4.859 ; -4.961 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; -3.911 ; -4.122 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; -2.770 ; -3.100 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                       ;
+-----------------+------------+--------+--------+------------+-------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                               ;
+-----------------+------------+--------+--------+------------+-------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 4.590  ; 4.140  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 3.323  ; 3.087  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 3.313  ; 3.077  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 3.313  ; 3.077  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 3.313  ; 3.077  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 3.317  ; 3.081  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 3.326  ; 3.090  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 3.335  ; 3.099  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 4.590  ; 4.140  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 3.336  ; 3.100  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 3.346  ; 3.110  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 3.323  ; 3.087  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 4.578  ; 4.128  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 3.325  ; 3.089  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 4.578  ; 4.128  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 4.590  ; 4.140  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 3.335  ; 3.099  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 4.657  ; 4.209  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 3.607  ; 3.350  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 3.607  ; 3.350  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 3.607  ; 3.350  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 4.637  ; 4.189  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 4.633  ; 4.185  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 2.563  ; 2.365  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 3.507  ; 3.264  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 3.519  ; 3.276  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 3.639  ; 3.382  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 4.657  ; 4.209  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 3.633  ; 3.376  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 3.633  ; 3.376  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 3.623  ; 3.366  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 4.648  ; 4.200  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 3.614  ; 3.357  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 3.624  ; 3.367  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 3.648  ; 3.993  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 3.648  ; 3.993  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 3.012  ; 3.302  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 3.335  ; 3.099  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 3.345  ; 3.109  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 7.899  ; 7.884  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 3.123  ; 3.087  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 4.544  ; 4.226  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 6.978  ; 7.102  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 3.526  ; 3.802  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]        ; FPGA_CLK   ; 11.918 ; 11.726 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]       ; FPGA_CLK   ; 9.919  ; 9.637  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]       ; FPGA_CLK   ; 11.918 ; 11.726 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]       ; FPGA_CLK   ; 9.323  ; 8.831  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]       ; FPGA_CLK   ; 10.915 ; 11.290 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]        ; FPGA_CLK   ; 11.255 ; 11.356 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]       ; FPGA_CLK   ; 11.255 ; 11.356 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]       ; FPGA_CLK   ; 9.115  ; 8.772  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]       ; FPGA_CLK   ; 8.526  ; 8.152  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]       ; FPGA_CLK   ; 7.747  ; 7.259  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS          ; FPGA_CLK   ; 9.177  ; 9.205  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]        ; FPGA_CLK   ; 9.725  ; 9.233  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]       ; FPGA_CLK   ; 8.784  ; 8.394  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]       ; FPGA_CLK   ; 9.725  ; 9.233  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]       ; FPGA_CLK   ; 8.842  ; 8.364  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]       ; FPGA_CLK   ; 8.668  ; 8.274  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS          ; FPGA_CLK   ; 2.486  ; 2.369  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 9.375  ;        ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;        ; 9.104  ; Fall       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+-----------------+------------+--------+--------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                             ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 2.555 ; 2.323 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 2.565 ; 2.333 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 2.555 ; 2.323 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 2.555 ; 2.323 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 2.555 ; 2.323 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 2.559 ; 2.327 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 2.567 ; 2.335 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 2.577 ; 2.345 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 3.871 ; 3.422 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 2.578 ; 2.346 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 2.588 ; 2.356 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 2.565 ; 2.333 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 2.567 ; 2.335 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 2.567 ; 2.335 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 3.859 ; 3.410 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 3.871 ; 3.422 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 2.577 ; 2.345 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 1.847 ; 1.650 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 2.848 ; 2.595 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 2.848 ; 2.595 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 2.848 ; 2.595 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 3.920 ; 3.473 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 3.917 ; 3.470 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 1.847 ; 1.650 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 2.749 ; 2.510 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 2.760 ; 2.521 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 2.880 ; 2.627 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 3.940 ; 3.493 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 2.874 ; 2.621 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 2.874 ; 2.621 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 2.864 ; 2.611 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 3.931 ; 3.484 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 2.855 ; 2.602 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 2.865 ; 2.612 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 2.267 ; 2.551 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 2.877 ; 3.215 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 2.267 ; 2.551 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 2.577 ; 2.345 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 2.587 ; 2.355 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 7.087 ; 7.087 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 2.399 ; 2.363 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 3.750 ; 3.440 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 6.196 ; 6.328 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 2.769 ; 3.037 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]        ; FPGA_CLK   ; 5.046 ; 4.744 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]       ; FPGA_CLK   ; 5.228 ; 4.926 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]       ; FPGA_CLK   ; 7.591 ; 7.683 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]       ; FPGA_CLK   ; 5.046 ; 4.744 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]       ; FPGA_CLK   ; 7.818 ; 7.742 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]        ; FPGA_CLK   ; 4.630 ; 4.329 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]       ; FPGA_CLK   ; 7.378 ; 7.489 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]       ; FPGA_CLK   ; 4.630 ; 4.329 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]       ; FPGA_CLK   ; 4.772 ; 4.491 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]       ; FPGA_CLK   ; 4.934 ; 4.349 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS          ; FPGA_CLK   ; 6.946 ; 6.943 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]        ; FPGA_CLK   ; 4.826 ; 4.382 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]       ; FPGA_CLK   ; 5.056 ; 4.661 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]       ; FPGA_CLK   ; 4.826 ; 4.382 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]       ; FPGA_CLK   ; 5.370 ; 4.992 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]       ; FPGA_CLK   ; 5.268 ; 4.923 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS          ; FPGA_CLK   ; 1.766 ; 1.650 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 8.697 ;       ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 8.431 ; Fall       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.980 ; 2.980 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.985 ; 2.985 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.985 ; 2.985 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.985 ; 2.985 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.398 ; 3.398 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.791 ; 3.791 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.825 ; 3.825 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.950 ; 3.950 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 4.077 ; 4.077 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.722 ; 3.722 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.376 ; 3.376 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.022 ; 3.022 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.022 ; 3.022 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.012 ; 3.012 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.990 ; 2.990 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.980 ; 2.980 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.990 ; 2.990 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 4.935 ; 4.559 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                             ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.934 ; 1.934 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.939 ; 1.939 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.939 ; 1.939 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.939 ; 1.939 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.337 ; 2.337 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.713 ; 2.713 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.746 ; 2.746 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.866 ; 2.866 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.988 ; 2.988 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.648 ; 2.648 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.315 ; 2.315 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.975 ; 1.975 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.975 ; 1.975 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.965 ; 1.965 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 1.944 ; 1.944 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.934 ; 1.934 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.944 ; 1.944 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 4.028 ; 3.667 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                            ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.760     ; 2.831     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.820     ; 2.891     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.820     ; 2.891     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.820     ; 2.891     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.211     ; 3.282     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.568     ; 3.639     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.596     ; 3.667     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.640     ; 3.711     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.770     ; 3.841     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.430     ; 3.501     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.122     ; 3.193     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.800     ; 2.871     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.800     ; 2.871     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.790     ; 2.861     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.770     ; 2.841     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.760     ; 2.831     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.770     ; 2.841     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 4.209     ; 4.585     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                                    ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.792     ; 1.928     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.849     ; 1.985     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.849     ; 1.985     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.849     ; 1.985     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.225     ; 2.361     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.568     ; 2.704     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.594     ; 2.730     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.636     ; 2.772     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.762     ; 2.898     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.435     ; 2.571     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.140     ; 2.276     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.831     ; 1.967     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.831     ; 1.967     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.821     ; 1.957     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 1.802     ; 1.938     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.792     ; 1.928     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.802     ; 1.938     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.332     ; 3.693     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+


---------------------------------------------
; Slow 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+-------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup Summary                                                                    ;
+-------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                         ; Slack ; End Point TNS ;
+-------------------------------------------------------------------------------+-------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 6.173 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 7.918 ; 0.000         ;
+-------------------------------------------------------------------------------+-------+---------------+


+-------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold Summary                                                                     ;
+-------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                         ; Slack ; End Point TNS ;
+-------------------------------------------------------------------------------+-------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.178 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.181 ; 0.000         ;
+-------------------------------------------------------------------------------+-------+---------------+


+-------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery Summary                                                                 ;
+-------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                         ; Slack ; End Point TNS ;
+-------------------------------------------------------------------------------+-------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.824 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 9.903 ; 0.000         ;
+-------------------------------------------------------------------------------+-------+---------------+


+-------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal Summary                                                                  ;
+-------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                         ; Slack ; End Point TNS ;
+-------------------------------------------------------------------------------+-------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.986 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 1.720 ; 0.000         ;
+-------------------------------------------------------------------------------+-------+---------------+


+--------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width Summary                                                       ;
+-------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                         ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.658  ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.367 ; 0.000         ;
; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]  ; 17.598 ; 0.000         ;
; FPGA_CLK                                                                      ; 99.405 ; 0.000         ;
+-------------------------------------------------------------------------------+--------+---------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                       ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                         ; To Node                                      ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 6.173 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.092     ; 5.422      ;
; 6.214 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 5.374      ;
; 6.235 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.117     ; 5.335      ;
; 6.262 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.125     ; 5.300      ;
; 6.267 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.110     ; 5.310      ;
; 6.269 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.117     ; 5.301      ;
; 6.271 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 5.314      ;
; 6.287 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.118     ; 5.282      ;
; 6.287 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 5.301      ;
; 6.292 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[17]                                                                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 5.298      ;
; 6.293 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 5.292      ;
; 6.303 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.120     ; 5.264      ;
; 6.307 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.090     ; 5.290      ;
; 6.307 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 5.277      ;
; 6.327 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.119     ; 5.241      ;
; 6.328 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.125     ; 5.234      ;
; 6.333 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.127     ; 5.227      ;
; 6.339 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.091     ; 5.257      ;
; 6.339 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.125     ; 5.223      ;
; 6.343 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 5.242      ;
; 6.346 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[22]                                                                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 5.244      ;
; 6.347 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.124     ; 5.216      ;
; 6.351 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 5.237      ;
; 6.352 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.093     ; 5.242      ;
; 6.366 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.116     ; 5.205      ;
; 6.380 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.101     ; 5.206      ;
; 6.381 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.124     ; 5.182      ;
; 6.383 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.109     ; 5.195      ;
; 6.396 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[18]                                                                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 5.194      ;
; 6.398 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.124     ; 5.165      ;
; 6.399 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[13]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.108     ; 5.180      ;
; 6.401 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.116     ; 5.170      ;
; 6.404 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[17]                                                                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.104     ; 5.179      ;
; 6.404 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.120     ; 5.163      ;
; 6.405 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.109     ; 5.173      ;
; 6.406 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.109     ; 5.172      ;
; 6.408 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.110     ; 5.169      ;
; 6.409 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[10]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.125     ; 5.153      ;
; 6.410 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.118     ; 5.159      ;
; 6.411 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.100     ; 5.176      ;
; 6.413 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.124     ; 5.150      ;
; 6.413 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[13]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.118     ; 5.156      ;
; 6.415 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 5.170      ;
; 6.415 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.127     ; 5.145      ;
; 6.419 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[19]                                                                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 5.171      ;
; 6.419 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.115     ; 5.153      ;
; 6.426 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.118     ; 5.143      ;
; 6.428 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[4]                             ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.107     ; 5.152      ;
; 6.428 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.109     ; 5.150      ;
; 6.431 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.108     ; 5.148      ;
; 6.433 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.100     ; 5.154      ;
; 6.435 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.116     ; 5.136      ;
; 6.437 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.101     ; 5.149      ;
; 6.438 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[0]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.125     ; 5.124      ;
; 6.445 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.115     ; 5.127      ;
; 6.447 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.124     ; 5.116      ;
; 6.448 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 5.140      ;
; 6.449 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.109     ; 5.129      ;
; 6.450 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.125     ; 5.112      ;
; 6.451 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[13]                                                                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.118     ; 5.118      ;
; 6.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.117     ; 5.117      ;
; 6.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.118     ; 5.115      ;
; 6.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.127     ; 5.106      ;
; 6.455 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.109     ; 5.123      ;
; 6.456 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.114     ; 5.117      ;
; 6.458 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[17]                                                                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.096     ; 5.133      ;
; 6.458 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[22]                                                                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.104     ; 5.125      ;
; 6.459 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.101     ; 5.127      ;
; 6.462 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 5.122      ;
; 6.463 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[0]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 5.125      ;
; 6.469 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.119     ; 5.099      ;
; 6.470 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[17]                                                                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.104     ; 5.113      ;
; 6.471 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.109     ; 5.107      ;
; 6.473 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 5.112      ;
; 6.476 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[17]                                                                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.095     ; 5.116      ;
; 6.478 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.109     ; 5.100      ;
; 6.480 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.104     ; 5.103      ;
; 6.481 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.127     ; 5.079      ;
; 6.483 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[3]                             ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.111     ; 5.093      ;
; 6.483 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.100     ; 5.104      ;
; 6.484 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|oss_bank[1]                       ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.095     ; 5.108      ;
; 6.484 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 5.100      ;
; 6.485 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.110     ; 5.092      ;
; 6.487 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.118     ; 5.082      ;
; 6.487 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.124     ; 5.076      ;
; 6.494 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.127     ; 5.066      ;
; 6.500 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.118     ; 5.069      ;
; 6.504 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.107     ; 5.076      ;
; 6.508 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[18]                                                                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.104     ; 5.075      ;
; 6.509 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.101     ; 5.077      ;
; 6.510 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.124     ; 5.053      ;
; 6.511 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[13]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.115     ; 5.061      ;
; 6.512 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[22]                                                                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.096     ; 5.079      ;
; 6.521 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.109     ; 5.057      ;
; 6.522 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.125     ; 5.040      ;
; 6.523 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[17]                                                                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.098     ; 5.066      ;
; 6.523 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[17]                                                                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.104     ; 5.060      ;
; 6.524 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[22]                                                                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.104     ; 5.059      ;
; 6.525 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[13]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.125     ; 5.037      ;
; 6.526 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.121     ; 5.040      ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                            ;
+-------+----------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                  ; To Node                                                                                                                                                  ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 7.918 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.096     ; 3.721      ;
; 7.927 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.096     ; 3.712      ;
; 7.965 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 3.682      ;
; 7.975 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[29]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.096     ; 3.664      ;
; 8.037 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_noise_filter:pokey_noise_filter0|out_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.082     ; 3.616      ;
; 8.039 ; ram_do_reg[1]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.097     ; 3.599      ;
; 8.043 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.096     ; 3.596      ;
; 8.054 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[0]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 3.587      ;
; 8.054 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[2]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 3.597      ;
; 8.054 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[3]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 3.597      ;
; 8.055 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[4]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.080     ; 3.600      ;
; 8.088 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 3.559      ;
; 8.096 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[41]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 3.551      ;
; 8.105 ; ram_do_reg[1]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[27]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 3.535      ;
; 8.131 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[7]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 3.517      ;
; 8.131 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[4]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 3.517      ;
; 8.131 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[2]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 3.517      ;
; 8.131 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[1]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 3.517      ;
; 8.131 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[0]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 3.517      ;
; 8.131 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[3]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 3.517      ;
; 8.131 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[5]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 3.517      ;
; 8.131 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[6]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 3.517      ;
; 8.134 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_noise_filter:pokey_noise_filter1|out_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 3.507      ;
; 8.160 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 3.487      ;
; 8.162 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[7]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.079     ; 3.494      ;
; 8.162 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[6]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.079     ; 3.494      ;
; 8.162 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[5]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.079     ; 3.494      ;
; 8.162 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[3]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.079     ; 3.494      ;
; 8.162 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[1]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.079     ; 3.494      ;
; 8.162 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[0]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.079     ; 3.494      ;
; 8.162 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[2]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.079     ; 3.494      ;
; 8.189 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.097     ; 3.449      ;
; 8.190 ; ram_do_reg[0]              ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[0]                                                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.082     ; 3.463      ;
; 8.192 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[38]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 3.454      ;
; 8.201 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[2]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.079     ; 3.455      ;
; 8.210 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 3.436      ;
; 8.213 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 3.433      ;
; 8.214 ; ram_do_reg[1]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.090     ; 3.431      ;
; 8.226 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_noise_filter:pokey_noise_filter3|out_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 3.421      ;
; 8.262 ; ram_do_reg[1]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.090     ; 3.383      ;
; 8.280 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[0]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 3.361      ;
; 8.282 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.096     ; 3.357      ;
; 8.282 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[1]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.096     ; 3.357      ;
; 8.282 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[2]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.096     ; 3.357      ;
; 8.282 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[3]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.096     ; 3.357      ;
; 8.282 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[4]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.096     ; 3.357      ;
; 8.282 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[5]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.096     ; 3.357      ;
; 8.282 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[6]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.096     ; 3.357      ;
; 8.282 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[7]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.096     ; 3.357      ;
; 8.283 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[19]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 3.364      ;
; 8.284 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[7]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 3.364      ;
; 8.284 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[5]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 3.364      ;
; 8.284 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[4]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 3.364      ;
; 8.284 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[2]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 3.364      ;
; 8.284 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[1]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 3.364      ;
; 8.284 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[0]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 3.364      ;
; 8.284 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[3]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 3.364      ;
; 8.284 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[6]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 3.364      ;
; 8.294 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 3.358      ;
; 8.294 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 3.358      ;
; 8.294 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 3.358      ;
; 8.294 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 3.358      ;
; 8.294 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[4] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 3.358      ;
; 8.294 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[5] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 3.358      ;
; 8.307 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[39]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 3.334      ;
; 8.307 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|highpass1_reg                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 3.333      ;
; 8.318 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 3.328      ;
; 8.321 ; ram_do_reg[0]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 3.325      ;
; 8.322 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[6]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.080     ; 3.333      ;
; 8.322 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[5]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.080     ; 3.333      ;
; 8.322 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[1]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.080     ; 3.333      ;
; 8.322 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[0]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.080     ; 3.333      ;
; 8.322 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[3]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.080     ; 3.333      ;
; 8.322 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[4]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.080     ; 3.333      ;
; 8.322 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[7]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.080     ; 3.333      ;
; 8.338 ; ram_do_reg[0]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[0]                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.085     ; 3.312      ;
; 8.352 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_noise_filter:pokey_noise_filter0|out_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 3.297      ;
; 8.353 ; ram_do_reg[1]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[0]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.095     ; 3.287      ;
; 8.354 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[37]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 3.293      ;
; 8.361 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.090     ; 3.284      ;
; 8.362 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.090     ; 3.283      ;
; 8.364 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer1|count_reg[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 3.273      ;
; 8.364 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer1|count_reg[1]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 3.273      ;
; 8.364 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer1|count_reg[2]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 3.273      ;
; 8.364 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer1|count_reg[3]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 3.273      ;
; 8.364 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer1|count_reg[4]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 3.273      ;
; 8.364 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer1|count_reg[5]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 3.273      ;
; 8.364 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer1|count_reg[6]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 3.273      ;
; 8.364 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer1|count_reg[7]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 3.273      ;
; 8.364 ; ram_do_reg[1]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 3.282      ;
; 8.369 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[7]                                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 3.277      ;
; 8.373 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer3|count_reg[0]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 3.264      ;
; 8.373 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer3|count_reg[1]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 3.264      ;
; 8.373 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer3|count_reg[2]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 3.264      ;
; 8.373 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer3|count_reg[3]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 3.264      ;
; 8.373 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer3|count_reg[4]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 3.264      ;
; 8.373 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer3|count_reg[5]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 3.264      ;
; 8.373 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer3|count_reg[6]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 3.264      ;
; 8.373 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer3|count_reg[7]                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 3.264      ;
; 8.379 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[14]                                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 3.262      ;
+-------+----------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                   ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                    ; To Node                                                                                                                                      ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 0.178 ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[5]                                                                                  ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_9f41:auto_generated|ram_block1a0~porta_address_reg0              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.218      ; 0.500      ;
; 0.179 ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[6]                                                                                  ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_9f41:auto_generated|ram_block1a0~porta_address_reg0              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.218      ; 0.501      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[31]                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[31]                                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|idle_reg[1]                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|idle_reg[1]                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|idle_reg[2]                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|idle_reg[2]                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|idle_reg[3]                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|idle_reg[3]                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|first_line_of_instruction_reg                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|first_line_of_instruction_reg                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[29]                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[29]                                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[84]                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[84]                                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[273]                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[273]                                                                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[85]                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[85]                                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[93]                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[93]                                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[26]                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[26]                                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[21]                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[21]                                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[6]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[6]                                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[67]                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[67]                                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[46]                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[46]                                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[12]                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[12]                                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[44]                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[44]                                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[13]                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[13]                                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[70]                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[70]                                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[75]                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[75]                                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[65]                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[65]                                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[42]                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[42]                                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[3]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[3]                                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[364]                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[364]                                                                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[68]                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[68]                                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[60]                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[60]                                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[5]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[5]                                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[76]                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[76]                                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[77]                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[77]                                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[73]                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[73]                                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[4]                                                                                                ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[4]                                                                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[2]                                                                                   ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[2]                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[3]                                                                                   ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[3]                                                                                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|skctl_reg[0]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|skctl_reg[0]                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[0]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[0]                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[1]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[1]                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[2]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[2]                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[3]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[3]                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[7]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[7]                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[4]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[4]                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[5]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[5]                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[6]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[6]                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0]                   ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[0]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[0]                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[3]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[3]                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[1]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[1]                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[2]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[2]                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[7]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[7]                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer1|delay_line:underflow0_delay|shift_reg[0]                   ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer1|delay_line:underflow0_delay|shift_reg[0]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[2]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[2]                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[0]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[0]                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[1]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[1]                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[3]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[3]                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[6]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[6]                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[4]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[4]                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[5]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[5]                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[7]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[7]                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer3|delay_line:underflow0_delay|shift_reg[0]                   ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer3|delay_line:underflow0_delay|shift_reg[0]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_clock_reg                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_clock_reg                                                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|twotone_reg                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|twotone_reg                                                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vsync_reg                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vsync_reg                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[10]                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[10]                                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[20]                                                                                               ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[20]                                                                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[276]                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[276]                                                                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[131]                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[131]                                                                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[369]                                                                                              ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[369]                                                                                              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|last_line_of_instruction_reg                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|last_line_of_instruction_reg                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pot_reset_reg                                                                           ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pot_reset_reg                                                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|ss_n[0]                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|ss_n[0]                                                                       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|irqst_reg[0]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|irqst_reg[0]                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|irqst_reg[1]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|irqst_reg[1]                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|irqst_reg[2]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|irqst_reg[2]                                                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_refresh_count|value_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_refresh_count|value_reg[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_refresh_count|value_reg[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_refresh_count|value_reg[2] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_refresh_count|value_reg[3] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_refresh_count|value_reg[3] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|sclk                                                                          ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|sclk                                                                          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[1]                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[1]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[3]                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[3]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[4]                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[4]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile2|shift_reg[7]                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile2|shift_reg[7]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile2|count_reg[1]                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile2|count_reg[1]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile2|shift_reg[6]                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile2|shift_reg[6]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p3pf_reg[2]                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p3pf_reg[2]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|count_reg[1]                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|count_reg[1]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[3]                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[3]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[4]                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[4]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[5]                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[5]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pf_reg[2]                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pf_reg[2]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p2pl_reg[3]                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p2pl_reg[3]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pl_reg[2]                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pl_reg[2]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pl_reg[2]                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pl_reg[2]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pf_reg[2]                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pf_reg[2]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pf_reg[2]                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pf_reg[2]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pl_reg[1]                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pl_reg[1]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p2pf_reg[1]                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p2pf_reg[1]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pf_reg[1]                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pf_reg[1]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pf_reg[1]                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pf_reg[1]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pf_reg[1]                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pf_reg[1]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                               ;
+-------+-----------------------------------------------------------------------------------------------------------------+-------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                       ; To Node                                               ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------+-------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 0.181 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                           ; sdram_ctrl:sdram_controller|sdram_rdy                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.042      ; 0.307      ;
; 0.187 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                                      ; sdram_ctrl:sdram_controller|r_init_tmr[10]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[0]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_refr_act                                                                          ; sdram_ctrl:sdram_controller|r_refr_act                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_wr_act                                                                            ; sdram_ctrl:sdram_controller|r_wr_act                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_wr_bctr[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                                                                        ; sdram_ctrl:sdram_controller|r_bst_stp[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_rd_bctr[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_rd_act                                                                            ; sdram_ctrl:sdram_controller|r_rd_act                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_request_complete_reg                                                                                      ; sdram_request_complete_reg                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.195 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[0]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.314      ;
; 0.202 ; sdram_ctrl:sdram_controller|r_rd_act                                                                            ; sdram_ctrl:sdram_controller|ap1_rd_bst_act            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.321      ;
; 0.202 ; seq_reg[10]                                                                                                     ; sdram_ctrl:sdram_controller|sdram_rdy                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.042      ; 0.328      ;
; 0.206 ; seq_reg[10]                                                                                                     ; seq_reg[11]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.042      ; 0.332      ;
; 0.211 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.331      ;
; 0.217 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.337      ;
; 0.223 ; sdram_ctrl:sdram_controller|r_rd_reg                                                                            ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.342      ;
; 0.227 ; seq_reg[11]                                                                                                     ; seq_reg[0]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.042      ; 0.353      ;
; 0.265 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[19] ; ram_di_reg[3]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 0.458      ;
; 0.265 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[25] ; ram_di_reg[9]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 0.458      ;
; 0.266 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[21] ; ram_di_reg[5]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 0.459      ;
; 0.285 ; sdram_ctrl:sdram_controller|r_refr_act                                                                          ; sdram_ctrl:sdram_controller|r_wr_reg                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.404      ;
; 0.285 ; sdram_ctrl:sdram_controller|r_refr_act                                                                          ; sdram_ctrl:sdram_controller|r_rd_reg                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.404      ;
; 0.288 ; seq_reg[5]                                                                                                      ; seq_reg[6]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.407      ;
; 0.290 ; seq_reg[8]                                                                                                      ; seq_reg[9]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.042      ; 0.416      ;
; 0.293 ; seq_reg[9]                                                                                                      ; seq_reg[10]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.042      ; 0.419      ;
; 0.294 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.413      ;
; 0.294 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.413      ;
; 0.295 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.414      ;
; 0.295 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.414      ;
; 0.295 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.414      ;
; 0.295 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                                                                        ; sdram_ctrl:sdram_controller|r_rd_bctr[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.414      ;
; 0.296 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.415      ;
; 0.296 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.415      ;
; 0.296 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.415      ;
; 0.296 ; sdram_ctrl:sdram_controller|r_psel_dly[0]                                                                       ; sdram_ctrl:sdram_controller|ap1_rd_bst_act            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.415      ;
; 0.298 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_rd_act                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.417      ;
; 0.301 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.420      ;
; 0.301 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.420      ;
; 0.309 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_wr_act                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.428      ;
; 0.323 ; sdram_ctrl:sdram_controller|r_rd_reg                                                                            ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]          ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.442      ;
; 0.324 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[23] ; ram_di_reg[7]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 0.517      ;
; 0.325 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[26] ; ram_di_reg[10]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 0.518      ;
; 0.329 ; sdram_ctrl:sdram_controller|r_rd_act                                                                            ; sdram_ctrl:sdram_controller|r_rd_bctr[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.448      ;
; 0.347 ; seq_reg[6]                                                                                                      ; seq_reg[7]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.466      ;
; 0.347 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                                      ; sdram_ctrl:sdram_controller|r_init_fsm[1]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.467      ;
; 0.356 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[10]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.476      ;
; 0.361 ; seq_reg[2]                                                                                                      ; seq_reg[3]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.480      ;
; 0.365 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[16] ; ram_di_reg[0]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 0.558      ;
; 0.365 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[17] ; ram_di_reg[1]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 0.558      ;
; 0.365 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[20] ; ram_di_reg[4]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 0.558      ;
; 0.366 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[18] ; ram_di_reg[2]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 0.559      ;
; 0.367 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[24] ; ram_di_reg[8]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 0.560      ;
; 0.371 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[0]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.491      ;
; 0.374 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                                      ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.494      ;
; 0.377 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                                      ; sdram_ctrl:sdram_controller|r_init_fsm[0]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.497      ;
; 0.388 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[22] ; ram_di_reg[6]                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 0.581      ;
; 0.392 ; sdram_ctrl:sdram_controller|r_psel[0]                                                                           ; sdram_ctrl:sdram_controller|r_psel_dly[0]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.512      ;
; 0.395 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[28] ; ram_di_reg[12]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 0.588      ;
; 0.412 ; sdram_ctrl:sdram_controller|r_wr_act                                                                            ; sdram_ctrl:sdram_controller|r_wr_bctr[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.531      ;
; 0.443 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.562      ;
; 0.443 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.562      ;
; 0.444 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.563      ;
; 0.444 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.563      ;
; 0.449 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[27] ; ram_di_reg[11]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.089      ; 0.641      ;
; 0.451 ; seq_reg[1]                                                                                                      ; seq_reg[2]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.570      ;
; 0.453 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.572      ;
; 0.453 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.572      ;
; 0.454 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.573      ;
; 0.454 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.573      ;
; 0.454 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[2]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.573      ;
; 0.456 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.575      ;
; 0.456 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.575      ;
; 0.457 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.576      ;
; 0.457 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.576      ;
; 0.457 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.576      ;
; 0.472 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                                       ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.592      ;
; 0.478 ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1                                                           ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.597      ;
; 0.489 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[12] ; ram_di_reg[12]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 0.682      ;
; 0.490 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[30] ; ram_di_reg[14]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 0.683      ;
; 0.491 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[29] ; ram_di_reg[13]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 0.684      ;
; 0.504 ; sdram_ctrl:sdram_controller|r_psel[0]                                                                           ; sdram_ctrl:sdram_controller|r_bst_stp[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.624      ;
; 0.506 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.625      ;
; 0.507 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.626      ;
; 0.507 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.626      ;
; 0.509 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.628      ;
; 0.510 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.629      ;
; 0.510 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.629      ;
; 0.515 ; sdram_request_reg                                                                                               ; sdram_ctrl:sdram_controller|r_psel[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -0.141     ; 0.458      ;
; 0.518 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[10] ; ram_di_reg[10]                                        ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.090      ; 0.711      ;
; 0.519 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.638      ;
; 0.519 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.638      ;
; 0.520 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.639      ;
; 0.520 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.639      ;
; 0.522 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.641      ;
; 0.522 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.641      ;
; 0.523 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.642      ;
; 0.523 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.642      ;
+-------+-----------------------------------------------------------------------------------------------------------------+-------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                          ;
+-------+---------------------------------------+----------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                                                        ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+----------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 8.824 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[14]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.260     ; 2.651      ;
; 8.831 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[8]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.257     ; 2.647      ;
; 8.836 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_8BIT_WRITE_ENABLE_reg    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.263     ; 2.636      ;
; 8.836 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_READ_reg                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.263     ; 2.636      ;
; 8.837 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[22]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.268     ; 2.630      ;
; 8.837 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[19]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.268     ; 2.630      ;
; 8.849 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.259     ; 2.627      ;
; 8.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[18]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.267     ; 2.618      ;
; 8.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[21]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.267     ; 2.618      ;
; 8.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[23]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.267     ; 2.618      ;
; 8.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[20]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.267     ; 2.618      ;
; 8.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[16]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.267     ; 2.618      ;
; 8.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[17]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.267     ; 2.618      ;
; 8.858 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[8]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.242     ; 2.635      ;
; 8.886 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[14]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.244     ; 2.605      ;
; 8.886 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[15]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.244     ; 2.605      ;
; 9.049 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[17]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.268     ; 2.418      ;
; 9.049 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[13]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.261     ; 2.425      ;
; 9.049 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[1]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.258     ; 2.428      ;
; 9.049 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[4]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.258     ; 2.428      ;
; 9.049 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[5]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.258     ; 2.428      ;
; 9.049 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[10]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.262     ; 2.424      ;
; 9.049 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[12]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.261     ; 2.425      ;
; 9.049 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[11]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.262     ; 2.424      ;
; 9.049 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.268     ; 2.418      ;
; 9.050 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[25]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.256     ; 2.429      ;
; 9.051 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[11]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.257     ; 2.427      ;
; 9.051 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.257     ; 2.427      ;
; 9.051 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.257     ; 2.427      ;
; 9.051 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|memory_ready_reg             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.261     ; 2.423      ;
; 9.051 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.257     ; 2.427      ;
; 9.053 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[3]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.262     ; 2.420      ;
; 9.053 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[6]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.262     ; 2.420      ;
; 9.053 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[1]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.262     ; 2.420      ;
; 9.053 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[7]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.262     ; 2.420      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[4]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.263     ; 2.418      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[5]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.258     ; 2.423      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[16]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.257     ; 2.424      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[21]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.257     ; 2.424      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[22]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.257     ; 2.424      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[25]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.257     ; 2.424      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[22]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.254     ; 2.427      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[22]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.254     ; 2.427      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[8]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.254     ; 2.427      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[8]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.254     ; 2.427      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[8]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.257     ; 2.424      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[2]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.258     ; 2.423      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[8]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.259     ; 2.422      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[27]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.254     ; 2.427      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[27]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.254     ; 2.427      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[27]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.257     ; 2.424      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[18]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.254     ; 2.427      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[18]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.257     ; 2.424      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[12]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.259     ; 2.422      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[10]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.254     ; 2.427      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[10]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.259     ; 2.422      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[11]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.259     ; 2.422      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[13]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.259     ; 2.422      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[0]    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.254     ; 2.427      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[16]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.258     ; 2.423      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[14]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.259     ; 2.422      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[24]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.257     ; 2.424      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[26]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.257     ; 2.424      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[0]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.254     ; 2.427      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[0]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.257     ; 2.424      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[9]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.259     ; 2.422      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[3]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.257     ; 2.424      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[23]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.257     ; 2.424      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[23]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.254     ; 2.427      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[23]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.254     ; 2.427      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[30]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.257     ; 2.424      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[30]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.254     ; 2.427      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[1]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.257     ; 2.424      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[9]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.254     ; 2.427      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[9]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.254     ; 2.427      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[9]            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.254     ; 2.427      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[2]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.257     ; 2.424      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[15]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.259     ; 2.422      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[19]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.254     ; 2.427      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[19]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.254     ; 2.427      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[19]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.254     ; 2.427      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[19]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.257     ; 2.424      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[20]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.257     ; 2.424      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[20]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.254     ; 2.427      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[20]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.254     ; 2.427      ;
; 9.055 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[17]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.263     ; 2.417      ;
; 9.055 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[22]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.263     ; 2.417      ;
; 9.055 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[18]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.263     ; 2.417      ;
; 9.055 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[21]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.263     ; 2.417      ;
; 9.055 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[20]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.263     ; 2.417      ;
; 9.055 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[19]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.263     ; 2.417      ;
; 9.056 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[31]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.264     ; 2.415      ;
; 9.056 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[22]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.268     ; 2.411      ;
; 9.056 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[22]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.263     ; 2.416      ;
; 9.056 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[5]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.263     ; 2.416      ;
; 9.056 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[16]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.268     ; 2.411      ;
; 9.056 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[2]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.263     ; 2.416      ;
; 9.056 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[4]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.263     ; 2.416      ;
; 9.056 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[15]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.267     ; 2.412      ;
; 9.056 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[20]           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.266     ; 2.413      ;
+-------+---------------------------------------+----------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                       ;
+--------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node              ; To Node                                                   ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 9.903  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[0]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.137     ; 1.647      ;
; 9.903  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[1]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.137     ; 1.647      ;
; 9.903  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[2]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.137     ; 1.647      ;
; 9.903  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[3]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.139     ; 1.645      ;
; 9.904  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[7]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.138     ; 1.645      ;
; 9.905  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[0]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.191     ; 1.589      ;
; 9.905  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[1]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.191     ; 1.589      ;
; 9.905  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[2]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.191     ; 1.589      ;
; 9.905  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[3]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.193     ; 1.587      ;
; 9.905  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[6]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.138     ; 1.644      ;
; 9.906  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[7]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.192     ; 1.587      ;
; 9.907  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[6]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.192     ; 1.586      ;
; 9.907  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[5]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.142     ; 1.638      ;
; 9.908  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[4]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.144     ; 1.635      ;
; 9.909  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[5]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.196     ; 1.580      ;
; 9.910  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[4]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.198     ; 1.577      ;
; 9.913  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[10]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.136     ; 1.638      ;
; 9.913  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[11]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.136     ; 1.638      ;
; 9.913  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[12]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.136     ; 1.638      ;
; 9.913  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.114     ; 1.660      ;
; 9.913  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.114     ; 1.660      ;
; 9.914  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.112     ; 1.661      ;
; 9.914  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[0]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.114     ; 1.659      ;
; 9.914  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[1]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.114     ; 1.659      ;
; 9.914  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[2]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.114     ; 1.659      ;
; 9.914  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[3]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.114     ; 1.659      ;
; 9.914  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[13]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.134     ; 1.639      ;
; 9.914  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[14]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.134     ; 1.639      ;
; 9.914  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[15]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.134     ; 1.639      ;
; 9.915  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[10]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.190     ; 1.580      ;
; 9.915  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[12]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.190     ; 1.580      ;
; 9.915  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[11]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.190     ; 1.580      ;
; 9.916  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[15]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.188     ; 1.581      ;
; 9.916  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[13]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.188     ; 1.581      ;
; 9.916  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[14]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.188     ; 1.581      ;
; 9.918  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[8]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.130     ; 1.639      ;
; 9.918  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[9]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.136     ; 1.633      ;
; 9.920  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[9]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.190     ; 1.575      ;
; 9.920  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[8]                   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.184     ; 1.581      ;
; 9.927  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[5]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.107     ; 1.653      ;
; 9.927  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[6]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.108     ; 1.652      ;
; 9.927  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[7]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.108     ; 1.652      ;
; 9.928  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[4]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.105     ; 1.654      ;
; 9.928  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[8]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.106     ; 1.653      ;
; 9.928  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.106     ; 1.653      ;
; 10.031 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.112     ; 1.544      ;
; 10.031 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.112     ; 1.544      ;
; 10.031 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.112     ; 1.544      ;
; 10.031 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.112     ; 1.544      ;
; 10.151 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 1.481      ;
; 10.151 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 1.481      ;
; 10.151 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 1.481      ;
; 10.151 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 1.481      ;
; 10.151 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 1.481      ;
; 10.151 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 1.481      ;
; 10.151 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 1.481      ;
; 10.151 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 1.481      ;
; 10.151 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 1.481      ;
; 10.151 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 1.481      ;
; 10.151 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.109     ; 1.474      ;
; 10.151 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.109     ; 1.474      ;
; 10.151 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.109     ; 1.474      ;
; 10.151 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.109     ; 1.474      ;
; 10.151 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.109     ; 1.474      ;
; 10.151 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.109     ; 1.474      ;
; 10.151 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.110     ; 1.473      ;
; 10.151 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.109     ; 1.474      ;
; 10.152 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 1.480      ;
; 10.152 ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 1.480      ;
; 10.152 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 1.480      ;
; 10.152 ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 1.480      ;
; 10.152 ; sdram_reset_ctrl_n_reg ; ram_di_reg[6]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 1.480      ;
; 10.152 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 1.480      ;
; 10.152 ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 1.480      ;
; 10.152 ; sdram_reset_ctrl_n_reg ; ram_di_reg[11]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 1.480      ;
; 10.152 ; sdram_reset_ctrl_n_reg ; ram_di_reg[12]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 1.480      ;
; 10.152 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 1.480      ;
; 10.152 ; sdram_reset_ctrl_n_reg ; ram_di_reg[14]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 1.480      ;
; 10.152 ; sdram_reset_ctrl_n_reg ; ram_di_reg[15]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 1.480      ;
; 10.153 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.100     ; 1.481      ;
; 10.153 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.100     ; 1.481      ;
; 10.153 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.100     ; 1.481      ;
; 10.153 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.100     ; 1.481      ;
; 10.154 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.101     ; 1.479      ;
; 10.154 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.481      ;
; 10.154 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.481      ;
; 10.154 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.481      ;
; 10.154 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.101     ; 1.479      ;
; 10.154 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.101     ; 1.479      ;
; 10.154 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.101     ; 1.479      ;
; 10.154 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.101     ; 1.479      ;
; 10.154 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.098     ; 1.482      ;
; 10.154 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.481      ;
; 10.154 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.481      ;
; 10.154 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.481      ;
; 10.154 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.101     ; 1.479      ;
; 10.155 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.480      ;
; 10.155 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.480      ;
; 10.155 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.480      ;
; 10.155 ; sdram_reset_ctrl_n_reg ; ram_do_reg[25]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.480      ;
+--------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                       ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                                   ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 0.986 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.253      ; 1.342      ;
; 0.986 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.253      ; 1.342      ;
; 0.986 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.253      ; 1.342      ;
; 0.986 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.253      ; 1.342      ;
; 0.986 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                               ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.253      ; 1.342      ;
; 0.986 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.253      ; 1.342      ;
; 0.986 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.253      ; 1.342      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 1.350      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 1.350      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 1.350      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; seq_reg[5]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 1.350      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 1.350      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 1.350      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.349      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.349      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.349      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; ram_do_reg[25]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.349      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.349      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.349      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.349      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; ram_do_reg[5]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.349      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.349      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; ram_do_reg[12]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.349      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.349      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; ram_do_reg[13]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.349      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.349      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; ram_do_reg[9]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.349      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.349      ;
; 1.164 ; sdram_reset_ctrl_n_reg ; ram_do_reg[20]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.349      ;
; 1.165 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.349      ;
; 1.165 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.349      ;
; 1.165 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.349      ;
; 1.165 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.349      ;
; 1.165 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.349      ;
; 1.165 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.349      ;
; 1.165 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 1.347      ;
; 1.165 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 1.347      ;
; 1.165 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 1.347      ;
; 1.165 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.349      ;
; 1.165 ; sdram_reset_ctrl_n_reg ; ram_do_reg[8]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.349      ;
; 1.165 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.349      ;
; 1.165 ; sdram_reset_ctrl_n_reg ; ram_do_reg[11]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.349      ;
; 1.165 ; sdram_reset_ctrl_n_reg ; ram_do_reg[14]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.349      ;
; 1.165 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.349      ;
; 1.165 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.349      ;
; 1.165 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.349      ;
; 1.165 ; sdram_reset_ctrl_n_reg ; ram_do_reg[15]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.349      ;
; 1.165 ; sdram_reset_ctrl_n_reg ; ram_do_reg[19]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.349      ;
; 1.165 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[0]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.352      ;
; 1.165 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[1]                                           ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.352      ;
; 1.166 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 1.348      ;
; 1.166 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.350      ;
; 1.166 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.350      ;
; 1.166 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.350      ;
; 1.166 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.350      ;
; 1.166 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.350      ;
; 1.166 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.350      ;
; 1.166 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.350      ;
; 1.166 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 1.348      ;
; 1.166 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 1.348      ;
; 1.166 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 1.348      ;
; 1.166 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 1.348      ;
; 1.166 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.351      ;
; 1.166 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.350      ;
; 1.166 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.350      ;
; 1.166 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.350      ;
; 1.166 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.079      ; 1.348      ;
; 1.168 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.349      ;
; 1.168 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.349      ;
; 1.168 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.349      ;
; 1.168 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.349      ;
; 1.168 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.349      ;
; 1.168 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.349      ;
; 1.168 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.349      ;
; 1.168 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.349      ;
; 1.168 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.349      ;
; 1.168 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.349      ;
; 1.168 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.349      ;
; 1.168 ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.349      ;
; 1.168 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.349      ;
; 1.168 ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.349      ;
; 1.168 ; sdram_reset_ctrl_n_reg ; ram_di_reg[6]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.349      ;
; 1.168 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.349      ;
; 1.168 ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                             ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.349      ;
; 1.168 ; sdram_reset_ctrl_n_reg ; ram_di_reg[11]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.349      ;
; 1.168 ; sdram_reset_ctrl_n_reg ; ram_di_reg[12]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.349      ;
; 1.168 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.349      ;
; 1.168 ; sdram_reset_ctrl_n_reg ; ram_di_reg[14]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.349      ;
; 1.168 ; sdram_reset_ctrl_n_reg ; ram_di_reg[15]                                            ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.349      ;
; 1.169 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.071      ; 1.343      ;
; 1.169 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.071      ; 1.343      ;
; 1.169 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.071      ; 1.343      ;
; 1.169 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.071      ; 1.343      ;
; 1.169 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.071      ; 1.343      ;
; 1.169 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.071      ; 1.343      ;
; 1.169 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.070      ; 1.342      ;
; 1.169 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.071      ; 1.343      ;
; 1.266 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.072      ; 1.415      ;
; 1.266 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                 ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.072      ; 1.415      ;
; 1.266 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.072      ; 1.415      ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                ;
+-------+-------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node         ; To Node                                                                                                                                                 ; Launch Clock                                                                  ; Latch Clock                                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+
; 1.720 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[0]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.264      ; 2.068      ;
; 1.720 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[4]                                                ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.264      ; 2.068      ;
; 1.732 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[4]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.247      ; 2.063      ;
; 1.913 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|break_pressed_reg   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.053      ; 2.050      ;
; 1.913 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|shift_pressed_reg   ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.053      ; 2.050      ;
; 1.913 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[1]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.047      ; 2.044      ;
; 1.913 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_raw_reg[1]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.047      ; 2.044      ;
; 1.913 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_raw_reg[0]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.047      ; 2.044      ;
; 1.913 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_raw_reg[5]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.047      ; 2.044      ;
; 1.913 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_raw_reg[4]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.047      ; 2.044      ;
; 1.913 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_raw_reg[7]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.047      ; 2.044      ;
; 1.913 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_raw_reg[2]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.047      ; 2.044      ;
; 1.913 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp0_raw_reg[6]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.050      ; 2.047      ;
; 1.913 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp0_raw_reg[1]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.050      ; 2.047      ;
; 1.913 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp0_raw_reg[4]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.050      ; 2.047      ;
; 1.913 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp0_raw_reg[5]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.050      ; 2.047      ;
; 1.913 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp0_delay|shift_reg[2][5]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.052      ; 2.049      ;
; 1.913 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm3_delay|shift_reg[4][7]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.049      ; 2.046      ;
; 1.913 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm3_delay|shift_reg[3][7]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.049      ; 2.046      ;
; 1.913 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm3_delay|shift_reg[2][7]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.049      ; 2.046      ;
; 1.913 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm3_delay|shift_reg[1][7]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.049      ; 2.046      ;
; 1.913 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm3_delay|shift_reg[0][7]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.049      ; 2.046      ;
; 1.913 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm3_delay|shift_reg[4][6]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.049      ; 2.046      ;
; 1.913 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm3_delay|shift_reg[3][6]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.049      ; 2.046      ;
; 1.913 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm3_delay|shift_reg[2][6]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.049      ; 2.046      ;
; 1.913 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm3_delay|shift_reg[1][6]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.049      ; 2.046      ;
; 1.913 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm3_delay|shift_reg[0][6]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.049      ; 2.046      ;
; 1.913 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm1_delay|shift_reg[3][7]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.049      ; 2.046      ;
; 1.913 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm1_delay|shift_reg[2][7]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.049      ; 2.046      ;
; 1.913 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm1_delay|shift_reg[1][7]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.049      ; 2.046      ;
; 1.913 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm1_delay|shift_reg[0][7]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.049      ; 2.046      ;
; 1.913 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm1_delay|shift_reg[0][6]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.049      ; 2.046      ;
; 1.913 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_raw_reg[3]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.053      ; 2.050      ;
; 1.913 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[4][3]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.053      ; 2.050      ;
; 1.913 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[3][3]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.053      ; 2.050      ;
; 1.913 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[2][3]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.053      ; 2.050      ;
; 1.913 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_raw_reg[2]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.053      ; 2.050      ;
; 1.913 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[4][2]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.053      ; 2.050      ;
; 1.913 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[3][2]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.053      ; 2.050      ;
; 1.913 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[2][2]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.053      ; 2.050      ;
; 1.913 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_raw_reg[4]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.053      ; 2.050      ;
; 1.913 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[4][4]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.053      ; 2.050      ;
; 1.913 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[3][4]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.053      ; 2.050      ;
; 1.913 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[2][4]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.053      ; 2.050      ;
; 1.913 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[1][4]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.053      ; 2.050      ;
; 1.913 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp1_delay|shift_reg[0][4]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.052      ; 2.049      ;
; 1.913 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpf2_raw_reg[4]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.048      ; 2.045      ;
; 1.913 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpf2_raw_reg[2]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.048      ; 2.045      ;
; 1.913 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpf2_raw_reg[6]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.048      ; 2.045      ;
; 1.913 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|colpf2_raw_reg[7]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.048      ; 2.045      ;
; 1.914 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|bincnt_reg[0]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.053      ; 2.051      ;
; 1.914 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|bincnt_reg[1]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.053      ; 2.051      ;
; 1.914 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|bincnt_reg[2]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.053      ; 2.051      ;
; 1.914 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|bincnt_reg[3]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.053      ; 2.051      ;
; 1.914 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|bincnt_reg[4]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.053      ; 2.051      ;
; 1.914 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|bincnt_reg[5]       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.053      ; 2.051      ;
; 1.914 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|control_pressed_reg ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.052      ; 2.050      ;
; 1.914 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[3]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.045      ; 2.043      ;
; 1.914 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[4][3]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.053      ; 2.051      ;
; 1.914 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[3][3]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.053      ; 2.051      ;
; 1.914 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[2][3]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.053      ; 2.051      ;
; 1.914 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[1][3]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.053      ; 2.051      ;
; 1.914 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[2]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.045      ; 2.043      ;
; 1.914 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[4][1]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.048      ; 2.046      ;
; 1.914 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[3][1]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.048      ; 2.046      ;
; 1.914 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[1][1]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.048      ; 2.046      ;
; 1.914 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[0][1]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.048      ; 2.046      ;
; 1.914 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[6]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.045      ; 2.043      ;
; 1.914 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[4][6]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 2.042      ;
; 1.914 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[3][6]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 2.042      ;
; 1.914 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[2][6]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 2.042      ;
; 1.914 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[1][6]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 2.042      ;
; 1.914 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm2_delay|shift_reg[0][6]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 2.042      ;
; 1.914 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_raw_reg[5]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.045      ; 2.043      ;
; 1.914 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_raw_reg[6]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.049      ; 2.047      ;
; 1.914 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_raw_reg[3]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.049      ; 2.047      ;
; 1.914 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_raw_reg[4]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.049      ; 2.047      ;
; 1.914 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_raw_reg[5]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.049      ; 2.047      ;
; 1.914 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[4][5]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.046      ; 2.044      ;
; 1.914 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[3][5]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.046      ; 2.044      ;
; 1.914 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[2][5]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.046      ; 2.044      ;
; 1.914 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[1][5]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.048      ; 2.046      ;
; 1.914 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[0][5]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.048      ; 2.046      ;
; 1.914 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[4][4]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.048      ; 2.046      ;
; 1.914 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[3][4]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.048      ; 2.046      ;
; 1.914 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[2][4]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.048      ; 2.046      ;
; 1.914 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[1][4]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.048      ; 2.046      ;
; 1.914 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[0][4]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.048      ; 2.046      ;
; 1.914 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_raw_reg[6]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 2.042      ;
; 1.914 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[4][6]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 2.042      ;
; 1.914 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[3][6]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 2.042      ;
; 1.914 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[2][6]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 2.042      ;
; 1.914 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[1][6]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 2.042      ;
; 1.914 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[0][6]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 2.042      ;
; 1.914 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[4][7]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 2.042      ;
; 1.914 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[3][7]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 2.042      ;
; 1.914 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[2][7]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 2.042      ;
; 1.914 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[1][7]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 2.042      ;
; 1.914 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[0][7]                         ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 2.042      ;
; 1.914 ; sdram_reset_n_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_raw_reg[3]                                                    ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.051      ; 2.049      ;
+-------+-------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                         ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                         ; Clock Edge ; Target                                                    ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[0]                                           ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[1]                                           ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[11]                                            ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[12]                                            ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[13]                                            ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[14]                                            ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[15]                                            ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[1]                                             ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[3]                                             ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[4]                                             ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[5]                                             ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[6]                                             ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[7]                                             ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[9]                                             ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[0]                                             ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[11]                                            ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[14]                                            ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[15]                                            ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[16]                                            ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[19]                                            ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[22]                                            ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[23]                                            ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[24]                                            ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[27]                                            ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[30]                                            ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[31]                                            ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[3]                                             ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[6]                                             ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[7]                                             ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[8]                                             ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_reg                      ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_act                    ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_act                      ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_reg                      ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_complete_reg                                ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[1]                                                ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[2]                                                ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[3]                                                ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[5]                                                ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[6]                                                ;
; 5.658 ; 5.874        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[7]                                                ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[0]                                             ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[10]                                            ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[2]                                             ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[8]                                             ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[10]                                            ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[12]                                            ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[13]                                            ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[17]                                            ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[18]                                            ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[1]                                             ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[20]                                            ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[21]                                            ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[25]                                            ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[26]                                            ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[28]                                            ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[29]                                            ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[2]                                             ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[4]                                             ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[5]                                             ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[9]                                             ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel[0]                     ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_act                      ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_req                    ;
; 5.659 ; 5.875        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[4]                                                ;
; 5.662 ; 5.817        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[5]                   ;
; 5.663 ; 5.818        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[0]                   ;
; 5.663 ; 5.818        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[13]                  ;
; 5.663 ; 5.818        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[14]                  ;
; 5.663 ; 5.818        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[15]                  ;
; 5.663 ; 5.818        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[1]                   ;
; 5.663 ; 5.818        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[2]                   ;
; 5.663 ; 5.818        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[3]                   ;
; 5.663 ; 5.818        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[4]                   ;
; 5.663 ; 5.818        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[7]                   ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                           ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                         ; Clock Edge ; Target                                                                                                                                                                                                                                     ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|generic_ram_infer:freezer_bram|altsyncram:ram_block_rtl_0|altsyncram_jc41:auto_generated|ram_block1a0~porta_address_reg0 ;
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|generic_ram_infer:freezer_bram|altsyncram:ram_block_rtl_0|altsyncram_jc41:auto_generated|ram_block1a0~porta_we_reg       ;
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a11~porta_address_reg0                                                                                                                                      ;
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a17~porta_address_reg0                                                                                                                                      ;
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a1~porta_address_reg0                                                                                                                                       ;
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a21~porta_address_reg0                                                                                                                                      ;
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a23~porta_address_reg0                                                                                                                                      ;
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a3~porta_address_reg0                                                                                                                                       ;
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a4~porta_address_reg0                                                                                                                                       ;
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a6~porta_address_reg0                                                                                                                                       ;
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a8~porta_address_reg0                                                                                                                                       ;
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_9f41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                           ;
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_9f41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                 ;
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_9f41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                           ;
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_9f41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                 ;
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_9f41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                          ;
; 17.367 ; 17.597       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_9f41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                ;
; 17.368 ; 17.598       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                                       ;
; 17.368 ; 17.598       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a5~porta_address_reg0                                                                                                                                       ;
; 17.368 ; 17.598       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_9f41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                            ;
; 17.368 ; 17.598       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_9f41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                  ;
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|generic_ram_infer:freezer_bram|altsyncram:ram_block_rtl_0|altsyncram_jc41:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a7~porta_address_reg0                                                                                                                                       ;
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_9f41:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                            ;
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_9f41:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                            ;
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_9f41:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                           ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a10~porta_address_reg0                                                                                                                                      ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a14~porta_address_reg0                                                                                                                                      ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a20~porta_address_reg0                                                                                                                                      ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a2~porta_address_reg0                                                                                                                                       ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_9f41:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                             ;
; 17.398 ; 17.582       ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[0]                                                                                                                                   ;
; 17.398 ; 17.582       ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[4]                                                                                                                                   ;
; 17.399 ; 17.583       ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                                                                                                                                                                         ;
; 17.401 ; 17.585       ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[3]                                                                                                                                                                                          ;
; 17.402 ; 17.586       ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[4]                                                                                                                                       ;
; 17.405 ; 17.621       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cycleRead                                                                                                          ;
; 17.405 ; 17.621       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cycleRmw                                                                                                           ;
; 17.405 ; 17.621       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cycleStack3                                                                                                        ;
; 17.405 ; 17.621       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cycleStack4                                                                                                        ;
; 17.405 ; 17.621       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theWe                                                                                                                          ;
; 17.405 ; 17.621       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; sdram_reset_n_reg                                                                                                                                                                                                                          ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[10]                                                                                                                                  ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[16]                                                                                                                                  ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[17]                                                                                                                                  ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[18]                                                                                                                                  ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[19]                                                                                                                                  ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[20]                                                                                                                                  ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[21]                                                                                                                                  ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[22]                                                                                                                                  ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[23]                                                                                                                                  ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[9]                                                                                                                                   ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|cart_mode_prev[0]                                                                                                          ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|cart_mode_prev[1]                                                                                                          ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|cart_mode_prev[2]                                                                                                          ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|cart_mode_prev[3]                                                                                                          ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|cart_mode_prev[4]                                                                                                          ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|cart_mode_prev[5]                                                                                                          ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|cfg_bank[20]                                                                                                               ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[11]                                                                                                                            ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[12]                                                                                                                            ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[13]                                                                                                                            ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[14]                                                                                                                            ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[17]                                                                                                                            ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[19]                                                                                                                            ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[1]                                                                                                                             ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[20]                                                                                                                            ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[21]                                                                                                                            ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[22]                                                                                                                            ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[23]                                                                                                                            ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[25]                                                                                                                            ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[28]                                                                                                                            ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[29]                                                                                                                            ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[30]                                                                                                                            ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[31]                                                                                                                            ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[5]                                                                                                                             ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[9]                                                                                                                             ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|ram_bank[13]                                                                                                             ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|ram_bank[14]                                                                                                             ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|ram_bank[15]                                                                                                             ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|rom_bank[13]                                                                                                             ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|rom_bank[14]                                                                                                             ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|rom_bank[15]                                                                                                             ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|cpu_fetch_real_reg                                                                                                                            ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg                                                                                                                                ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|write_enable_reg                                                                                                                              ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                                                                                                                    ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|antic_counter:antic_counter_display_list|value_reg[11]                                                                                                ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|antic_counter:antic_counter_memory_scan|value_reg[12]                                                                                                 ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|antic_counter:antic_counter_memory_scan|value_reg[13]                                                                                                 ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|antic_counter:antic_counter_memory_scan|value_reg[14]                                                                                                 ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|antic_counter:antic_counter_memory_scan|value_reg[15]                                                                                                 ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|display_list_address_low_temp_reg[0]                                                                                                                  ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|display_list_address_low_temp_reg[1]                                                                                                                  ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|display_list_address_low_temp_reg[2]                                                                                                                  ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|display_list_address_low_temp_reg[3]                                                                                                                  ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|display_list_address_low_temp_reg[4]                                                                                                                  ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|display_list_address_low_temp_reg[5]                                                                                                                  ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|display_list_address_low_temp_reg[6]                                                                                                                  ;
; 17.406 ; 17.622       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|display_list_address_low_temp_reg[7]                                                                                                                  ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                   ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                        ; Clock Edge ; Target                                                                                             ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------+
; 17.598 ; 17.598       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.598 ; 17.598       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.598 ; 17.598       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.598 ; 17.598       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 17.612 ; 17.612       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.619 ; 17.619       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.619 ; 17.619       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.623 ; 17.623       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.623 ; 17.623       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.629 ; 17.629       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.644 ; 17.644       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.644 ; 17.644       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.644 ; 17.644       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.644 ; 17.644       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'                                                                                                                        ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------+
; Slack   ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                                                 ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------+
; 99.405  ; 99.405       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 99.405  ; 99.405       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 99.439  ; 99.439       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                       ;
; 99.450  ; 99.450       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 100.000 ; 100.000      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                       ;
; 100.000 ; 100.000      ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                       ;
; 100.549 ; 100.549      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 100.561 ; 100.561      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                       ;
; 100.592 ; 100.592      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 100.592 ; 100.592      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 196.000 ; 200.000      ; 4.000          ; Port Rate        ; FPGA_CLK ; Rise       ; FPGA_CLK                                                                               ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                             ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.495 ; 2.053 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.474 ; 2.032 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.474 ; 2.032 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.474 ; 2.032 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 1.486 ; 2.044 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 1.491 ; 2.049 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 1.489 ; 2.047 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 1.485 ; 2.043 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 1.495 ; 2.053 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 1.487 ; 2.045 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 1.493 ; 2.051 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.493 ; 2.051 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.493 ; 2.051 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.483 ; 2.041 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 1.481 ; 2.039 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.471 ; 2.029 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.481 ; 2.039 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; 2.900 ; 3.311 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; 2.362 ; 2.830 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; 2.014 ; 2.540 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; 1.903 ; 2.394 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; 2.047 ; 2.550 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; 2.900 ; 3.311 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; 3.165 ; 3.563 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; 2.146 ; 2.591 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; 2.300 ; 2.748 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; 2.243 ; 2.729 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; 2.241 ; 2.716 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; 3.165 ; 3.563 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; 3.213 ; 4.026 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; 2.775 ; 3.499 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; 2.135 ; 2.591 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; -1.005 ; -1.563 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; -1.008 ; -1.566 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; -1.008 ; -1.566 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; -1.008 ; -1.566 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; -1.020 ; -1.578 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; -1.025 ; -1.583 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; -1.023 ; -1.581 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; -1.019 ; -1.577 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; -1.029 ; -1.587 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; -1.021 ; -1.579 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; -1.027 ; -1.585 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; -1.027 ; -1.585 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; -1.027 ; -1.585 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; -1.017 ; -1.575 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; -1.015 ; -1.573 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; -1.005 ; -1.563 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; -1.015 ; -1.573 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; -1.405 ; -1.892 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; -1.831 ; -2.281 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; -1.478 ; -1.984 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; -1.405 ; -1.892 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; -1.516 ; -2.007 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; -1.538 ; -2.029 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; -1.638 ; -2.081 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; -1.638 ; -2.081 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; -1.786 ; -2.231 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; -1.719 ; -2.185 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; -1.730 ; -2.202 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; -1.659 ; -2.145 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; -2.660 ; -3.456 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; -2.238 ; -2.951 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; -1.628 ; -2.081 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                     ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 2.588 ; 2.294 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 1.607 ; 1.456 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 1.597 ; 1.446 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 1.597 ; 1.446 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 1.597 ; 1.446 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 1.596 ; 1.445 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 1.604 ; 1.453 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 1.613 ; 1.462 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 2.588 ; 2.294 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 1.615 ; 1.464 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 1.625 ; 1.474 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 1.607 ; 1.456 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 2.582 ; 2.288 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 1.609 ; 1.458 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 2.582 ; 2.288 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 2.594 ; 2.300 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 1.619 ; 1.468 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 2.640 ; 2.362 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 1.753 ; 1.607 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 1.753 ; 1.607 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 1.753 ; 1.607 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 2.627 ; 2.349 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 2.622 ; 2.344 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 1.163 ; 1.075 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 1.685 ; 1.535 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 1.695 ; 1.545 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 1.780 ; 1.634 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 2.640 ; 2.362 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 1.774 ; 1.628 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 1.774 ; 1.628 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 1.764 ; 1.618 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 2.632 ; 2.354 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 1.756 ; 1.610 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 1.766 ; 1.620 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 1.793 ; 1.761 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 1.793 ; 1.761 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 1.430 ; 1.430 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 1.619 ; 1.468 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 1.629 ; 1.478 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 3.963 ; 4.631 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 1.415 ; 1.485 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 1.969 ; 2.083 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 3.591 ; 4.167 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 1.698 ; 1.620 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]        ; FPGA_CLK   ; 5.711 ; 6.461 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]       ; FPGA_CLK   ; 4.503 ; 4.608 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]       ; FPGA_CLK   ; 5.711 ; 6.461 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]       ; FPGA_CLK   ; 4.086 ; 4.298 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]       ; FPGA_CLK   ; 5.584 ; 6.016 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]        ; FPGA_CLK   ; 5.602 ; 6.102 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]       ; FPGA_CLK   ; 5.602 ; 6.102 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]       ; FPGA_CLK   ; 4.065 ; 4.116 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]       ; FPGA_CLK   ; 3.746 ; 3.851 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]       ; FPGA_CLK   ; 3.408 ; 3.534 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS          ; FPGA_CLK   ; 5.264 ; 4.674 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]        ; FPGA_CLK   ; 4.398 ; 4.485 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]       ; FPGA_CLK   ; 3.924 ; 3.963 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]       ; FPGA_CLK   ; 4.398 ; 4.485 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]       ; FPGA_CLK   ; 3.963 ; 4.031 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]       ; FPGA_CLK   ; 3.962 ; 3.970 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS          ; FPGA_CLK   ; 1.088 ; 1.054 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 8.368 ;       ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 8.315 ; Fall       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                             ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 1.178 ; 1.029 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 1.189 ; 1.040 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 1.179 ; 1.030 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 1.179 ; 1.030 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 1.179 ; 1.030 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 1.178 ; 1.029 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 1.186 ; 1.037 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 1.195 ; 1.046 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 2.192 ; 1.898 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 1.197 ; 1.048 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 1.207 ; 1.058 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 1.189 ; 1.040 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 1.191 ; 1.042 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 1.191 ; 1.042 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 2.186 ; 1.892 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 2.198 ; 1.904 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 1.201 ; 1.052 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 0.768 ; 0.680 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 1.334 ; 1.190 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 1.334 ; 1.190 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 1.334 ; 1.190 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 2.232 ; 1.954 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 2.227 ; 1.949 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 0.768 ; 0.680 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 1.266 ; 1.118 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 1.276 ; 1.128 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 1.361 ; 1.217 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 2.245 ; 1.967 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 1.355 ; 1.211 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 1.355 ; 1.211 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 1.345 ; 1.201 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 2.237 ; 1.959 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 1.337 ; 1.193 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 1.347 ; 1.203 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 1.020 ; 1.024 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 1.368 ; 1.341 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 1.020 ; 1.024 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 1.201 ; 1.052 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 1.211 ; 1.062 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 3.530 ; 4.190 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 1.019 ; 1.088 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 1.541 ; 1.649 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 3.168 ; 3.740 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 1.280 ; 1.206 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]        ; FPGA_CLK   ; 2.135 ; 2.261 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]       ; FPGA_CLK   ; 2.271 ; 2.358 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]       ; FPGA_CLK   ; 3.803 ; 4.338 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]       ; FPGA_CLK   ; 2.135 ; 2.261 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]       ; FPGA_CLK   ; 3.836 ; 4.478 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]        ; FPGA_CLK   ; 1.975 ; 1.992 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]       ; FPGA_CLK   ; 3.734 ; 4.225 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]       ; FPGA_CLK   ; 1.975 ; 1.992 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]       ; FPGA_CLK   ; 2.069 ; 2.091 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]       ; FPGA_CLK   ; 1.992 ; 2.144 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS          ; FPGA_CLK   ; 4.073 ; 3.506 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]        ; FPGA_CLK   ; 2.019 ; 2.070 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]       ; FPGA_CLK   ; 2.125 ; 2.167 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]       ; FPGA_CLK   ; 2.019 ; 2.070 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]       ; FPGA_CLK   ; 2.298 ; 2.338 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]       ; FPGA_CLK   ; 2.273 ; 2.303 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS          ; FPGA_CLK   ; 0.692 ; 0.658 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 7.995 ;       ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 7.941 ; Fall       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.154 ; 2.127 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.184 ; 2.157 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.184 ; 2.157 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.184 ; 2.157 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.394 ; 2.367 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.587 ; 2.560 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.598 ; 2.571 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.601 ; 2.574 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.678 ; 2.651 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.515 ; 2.488 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.356 ; 2.329 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.190 ; 2.163 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.190 ; 2.163 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.180 ; 2.153 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.164 ; 2.137 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.154 ; 2.127 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.164 ; 2.137 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.271 ; 2.895 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                             ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 0.853 ; 0.853 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 0.883 ; 0.883 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 0.883 ; 0.883 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 0.883 ; 0.883 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 1.084 ; 1.084 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 1.270 ; 1.270 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 1.280 ; 1.280 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 1.284 ; 1.284 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 1.358 ; 1.358 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 1.201 ; 1.201 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 1.049 ; 1.049 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 0.889 ; 0.889 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 0.889 ; 0.889 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 0.879 ; 0.879 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 0.863 ; 0.863 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 0.853 ; 0.853 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 0.863 ; 0.863 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.738 ; 2.377 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                            ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.220     ; 2.220     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.248     ; 2.248     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.248     ; 2.248     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.248     ; 2.248     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.482     ; 2.482     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.684     ; 2.684     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.700     ; 2.700     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.717     ; 2.717     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.812     ; 2.812     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.609     ; 2.609     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.435     ; 2.435     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.250     ; 2.250     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.250     ; 2.250     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.240     ; 2.240     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.230     ; 2.230     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.220     ; 2.220     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.230     ; 2.230     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.049     ; 3.425     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                                    ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 0.917     ; 1.034     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 0.944     ; 1.061     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 0.944     ; 1.061     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 0.944     ; 1.061     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 1.169     ; 1.286     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 1.363     ; 1.480     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 1.378     ; 1.495     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 1.394     ; 1.511     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 1.486     ; 1.603     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 1.291     ; 1.408     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 1.124     ; 1.241     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 0.947     ; 1.064     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 0.947     ; 1.064     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 0.937     ; 1.054     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 0.927     ; 1.044     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 0.917     ; 1.034     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 0.927     ; 1.044     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.525     ; 2.886     ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------+


---------------------------------------------
; Fast 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary                                                                                                        ;
+--------------------------------------------------------------------------------+--------+-------+----------+---------+---------------------+
; Clock                                                                          ; Setup  ; Hold  ; Recovery ; Removal ; Minimum Pulse Width ;
+--------------------------------------------------------------------------------+--------+-------+----------+---------+---------------------+
; Worst-case Slack                                                               ; -1.087 ; 0.178 ; 5.267    ; 0.986   ; 5.532               ;
;  FPGA_CLK                                                                      ; N/A    ; N/A   ; N/A      ; N/A     ; 99.405              ;
;  \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -1.087 ; 0.181 ; 7.731    ; 0.986   ; 5.532               ;
;  \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 2.861  ; 0.178 ; 5.267    ; 1.720   ; 17.272              ;
;  \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]  ; N/A    ; N/A   ; N/A      ; N/A     ; 17.584              ;
; Design-wide TNS                                                                ; -6.454 ; 0.0   ; 0.0      ; 0.0     ; 0.0                 ;
;  FPGA_CLK                                                                      ; N/A    ; N/A   ; N/A      ; N/A     ; 0.000               ;
;  \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; -6.454 ; 0.000 ; 0.000    ; 0.000   ; 0.000               ;
;  \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000  ; 0.000 ; 0.000    ; 0.000   ; 0.000               ;
;  \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]  ; N/A    ; N/A   ; N/A      ; N/A     ; 0.000               ;
+--------------------------------------------------------------------------------+--------+-------+----------+---------+---------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                             ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 3.046 ; 3.153 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.025 ; 3.132 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.025 ; 3.132 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.025 ; 3.132 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.036 ; 3.143 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.040 ; 3.147 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.038 ; 3.145 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.034 ; 3.141 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.046 ; 3.153 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.032 ; 3.139 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.036 ; 3.143 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.036 ; 3.143 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.036 ; 3.143 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.026 ; 3.133 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 3.024 ; 3.131 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 3.014 ; 3.121 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 3.024 ; 3.131 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; 5.841 ; 6.163 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; 4.788 ; 5.026 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; 4.106 ; 4.367 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; 3.866 ; 4.062 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; 4.172 ; 4.382 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; 5.841 ; 6.163 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; 6.428 ; 6.805 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; 4.218 ; 4.394 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; 4.607 ; 4.792 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; 4.560 ; 4.798 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; 4.473 ; 4.762 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; 6.428 ; 6.805 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; 6.695 ; 6.984 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; 5.667 ; 5.990 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; 4.278 ; 4.492 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                               ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; -1.005 ; -1.563 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; -1.008 ; -1.566 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; -1.008 ; -1.566 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; -1.008 ; -1.566 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; -1.020 ; -1.578 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; -1.025 ; -1.583 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; -1.023 ; -1.581 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; -1.019 ; -1.577 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; -1.029 ; -1.587 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; -1.021 ; -1.579 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; -1.027 ; -1.585 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; -1.027 ; -1.585 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; -1.027 ; -1.585 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; -1.017 ; -1.575 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; -1.015 ; -1.573 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; -1.005 ; -1.563 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; -1.015 ; -1.573 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; -1.405 ; -1.892 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; -1.831 ; -2.281 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; -1.478 ; -1.984 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; -1.405 ; -1.892 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; -1.516 ; -2.007 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; -1.538 ; -2.029 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; -1.638 ; -2.081 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; -1.638 ; -2.081 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; -1.786 ; -2.231 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; -1.719 ; -2.185 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; -1.730 ; -2.202 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; -1.659 ; -2.145 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; -2.660 ; -3.456 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; -2.238 ; -2.951 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; -1.628 ; -2.081 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                       ;
+-----------------+------------+--------+--------+------------+-------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                               ;
+-----------------+------------+--------+--------+------------+-------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 4.590  ; 4.140  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 3.323  ; 3.087  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 3.313  ; 3.077  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 3.313  ; 3.077  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 3.313  ; 3.077  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 3.317  ; 3.081  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 3.326  ; 3.090  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 3.335  ; 3.099  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 4.590  ; 4.140  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 3.336  ; 3.100  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 3.346  ; 3.110  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 3.323  ; 3.087  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 4.578  ; 4.128  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 3.325  ; 3.089  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 4.578  ; 4.128  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 4.590  ; 4.140  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 3.335  ; 3.099  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 4.657  ; 4.209  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 3.607  ; 3.350  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 3.607  ; 3.350  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 3.607  ; 3.350  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 4.637  ; 4.189  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 4.633  ; 4.185  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 2.563  ; 2.365  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 3.507  ; 3.264  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 3.519  ; 3.276  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 3.639  ; 3.382  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 4.657  ; 4.209  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 3.633  ; 3.376  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 3.633  ; 3.376  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 3.623  ; 3.366  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 4.648  ; 4.200  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 3.614  ; 3.357  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 3.624  ; 3.367  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 3.648  ; 3.993  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 3.648  ; 3.993  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 3.012  ; 3.302  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 3.335  ; 3.099  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 3.345  ; 3.109  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 7.899  ; 7.919  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 3.123  ; 3.087  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 4.544  ; 4.226  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 6.978  ; 7.102  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 3.526  ; 3.802  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]        ; FPGA_CLK   ; 11.927 ; 11.996 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]       ; FPGA_CLK   ; 10.040 ; 9.901  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]       ; FPGA_CLK   ; 11.927 ; 11.996 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]       ; FPGA_CLK   ; 9.345  ; 9.019  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]       ; FPGA_CLK   ; 11.131 ; 11.421 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]        ; FPGA_CLK   ; 11.306 ; 11.485 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]       ; FPGA_CLK   ; 11.306 ; 11.485 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]       ; FPGA_CLK   ; 9.184  ; 8.904  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]       ; FPGA_CLK   ; 8.549  ; 8.351  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]       ; FPGA_CLK   ; 7.747  ; 7.380  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS          ; FPGA_CLK   ; 9.228  ; 9.205  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]        ; FPGA_CLK   ; 9.794  ; 9.496  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]       ; FPGA_CLK   ; 8.957  ; 8.709  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]       ; FPGA_CLK   ; 9.794  ; 9.496  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]       ; FPGA_CLK   ; 8.931  ; 8.536  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]       ; FPGA_CLK   ; 8.791  ; 8.493  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS          ; FPGA_CLK   ; 2.486  ; 2.369  ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 9.375  ;        ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;        ; 9.104  ; Fall       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+-----------------+------------+--------+--------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                             ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                               ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 1.178 ; 1.029 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 1.189 ; 1.040 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 1.179 ; 1.030 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 1.179 ; 1.030 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 1.179 ; 1.030 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 1.178 ; 1.029 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 1.186 ; 1.037 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 1.195 ; 1.046 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 2.192 ; 1.898 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 1.197 ; 1.048 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 1.207 ; 1.058 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 1.189 ; 1.040 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 1.191 ; 1.042 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 1.191 ; 1.042 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 2.186 ; 1.892 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 2.198 ; 1.904 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 1.201 ; 1.052 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 0.768 ; 0.680 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 1.334 ; 1.190 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 1.334 ; 1.190 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 1.334 ; 1.190 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 2.232 ; 1.954 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 2.227 ; 1.949 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 0.768 ; 0.680 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 1.266 ; 1.118 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 1.276 ; 1.128 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 1.361 ; 1.217 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 2.245 ; 1.967 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 1.355 ; 1.211 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 1.355 ; 1.211 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 1.345 ; 1.201 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 2.237 ; 1.959 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 1.337 ; 1.193 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 1.347 ; 1.203 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 1.020 ; 1.024 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 1.368 ; 1.341 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 1.020 ; 1.024 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 1.201 ; 1.052 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 1.211 ; 1.062 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 3.530 ; 4.190 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 1.019 ; 1.088 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 1.541 ; 1.649 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 3.168 ; 3.740 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 1.280 ; 1.206 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]        ; FPGA_CLK   ; 2.135 ; 2.261 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]       ; FPGA_CLK   ; 2.271 ; 2.358 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]       ; FPGA_CLK   ; 3.803 ; 4.338 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]       ; FPGA_CLK   ; 2.135 ; 2.261 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]       ; FPGA_CLK   ; 3.836 ; 4.478 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]        ; FPGA_CLK   ; 1.975 ; 1.992 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]       ; FPGA_CLK   ; 3.734 ; 4.225 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]       ; FPGA_CLK   ; 1.975 ; 1.992 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]       ; FPGA_CLK   ; 2.069 ; 2.091 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]       ; FPGA_CLK   ; 1.992 ; 2.144 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS          ; FPGA_CLK   ; 4.073 ; 3.506 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]        ; FPGA_CLK   ; 2.019 ; 2.070 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]       ; FPGA_CLK   ; 2.125 ; 2.167 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]       ; FPGA_CLK   ; 2.019 ; 2.070 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]       ; FPGA_CLK   ; 2.298 ; 2.338 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]       ; FPGA_CLK   ; 2.273 ; 2.303 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS          ; FPGA_CLK   ; 0.692 ; 0.658 ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 7.995 ;       ; Rise       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 7.941 ; Fall       ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                     ;
+----------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; Pin            ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
+----------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; VGA_VS         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_HS         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[0]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[1]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[2]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[3]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[0]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[1]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[2]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[3]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[0]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[1]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[2]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[3]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; AUDIO_L        ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; AUDIO_R        ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_BA[0]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_BA[1]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_CS_N     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_RAS_N    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_CAS_N    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_WE_N     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQM_n[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQM_n[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_CLK      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[0]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[1]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[2]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[3]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[4]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[5]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[6]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[7]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[8]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[9]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[10]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[11]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[12]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SD_CLK         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SD_CMD         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SD_DAT3        ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[0]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[1]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[2]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[3]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[4]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[5]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[6]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[7]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[8]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[9]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[10]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[11]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[12]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[13]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[14]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[15]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+----------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+


+-----------------------------------------------------------------+
; Input Transition Times                                          ;
+--------------+--------------+-----------------+-----------------+
; Pin          ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+--------------+--------------+-----------------+-----------------+
; PS2M_CLK     ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; PS2M_DAT     ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY1_n[5]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY2_n[5]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[0]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[1]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[2]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[3]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[4]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[5]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[6]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[7]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[8]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[9]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[10] ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[11] ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[12] ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[13] ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[14] ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[15] ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; FPGA_CLK     ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY1_n[4]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY2_n[4]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY2_n[1]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY1_n[2]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY1_n[0]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY1_n[1]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY1_n[3]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY2_n[3]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY2_n[0]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY2_n[2]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SD_DAT0      ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; PS2K_CLK     ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; PS2K_DAT     ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
+--------------+--------------+-----------------+-----------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin            ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; VGA_VS         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_HS         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.00154 V          ; 0.08 V                               ; 0.145 V                              ; 7.32e-09 s                  ; 7.58e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.00154 V         ; 0.08 V                              ; 0.145 V                             ; 7.32e-09 s                 ; 7.58e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[0]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.46e-07 V                   ; 3.09 V              ; -0.011 V            ; 0.146 V                              ; 0.189 V                              ; 1.76e-09 s                  ; 1.77e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.46e-07 V                  ; 3.09 V             ; -0.011 V           ; 0.146 V                             ; 0.189 V                             ; 1.76e-09 s                 ; 1.77e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[1]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.46e-07 V                   ; 3.08 V              ; -0.00108 V          ; 0.089 V                              ; 0.161 V                              ; 7.68e-09 s                  ; 7.97e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.46e-07 V                  ; 3.08 V             ; -0.00108 V         ; 0.089 V                             ; 0.161 V                             ; 7.68e-09 s                 ; 7.97e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[2]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.46e-07 V                   ; 3.09 V              ; -0.013 V            ; 0.091 V                              ; 0.178 V                              ; 1.33e-09 s                  ; 1.36e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.46e-07 V                  ; 3.09 V             ; -0.013 V           ; 0.091 V                             ; 0.178 V                             ; 1.33e-09 s                 ; 1.36e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[3]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.46e-07 V                   ; 3.08 V              ; -0.00108 V          ; 0.089 V                              ; 0.161 V                              ; 7.68e-09 s                  ; 7.97e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.46e-07 V                  ; 3.08 V             ; -0.00108 V         ; 0.089 V                             ; 0.161 V                             ; 7.68e-09 s                 ; 7.97e-09 s                 ; Yes                       ; Yes                       ;
; VGA_G[0]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.00154 V          ; 0.08 V                               ; 0.145 V                              ; 7.32e-09 s                  ; 7.58e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.00154 V         ; 0.08 V                              ; 0.145 V                             ; 7.32e-09 s                 ; 7.58e-09 s                 ; Yes                       ; Yes                       ;
; VGA_G[1]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_G[2]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_G[3]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_R[0]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_R[1]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_R[2]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_R[3]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; AUDIO_L        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.46e-07 V                   ; 3.08 V              ; -0.00108 V          ; 0.089 V                              ; 0.161 V                              ; 7.68e-09 s                  ; 7.97e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.46e-07 V                  ; 3.08 V             ; -0.00108 V         ; 0.089 V                             ; 0.161 V                             ; 7.68e-09 s                 ; 7.97e-09 s                 ; Yes                       ; Yes                       ;
; AUDIO_R        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.46e-07 V                   ; 3.09 V              ; -0.011 V            ; 0.146 V                              ; 0.189 V                              ; 1.76e-09 s                  ; 1.77e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.46e-07 V                  ; 3.09 V             ; -0.011 V           ; 0.146 V                             ; 0.189 V                             ; 1.76e-09 s                 ; 1.77e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_BA[0]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_BA[1]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.08 V              ; -0.00469 V          ; 0.309 V                              ; 0.24 V                               ; 5.8e-09 s                   ; 4.65e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.08 V             ; -0.00469 V         ; 0.309 V                             ; 0.24 V                              ; 5.8e-09 s                  ; 4.65e-09 s                 ; No                        ; Yes                       ;
; SDRAM_CS_N     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_RAS_N    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_CAS_N    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.08 V              ; -0.00469 V          ; 0.309 V                              ; 0.24 V                               ; 5.8e-09 s                   ; 4.65e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.08 V             ; -0.00469 V         ; 0.309 V                             ; 0.24 V                              ; 5.8e-09 s                  ; 4.65e-09 s                 ; No                        ; Yes                       ;
; SDRAM_WE_N     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQM_n[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQM_n[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_CLK      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[6]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[7]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.08 V              ; -0.00469 V          ; 0.309 V                              ; 0.24 V                               ; 5.8e-09 s                   ; 4.65e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.08 V             ; -0.00469 V         ; 0.309 V                             ; 0.24 V                              ; 5.8e-09 s                  ; 4.65e-09 s                 ; No                        ; Yes                       ;
; SDRAM_A[8]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[9]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[10]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[11]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[12]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.08 V              ; -0.00469 V          ; 0.309 V                              ; 0.24 V                               ; 5.8e-09 s                   ; 4.65e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.08 V             ; -0.00469 V         ; 0.309 V                             ; 0.24 V                              ; 5.8e-09 s                  ; 4.65e-09 s                 ; No                        ; Yes                       ;
; SD_CLK         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; SD_CMD         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.00154 V          ; 0.08 V                               ; 0.145 V                              ; 7.32e-09 s                  ; 7.58e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.00154 V         ; 0.08 V                              ; 0.145 V                             ; 7.32e-09 s                 ; 7.58e-09 s                 ; Yes                       ; Yes                       ;
; SD_DAT3        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[0]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[1]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[2]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[3]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.08 V              ; -0.00384 V          ; 0.283 V                              ; 0.244 V                              ; 6.17e-09 s                  ; 4.9e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.08 V             ; -0.00384 V         ; 0.283 V                             ; 0.244 V                             ; 6.17e-09 s                 ; 4.9e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[4]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.08 V              ; -0.00384 V          ; 0.283 V                              ; 0.244 V                              ; 6.17e-09 s                  ; 4.9e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.08 V             ; -0.00384 V         ; 0.283 V                             ; 0.244 V                             ; 6.17e-09 s                 ; 4.9e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[5]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[6]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.12 V              ; -0.0417 V           ; 0.221 V                              ; 0.245 V                              ; 1.09e-09 s                  ; 8.59e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.12 V             ; -0.0417 V          ; 0.221 V                             ; 0.245 V                             ; 1.09e-09 s                 ; 8.59e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[7]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.12 V              ; -0.0417 V           ; 0.221 V                              ; 0.245 V                              ; 1.09e-09 s                  ; 8.59e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.12 V             ; -0.0417 V          ; 0.221 V                             ; 0.245 V                             ; 1.09e-09 s                 ; 8.59e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[8]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[9]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.08 V              ; -0.00384 V          ; 0.283 V                              ; 0.244 V                              ; 6.17e-09 s                  ; 4.9e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.08 V             ; -0.00384 V         ; 0.283 V                             ; 0.244 V                             ; 6.17e-09 s                 ; 4.9e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[10]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[11]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[12]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[13]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.08 V              ; -0.00384 V          ; 0.283 V                              ; 0.244 V                              ; 6.17e-09 s                  ; 4.9e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.08 V             ; -0.00384 V         ; 0.283 V                             ; 0.244 V                             ; 6.17e-09 s                 ; 4.9e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[14]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[15]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin            ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; VGA_VS         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_HS         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.47 V              ; -0.0076 V           ; 0.323 V                              ; 0.334 V                              ; 4.77e-09 s                  ; 5.17e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 3.1e-07 V                   ; 3.47 V             ; -0.0076 V          ; 0.323 V                             ; 0.334 V                             ; 4.77e-09 s                 ; 5.17e-09 s                 ; No                        ; No                        ;
; VGA_B[0]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.1e-07 V                    ; 3.51 V              ; -0.0419 V           ; 0.296 V                              ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.1e-07 V                   ; 3.51 V             ; -0.0419 V          ; 0.296 V                             ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; VGA_B[1]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.1e-07 V                    ; 3.47 V              ; -0.00709 V          ; 0.326 V                              ; 0.34 V                               ; 5.02e-09 s                  ; 5.43e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.1e-07 V                   ; 3.47 V             ; -0.00709 V         ; 0.326 V                             ; 0.34 V                              ; 5.02e-09 s                 ; 5.43e-09 s                 ; No                        ; No                        ;
; VGA_B[2]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.1e-07 V                    ; 3.52 V              ; -0.0514 V           ; 0.253 V                              ; 0.324 V                              ; 8.77e-10 s                  ; 8.98e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 2.1e-07 V                   ; 3.52 V             ; -0.0514 V          ; 0.253 V                             ; 0.324 V                             ; 8.77e-10 s                 ; 8.98e-10 s                 ; No                        ; No                        ;
; VGA_B[3]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.1e-07 V                    ; 3.47 V              ; -0.00709 V          ; 0.326 V                              ; 0.34 V                               ; 5.02e-09 s                  ; 5.43e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.1e-07 V                   ; 3.47 V             ; -0.00709 V         ; 0.326 V                             ; 0.34 V                              ; 5.02e-09 s                 ; 5.43e-09 s                 ; No                        ; No                        ;
; VGA_G[0]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.47 V              ; -0.0076 V           ; 0.323 V                              ; 0.334 V                              ; 4.77e-09 s                  ; 5.17e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 3.1e-07 V                   ; 3.47 V             ; -0.0076 V          ; 0.323 V                             ; 0.334 V                             ; 4.77e-09 s                 ; 5.17e-09 s                 ; No                        ; No                        ;
; VGA_G[1]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_G[2]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_G[3]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_R[0]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_R[1]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_R[2]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_R[3]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; AUDIO_L        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.1e-07 V                    ; 3.47 V              ; -0.00709 V          ; 0.326 V                              ; 0.34 V                               ; 5.02e-09 s                  ; 5.43e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.1e-07 V                   ; 3.47 V             ; -0.00709 V         ; 0.326 V                             ; 0.34 V                              ; 5.02e-09 s                 ; 5.43e-09 s                 ; No                        ; No                        ;
; AUDIO_R        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.1e-07 V                    ; 3.51 V              ; -0.0419 V           ; 0.296 V                              ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.1e-07 V                   ; 3.51 V             ; -0.0419 V          ; 0.296 V                             ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; SDRAM_BA[0]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_BA[1]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.48 V              ; -0.0142 V           ; 0.362 V                              ; 0.291 V                              ; 3.89e-09 s                  ; 3.25e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.9e-07 V                   ; 3.48 V             ; -0.0142 V          ; 0.362 V                             ; 0.291 V                             ; 3.89e-09 s                 ; 3.25e-09 s                 ; No                        ; No                        ;
; SDRAM_CS_N     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_RAS_N    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_CAS_N    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.48 V              ; -0.0142 V           ; 0.362 V                              ; 0.291 V                              ; 3.89e-09 s                  ; 3.25e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.9e-07 V                   ; 3.48 V             ; -0.0142 V          ; 0.362 V                             ; 0.291 V                             ; 3.89e-09 s                 ; 3.25e-09 s                 ; No                        ; No                        ;
; SDRAM_WE_N     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_DQM_n[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_DQM_n[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_CLK      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[6]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[7]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.48 V              ; -0.0142 V           ; 0.362 V                              ; 0.291 V                              ; 3.89e-09 s                  ; 3.25e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.9e-07 V                   ; 3.48 V             ; -0.0142 V          ; 0.362 V                             ; 0.291 V                             ; 3.89e-09 s                 ; 3.25e-09 s                 ; No                        ; No                        ;
; SDRAM_A[8]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[9]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[10]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[11]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[12]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.48 V              ; -0.0142 V           ; 0.362 V                              ; 0.291 V                              ; 3.89e-09 s                  ; 3.25e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.9e-07 V                   ; 3.48 V             ; -0.0142 V          ; 0.362 V                             ; 0.291 V                             ; 3.89e-09 s                 ; 3.25e-09 s                 ; No                        ; No                        ;
; SD_CLK         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SD_CMD         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.47 V              ; -0.0076 V           ; 0.323 V                              ; 0.334 V                              ; 4.77e-09 s                  ; 5.17e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 3.1e-07 V                   ; 3.47 V             ; -0.0076 V          ; 0.323 V                             ; 0.334 V                             ; 4.77e-09 s                 ; 5.17e-09 s                 ; No                        ; No                        ;
; SD_DAT3        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[0]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[1]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[2]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[3]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.48 V              ; -0.0136 V           ; 0.352 V                              ; 0.346 V                              ; 4.12e-09 s                  ; 3.34e-09 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.48 V             ; -0.0136 V          ; 0.352 V                             ; 0.346 V                             ; 4.12e-09 s                 ; 3.34e-09 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[4]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.48 V              ; -0.0136 V           ; 0.352 V                              ; 0.346 V                              ; 4.12e-09 s                  ; 3.34e-09 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.48 V             ; -0.0136 V          ; 0.352 V                             ; 0.346 V                             ; 4.12e-09 s                 ; 3.34e-09 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[5]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[6]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.57 V              ; -0.0645 V           ; 0.332 V                              ; 0.165 V                              ; 6.78e-10 s                  ; 6.19e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.57 V             ; -0.0645 V          ; 0.332 V                             ; 0.165 V                             ; 6.78e-10 s                 ; 6.19e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[7]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.57 V              ; -0.0645 V           ; 0.332 V                              ; 0.165 V                              ; 6.78e-10 s                  ; 6.19e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.57 V             ; -0.0645 V          ; 0.332 V                             ; 0.165 V                             ; 6.78e-10 s                 ; 6.19e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[8]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[9]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.48 V              ; -0.0136 V           ; 0.352 V                              ; 0.346 V                              ; 4.12e-09 s                  ; 3.34e-09 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.48 V             ; -0.0136 V          ; 0.352 V                             ; 0.346 V                             ; 4.12e-09 s                 ; 3.34e-09 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[10]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[11]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[12]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[13]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.48 V              ; -0.0136 V           ; 0.352 V                              ; 0.346 V                              ; 4.12e-09 s                  ; 3.34e-09 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.48 V             ; -0.0136 V          ; 0.352 V                             ; 0.346 V                             ; 4.12e-09 s                 ; 3.34e-09 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[14]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[15]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Transfers                                                                                                                                                                                           ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                                    ; To Clock                                                                      ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------+----------+----------+----------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1886     ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 135732   ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8302     ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 21750754 ; 0        ; 0        ; 0        ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Transfers                                                                                                                                                                                            ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                                    ; To Clock                                                                      ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------+----------+----------+----------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1886     ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 135732   ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8302     ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 21750754 ; 0        ; 0        ; 0        ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Recovery Transfers                                                                                                                                                                                        ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                                    ; To Clock                                                                      ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------+----------+----------+----------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 146      ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 508      ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 2359     ; 0        ; 0        ; 0        ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Removal Transfers                                                                                                                                                                                         ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                                    ; To Clock                                                                      ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------+----------+----------+----------+
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 146      ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 508      ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 2359     ; 0        ; 0        ; 0        ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design


---------------
; Report RSKM ;
---------------
No dedicated SERDES Receiver circuitry present in device or used in design


+------------------------------------------------+
; Unconstrained Paths                            ;
+---------------------------------+-------+------+
; Property                        ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks                  ; 0     ; 0    ;
; Unconstrained Clocks            ; 0     ; 0    ;
; Unconstrained Input Ports       ; 29    ; 29   ;
; Unconstrained Input Port Paths  ; 61    ; 61   ;
; Unconstrained Output Ports      ; 55    ; 55   ;
; Unconstrained Output Port Paths ; 157   ; 157  ;
+---------------------------------+-------+------+


+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II 32-bit TimeQuest Timing Analyzer
    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
    Info: Processing started: Sat Nov  1 22:40:41 2014
Info: Command: quartus_sta atari800core -c atari800core
Info: qsta_default_script.tcl version: #1
Info (11104): Parallel Compilation has detected 4 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 2 of the 2 physical processors detected instead.
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (332104): Reading SDC File: 'atari800core.sdc'
Info (332110): Deriving PLL clocks
    Info (332110): create_generated_clock -source {\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 3 -duty_cycle 50.00 -name {\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]} {\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]}
    Info (332110): create_generated_clock -source {\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]} -duty_cycle 50.00 -name {\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]} {\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]}
    Info (332110): create_generated_clock -source {\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 3 -phase 234.00 -duty_cycle 50.00 -name {\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]} {\gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]}
    Info (332110): create_generated_clock -source {\gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 40 -multiply_by 227 -duty_cycle 50.00 -name {\gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]} {\gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0]}
Info (332151): Clock uncertainty is not calculated until you update the timing netlist.
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Analyzing Slow 1200mV 85C Model
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -1.087
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -1.087        -6.454 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     2.861         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
Info (332146): Worst-case hold slack is 0.437
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.437         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.453         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
Info (332146): Worst-case recovery slack is 5.267
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     5.267         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     7.731         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case removal slack is 2.154
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     2.154         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     3.646         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
Info (332146): Worst-case minimum pulse width slack is 5.544
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     5.544         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    17.297         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    17.584         0.000 \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    99.862         0.000 FPGA_CLK 
Info: Analyzing Slow 1200mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -0.402
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -0.402        -0.874 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     3.355         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
Info (332146): Worst-case hold slack is 0.387
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.387         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.402         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
Info (332146): Worst-case recovery slack is 5.816
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     5.816         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     8.123         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case removal slack is 1.923
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     1.923         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     3.282         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
Info (332146): Worst-case minimum pulse width slack is 5.532
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     5.532         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    17.272         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    17.587         0.000 \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    99.837         0.000 FPGA_CLK 
Info: Analyzing Fast 1200mV 0C Model
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info (332146): Worst-case setup slack is 6.173
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     6.173         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     7.918         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
Info (332146): Worst-case hold slack is 0.178
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.178         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.181         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case recovery slack is 8.824
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     8.824         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     9.903         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case removal slack is 0.986
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.986         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     1.720         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
Info (332146): Worst-case minimum pulse width slack is 5.658
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     5.658         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    17.367         0.000 \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    17.598         0.000 \gen_real_pll:gen_tv_pal:mcc_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    99.405         0.000 FPGA_CLK 
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Peak virtual memory: 529 megabytes
    Info: Processing ended: Sat Nov  1 22:41:07 2014
    Info: Elapsed time: 00:00:26
    Info: Total CPU time (on all processors): 00:00:29


