TimeQuest Timing Analyzer report for atari800core
Sat Aug  2 12:36:39 2014
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Parallel Compilation
  4. SDC File List
  5. Clocks
  6. Slow 1200mV 85C Model Fmax Summary
  7. Timing Closure Recommendations
  8. Slow 1200mV 85C Model Setup Summary
  9. Slow 1200mV 85C Model Hold Summary
 10. Slow 1200mV 85C Model Recovery Summary
 11. Slow 1200mV 85C Model Removal Summary
 12. Slow 1200mV 85C Model Minimum Pulse Width Summary
 13. Slow 1200mV 85C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 14. Slow 1200mV 85C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 15. Slow 1200mV 85C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'
 16. Slow 1200mV 85C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 17. Slow 1200mV 85C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'
 18. Slow 1200mV 85C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 19. Slow 1200mV 85C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 20. Slow 1200mV 85C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 21. Slow 1200mV 85C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'
 22. Slow 1200mV 85C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 23. Slow 1200mV 85C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'
 24. Slow 1200mV 85C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 25. Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 26. Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'
 27. Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 28. Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]'
 29. Slow 1200mV 85C Model Minimum Pulse Width: 'FPGA_CLK'
 30. Setup Times
 31. Hold Times
 32. Clock to Output Times
 33. Minimum Clock to Output Times
 34. Output Enable Times
 35. Minimum Output Enable Times
 36. Output Disable Times
 37. Minimum Output Disable Times
 38. Slow 1200mV 85C Model Metastability Report
 39. Slow 1200mV 0C Model Fmax Summary
 40. Slow 1200mV 0C Model Setup Summary
 41. Slow 1200mV 0C Model Hold Summary
 42. Slow 1200mV 0C Model Recovery Summary
 43. Slow 1200mV 0C Model Removal Summary
 44. Slow 1200mV 0C Model Minimum Pulse Width Summary
 45. Slow 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 46. Slow 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 47. Slow 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'
 48. Slow 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 49. Slow 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 50. Slow 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'
 51. Slow 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 52. Slow 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 53. Slow 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'
 54. Slow 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 55. Slow 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'
 56. Slow 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 57. Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 58. Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'
 59. Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 60. Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]'
 61. Slow 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'
 62. Setup Times
 63. Hold Times
 64. Clock to Output Times
 65. Minimum Clock to Output Times
 66. Output Enable Times
 67. Minimum Output Enable Times
 68. Output Disable Times
 69. Minimum Output Disable Times
 70. Slow 1200mV 0C Model Metastability Report
 71. Fast 1200mV 0C Model Setup Summary
 72. Fast 1200mV 0C Model Hold Summary
 73. Fast 1200mV 0C Model Recovery Summary
 74. Fast 1200mV 0C Model Removal Summary
 75. Fast 1200mV 0C Model Minimum Pulse Width Summary
 76. Fast 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 77. Fast 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 78. Fast 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'
 79. Fast 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 80. Fast 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'
 81. Fast 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 82. Fast 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 83. Fast 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 84. Fast 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'
 85. Fast 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 86. Fast 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'
 87. Fast 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 88. Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 89. Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'
 90. Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 91. Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]'
 92. Fast 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'
 93. Setup Times
 94. Hold Times
 95. Clock to Output Times
 96. Minimum Clock to Output Times
 97. Output Enable Times
 98. Minimum Output Enable Times
 99. Output Disable Times
100. Minimum Output Disable Times
101. Fast 1200mV 0C Model Metastability Report
102. Multicorner Timing Analysis Summary
103. Setup Times
104. Hold Times
105. Clock to Output Times
106. Minimum Clock to Output Times
107. Board Trace Model Assignments
108. Input Transition Times
109. Slow Corner Signal Integrity Metrics
110. Fast Corner Signal Integrity Metrics
111. Setup Transfers
112. Hold Transfers
113. Recovery Transfers
114. Removal Transfers
115. Report TCCS
116. Report RSKM
117. Unconstrained Paths
118. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
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Your use of Altera Corporation's design tools, logic functions 
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(including device programming or simulation files), and any 
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without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                                      ;
+--------------------+-------------------------------------------------------------------+
; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ;
; Revision Name      ; atari800core                                                      ;
; Device Family      ; Cyclone III                                                       ;
; Device Name        ; EP3C16E144C8                                                      ;
; Timing Models      ; Final                                                             ;
; Delay Model        ; Combined                                                          ;
; Rise/Fall Delays   ; Enabled                                                           ;
+--------------------+-------------------------------------------------------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 4           ;
; Maximum allowed            ; 2           ;
;                            ;             ;
; Average used               ; 1.35        ;
; Maximum used               ; 2           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processor 2            ;  35.3%      ;
;     Processors 3-4         ;   0.0%      ;
+----------------------------+-------------+


+------------------------------------------------------+
; SDC File List                                        ;
+------------------+--------+--------------------------+
; SDC File Path    ; Status ; Read at                  ;
+------------------+--------+--------------------------+
; atari800core.sdc ; OK     ; Sat Aug  2 12:36:23 2014 ;
+------------------+--------+--------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
+--------------------------------------------------------------------------------+-----------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+-------------------------------------------------------------------------------+----------------------------------------------------------------------------------+------------------------------------------------------------------------------------+
; Clock Name                                                                     ; Type      ; Period  ; Frequency ; Rise  ; Fall    ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master                                                                        ; Source                                                                           ; Targets                                                                            ;
+--------------------------------------------------------------------------------+-----------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+-------------------------------------------------------------------------------+----------------------------------------------------------------------------------+------------------------------------------------------------------------------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Generated ; 11.640  ; 85.91 MHz ; 0.000 ; 5.820   ; 50.00      ; 1         ; 3           ;       ;        ;           ;            ; false    ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] } ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Generated ; 34.920  ; 28.64 MHz ; 0.000 ; 17.460  ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] } ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ; Generated ; 11.640  ; 85.91 MHz ; 7.638 ; 13.458  ; 50.00      ; 1         ; 3           ; 236.2 ;        ;           ;            ; false    ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] } ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Generated ; 17.460  ; 57.27 MHz ; 0.000 ; 8.730   ; 50.00      ; 1         ; 2           ;       ;        ;           ;            ; false    ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] } ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]  ; Generated ; 34.920  ; 28.64 MHz ; 0.000 ; 17.460  ; 50.00      ; 11        ; 63          ;       ;        ;           ;            ; false    ; FPGA_CLK                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]  ; { \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] }  ;
; FPGA_CLK                                                                       ; Base      ; 200.000 ; 5.0 MHz   ; 0.000 ; 100.000 ;            ;           ;             ;       ;        ;           ;            ;          ;                                                                               ;                                                                                  ; { FPGA_CLK }                                                                       ;
+--------------------------------------------------------------------------------+-----------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+-------------------------------------------------------------------------------+----------------------------------------------------------------------------------+------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Fmax Summary                                                                                   ;
+------------+-----------------+--------------------------------------------------------------------------------+------+
; Fmax       ; Restricted Fmax ; Clock Name                                                                     ; Note ;
+------------+-----------------+--------------------------------------------------------------------------------+------+
; 46.14 MHz  ; 46.14 MHz       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;      ;
; 113.13 MHz ; 113.13 MHz      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;      ;
; 136.2 MHz  ; 136.2 MHz       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;      ;
+------------+-----------------+--------------------------------------------------------------------------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


----------------------------------
; Timing Closure Recommendations ;
----------------------------------
HTML report is unavailable in plain text report export.


+---------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup Summary                                                                     ;
+--------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                          ; Slack  ; End Point TNS ;
+--------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.049  ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 2.268  ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 10.118 ; 0.000         ;
+--------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold Summary                                                                     ;
+--------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                          ; Slack ; End Point TNS ;
+--------------------------------------------------------------------------------+-------+---------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.453 ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.453 ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.454 ; 0.000         ;
+--------------------------------------------------------------------------------+-------+---------------+


+---------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery Summary                                                                  ;
+--------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                          ; Slack  ; End Point TNS ;
+--------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 5.854  ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 7.443  ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 12.134 ; 0.000         ;
+--------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal Summary                                                                  ;
+--------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                          ; Slack ; End Point TNS ;
+--------------------------------------------------------------------------------+-------+---------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 2.790 ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 3.809 ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 4.783 ; 0.000         ;
+--------------------------------------------------------------------------------+-------+---------------+


+---------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width Summary                                                       ;
+--------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                          ; Slack  ; End Point TNS ;
+--------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.517  ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 8.433  ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.158 ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]  ; 17.423 ; 0.000         ;
; FPGA_CLK                                                                       ; 99.862 ; 0.000         ;
+--------------------------------------------------------------------------------+--------+---------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                       ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                         ; To Node                                      ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 0.049 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.210     ; 11.252     ;
; 0.425 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.210     ; 10.876     ;
; 0.518 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.210     ; 10.783     ;
; 0.749 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.210     ; 10.552     ;
; 0.756 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.207     ; 10.548     ;
; 0.834 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.207     ; 10.470     ;
; 0.845 ; sdram_reset_n_reg                                                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.210     ; 10.456     ;
; 0.850 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.210     ; 10.451     ;
; 0.918 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.207     ; 10.386     ;
; 0.923 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.212     ; 10.376     ;
; 0.923 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.207     ; 10.381     ;
; 0.954 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.207     ; 10.350     ;
; 0.984 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.211     ; 10.316     ;
; 0.985 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.207     ; 10.319     ;
; 1.017 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.212     ; 10.282     ;
; 1.030 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[5]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.203     ; 10.278     ;
; 1.122 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.212     ; 10.177     ;
; 1.137 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.225     ; 10.149     ;
; 1.144 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.211     ; 10.156     ;
; 1.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.207     ; 10.118     ;
; 1.236 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.225     ; 10.050     ;
; 1.254 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.211     ; 10.046     ;
; 1.275 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.225     ; 10.011     ;
; 1.299 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.212     ; 10.000     ;
; 1.392 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.212     ; 9.907      ;
; 1.392 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.222     ; 9.897      ;
; 1.397 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.208     ; 9.906      ;
; 1.418 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[14]                                                                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.207     ; 9.886      ;
; 1.456 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.211     ; 9.844      ;
; 1.463 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[15]                                                                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.207     ; 9.841      ;
; 1.465 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[4]                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.203     ; 9.843      ;
; 1.479 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[5]                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.207     ; 9.825      ;
; 1.492 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.222     ; 9.797      ;
; 1.513 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.225     ; 9.773      ;
; 1.517 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[6]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.202     ; 9.792      ;
; 1.520 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.211     ; 9.780      ;
; 1.542 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[4]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.203     ; 9.766      ;
; 1.556 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.212     ; 9.743      ;
; 1.587 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.208     ; 9.716      ;
; 1.606 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.225     ; 9.680      ;
; 1.611 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.209     ; 9.691      ;
; 1.612 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.225     ; 9.674      ;
; 1.613 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.211     ; 9.687      ;
; 1.617 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.209     ; 9.685      ;
; 1.623 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.212     ; 9.676      ;
; 1.630 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.209     ; 9.672      ;
; 1.639 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.208     ; 9.664      ;
; 1.651 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.225     ; 9.635      ;
; 1.660 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.208     ; 9.643      ;
; 1.663 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.208     ; 9.640      ;
; 1.665 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.222     ; 9.624      ;
; 1.693 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.213     ; 9.605      ;
; 1.705 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.225     ; 9.581      ;
; 1.706 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.222     ; 9.583      ;
; 1.719 ; sdram_reset_n_reg                                                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.212     ; 9.580      ;
; 1.724 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.212     ; 9.575      ;
; 1.729 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.222     ; 9.560      ;
; 1.733 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.222     ; 9.556      ;
; 1.740 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.222     ; 9.549      ;
; 1.743 ; sdram_reset_n_reg                                                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.211     ; 9.557      ;
; 1.744 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.225     ; 9.542      ;
; 1.748 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.211     ; 9.552      ;
; 1.757 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.208     ; 9.546      ;
; 1.767 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.211     ; 9.533      ;
; 1.768 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|antic_fetch_real_reg                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.207     ; 9.536      ;
; 1.770 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.208     ; 9.533      ;
; 1.792 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.209     ; 9.510      ;
; 1.797 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.209     ; 9.505      ;
; 1.803 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.222     ; 9.486      ;
; 1.806 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.222     ; 9.483      ;
; 1.807 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.222     ; 9.482      ;
; 1.807 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.209     ; 9.495      ;
; 1.811 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.208     ; 9.492      ;
; 1.818 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.211     ; 9.482      ;
; 1.826 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.212     ; 9.473      ;
; 1.829 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[5]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.204     ; 9.478      ;
; 1.837 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.225     ; 9.449      ;
; 1.839 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.222     ; 9.450      ;
; 1.840 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.222     ; 9.449      ;
; 1.844 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.211     ; 9.456      ;
; 1.848 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.222     ; 9.441      ;
; 1.851 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.208     ; 9.452      ;
; 1.861 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[8]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.206     ; 9.444      ;
; 1.886 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.213     ; 9.412      ;
; 1.889 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[5]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.204     ; 9.418      ;
; 1.891 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.214     ; 9.406      ;
; 1.903 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.222     ; 9.386      ;
; 1.904 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[5]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.205     ; 9.402      ;
; 1.906 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.222     ; 9.383      ;
; 1.913 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.214     ; 9.384      ;
; 1.933 ; sdram_reset_n_reg                                                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.225     ; 9.353      ;
; 1.936 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.225     ; 9.350      ;
; 1.938 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.225     ; 9.348      ;
; 1.939 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.222     ; 9.350      ;
; 1.940 ; sdram_reset_n_reg                                                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.211     ; 9.360      ;
; 1.945 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.211     ; 9.355      ;
; 1.951 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.213     ; 9.347      ;
; 1.959 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.209     ; 9.343      ;
; 1.969 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[6]                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.206     ; 9.336      ;
; 1.969 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.209     ; 9.333      ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                              ;
+-------+----------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                  ; To Node                                                                                                                                                    ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 2.268 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.180     ; 9.193      ;
; 2.697 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.180     ; 8.764      ;
; 2.722 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[37]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.201     ; 8.718      ;
; 2.734 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.178     ; 8.729      ;
; 2.747 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.178     ; 8.716      ;
; 2.759 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[31]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.201     ; 8.681      ;
; 2.803 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[35]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.200     ; 8.638      ;
; 2.828 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[0]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.211     ; 8.602      ;
; 2.828 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[1]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.211     ; 8.602      ;
; 2.829 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.200     ; 8.612      ;
; 2.830 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[5]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.211     ; 8.600      ;
; 2.845 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.201     ; 8.595      ;
; 2.845 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.200     ; 8.596      ;
; 2.871 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[0]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.198     ; 8.572      ;
; 2.871 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[1]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.198     ; 8.572      ;
; 2.871 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[2]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.198     ; 8.572      ;
; 2.871 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[3]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.198     ; 8.572      ;
; 2.871 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[4]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.198     ; 8.572      ;
; 2.871 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[5]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.198     ; 8.572      ;
; 2.871 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[6]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.198     ; 8.572      ;
; 2.871 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[7]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.198     ; 8.572      ;
; 2.903 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[35]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.200     ; 8.538      ;
; 2.916 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[0]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.198     ; 8.527      ;
; 2.916 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[1]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.198     ; 8.527      ;
; 2.916 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[2]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.198     ; 8.527      ;
; 2.916 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[3]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.198     ; 8.527      ;
; 2.916 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[4]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.198     ; 8.527      ;
; 2.916 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[5]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.198     ; 8.527      ;
; 2.916 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[6]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.198     ; 8.527      ;
; 2.916 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[7]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.198     ; 8.527      ;
; 2.950 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[4]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.211     ; 8.480      ;
; 3.025 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[11]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.190     ; 8.426      ;
; 3.031 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[2]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.211     ; 8.399      ;
; 3.031 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[3]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.211     ; 8.399      ;
; 3.066 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[6]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.206     ; 8.369      ;
; 3.066 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[7]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.206     ; 8.369      ;
; 3.106 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.200     ; 8.335      ;
; 3.125 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[0]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.201     ; 8.315      ;
; 3.136 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[26]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.178     ; 8.327      ;
; 3.164 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.200     ; 8.277      ;
; 3.168 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[0]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.201     ; 8.272      ;
; 3.189 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.208     ; 8.244      ;
; 3.214 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[1]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.205     ; 8.222      ;
; 3.214 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[2]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.205     ; 8.222      ;
; 3.214 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[3]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.205     ; 8.222      ;
; 3.224 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[5]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.211     ; 8.206      ;
; 3.224 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[2]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.211     ; 8.206      ;
; 3.224 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[1]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.211     ; 8.206      ;
; 3.224 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[0]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.211     ; 8.206      ;
; 3.224 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[3]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.211     ; 8.206      ;
; 3.224 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[4]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.211     ; 8.206      ;
; 3.224 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[6]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.211     ; 8.206      ;
; 3.224 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[7]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.211     ; 8.206      ;
; 3.230 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[0]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.200     ; 8.211      ;
; 3.230 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[1]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.200     ; 8.211      ;
; 3.230 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[2]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.200     ; 8.211      ;
; 3.230 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[3]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.200     ; 8.211      ;
; 3.230 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[4]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.200     ; 8.211      ;
; 3.230 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[5]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.200     ; 8.211      ;
; 3.230 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[6]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.200     ; 8.211      ;
; 3.230 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[7]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.200     ; 8.211      ;
; 3.241 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[1]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.206     ; 8.194      ;
; 3.241 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[0]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.206     ; 8.194      ;
; 3.241 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[2]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.206     ; 8.194      ;
; 3.241 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[3]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.206     ; 8.194      ;
; 3.241 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[4]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.206     ; 8.194      ;
; 3.241 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[5]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.206     ; 8.194      ;
; 3.241 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.178     ; 8.222      ;
; 3.251 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[0]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.198     ; 8.192      ;
; 3.251 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[1]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.198     ; 8.192      ;
; 3.251 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[2]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.198     ; 8.192      ;
; 3.251 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[3]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.198     ; 8.192      ;
; 3.251 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[4]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.198     ; 8.192      ;
; 3.251 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[5]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.198     ; 8.192      ;
; 3.251 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[6]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.198     ; 8.192      ;
; 3.251 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[7]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.198     ; 8.192      ;
; 3.261 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[1]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.206     ; 8.174      ;
; 3.261 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[5]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.206     ; 8.174      ;
; 3.261 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[4]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.206     ; 8.174      ;
; 3.261 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[0]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.206     ; 8.174      ;
; 3.261 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[2]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.206     ; 8.174      ;
; 3.261 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[3]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.206     ; 8.174      ;
; 3.286 ; ram_do_reg[5]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.180     ; 8.175      ;
; 3.312 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[37]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.201     ; 8.128      ;
; 3.313 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[40]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.200     ; 8.128      ;
; 3.334 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[37]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.201     ; 8.106      ;
; 3.361 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer3|delay_line:underflow0_delay|shift_reg[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.199     ; 8.081      ;
; 3.375 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[31]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.201     ; 8.065      ;
; 3.388 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[19]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.201     ; 8.052      ;
; 3.388 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[31]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.201     ; 8.052      ;
; 3.399 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[7]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.210     ; 8.032      ;
; 3.399 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[6]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.210     ; 8.032      ;
; 3.399 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[5]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.210     ; 8.032      ;
; 3.399 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[4]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.210     ; 8.032      ;
; 3.399 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[3]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.210     ; 8.032      ;
; 3.399 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[2]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.210     ; 8.032      ;
; 3.399 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[1]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.210     ; 8.032      ;
; 3.399 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[0]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.210     ; 8.032      ;
; 3.399 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.178     ; 8.064      ;
; 3.418 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.200     ; 8.023      ;
+-------+----------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                                                                                                                                                  ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                ; To Node                                                                         ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 10.118 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.155     ; 7.058      ;
; 10.323 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.155     ; 6.853      ;
; 10.373 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.155     ; 6.803      ;
; 10.426 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.099     ; 6.806      ;
; 10.480 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.156     ; 6.695      ;
; 10.513 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.098     ; 6.720      ;
; 10.517 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.099     ; 6.715      ;
; 10.530 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.099     ; 6.702      ;
; 10.724 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.155     ; 6.452      ;
; 10.740 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.099     ; 6.492      ;
; 10.833 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.098     ; 6.400      ;
; 10.845 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.098     ; 6.388      ;
; 10.852 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.098     ; 6.381      ;
; 10.891 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.154     ; 6.286      ;
; 10.934 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.133     ; 6.264      ;
; 10.935 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.098     ; 6.298      ;
; 10.954 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.133     ; 6.244      ;
; 10.960 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.133     ; 6.238      ;
; 10.962 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.098     ; 6.271      ;
; 10.981 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.098     ; 6.252      ;
; 10.993 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.156     ; 6.182      ;
; 10.998 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.134     ; 6.199      ;
; 11.024 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.099     ; 6.208      ;
; 11.035 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.155     ; 6.141      ;
; 11.055 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.155     ; 6.121      ;
; 11.079 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.099     ; 6.153      ;
; 11.095 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.098     ; 6.138      ;
; 11.110 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.098     ; 6.123      ;
; 11.142 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.098     ; 6.091      ;
; 11.151 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.098     ; 6.082      ;
; 11.158 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.098     ; 6.075      ;
; 11.192 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.098     ; 6.041      ;
; 11.197 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.099     ; 6.035      ;
; 11.201 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.134     ; 5.996      ;
; 11.234 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.098     ; 5.999      ;
; 11.240 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.134     ; 5.957      ;
; 11.248 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.155     ; 5.928      ;
; 11.255 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.098     ; 5.978      ;
; 11.267 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.099     ; 5.965      ;
; 11.325 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.098     ; 5.908      ;
; 11.326 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.133     ; 5.872      ;
; 11.355 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.099     ; 5.877      ;
; 11.362 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.099     ; 5.870      ;
; 11.399 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.098     ; 5.834      ;
; 11.400 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.098     ; 5.833      ;
; 11.401 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.099     ; 5.831      ;
; 11.411 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.134     ; 5.786      ;
; 11.442 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.134     ; 5.755      ;
; 11.486 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.099     ; 5.746      ;
; 11.528 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.467     ; 5.466      ;
; 11.529 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hsync_reg                                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[0]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.168     ; 5.764      ;
; 11.529 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hsync_reg                                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[1]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.168     ; 5.764      ;
; 11.529 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hsync_reg                                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.168     ; 5.764      ;
; 11.529 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hsync_reg                                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.168     ; 5.764      ;
; 11.529 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hsync_reg                                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.168     ; 5.764      ;
; 11.529 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hsync_reg                                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.168     ; 5.764      ;
; 11.529 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hsync_reg                                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.168     ; 5.764      ;
; 11.529 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hsync_reg                                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[7]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.168     ; 5.764      ;
; 11.529 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hsync_reg                                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.168     ; 5.764      ;
; 11.529 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hsync_reg                                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[9]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.168     ; 5.764      ;
; 11.529 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hsync_reg                                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.168     ; 5.764      ;
; 11.569 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.098     ; 5.664      ;
; 11.595 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.098     ; 5.638      ;
; 11.645 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.135     ; 5.551      ;
; 11.653 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.467     ; 5.341      ;
; 11.712 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.134     ; 5.485      ;
; 11.746 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.098     ; 5.487      ;
; 11.775 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.134     ; 5.422      ;
; 11.835 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.099     ; 5.397      ;
; 11.841 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.467     ; 5.153      ;
; 11.851 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.099     ; 5.381      ;
; 11.874 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.099     ; 5.358      ;
; 11.881 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.100     ; 5.350      ;
; 11.905 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.099     ; 5.327      ;
; 11.913 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.100     ; 5.318      ;
; 11.924 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.467     ; 5.070      ;
; 11.944 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.098     ; 5.289      ;
; 11.970 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.467     ; 5.024      ;
; 12.000 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.155     ; 5.176      ;
; 12.007 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.467     ; 4.987      ;
; 12.126 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.469     ; 4.866      ;
; 12.162 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.467     ; 4.832      ;
; 12.166 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.099     ; 5.066      ;
; 12.170 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.098     ; 5.063      ;
; 12.184 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.468     ; 4.809      ;
; 12.231 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.098     ; 5.002      ;
; 12.272 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.156     ; 4.903      ;
; 12.306 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.468     ; 4.687      ;
; 12.374 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.099     ; 4.858      ;
; 12.426 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.099     ; 4.806      ;
; 12.456 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.098     ; 4.777      ;
; 12.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.100     ; 4.728      ;
; 12.511 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.097     ; 4.723      ;
; 12.552 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.468     ; 4.441      ;
; 12.554 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.468     ; 4.439      ;
; 12.638 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.155     ; 4.538      ;
; 12.658 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.468     ; 4.335      ;
; 12.658 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.468     ; 4.335      ;
; 12.662 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.468     ; 4.331      ;
; 12.685 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.155     ; 4.491      ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                         ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                               ; To Node                                                                                                                                                 ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cyclePreRead                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cyclePreRead                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Creg                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Creg                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Vreg                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Vreg                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vblank_reg                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vblank_reg                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_ready_reg                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_ready_reg                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[2]                                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[2]                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[0]                                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[0]                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[1]                                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[1]                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[3]                                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[3]                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[4]                                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[4]                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[5]                                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[5]                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[6]                                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[6]                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[7]                                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[7]                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_clock_reg                                                                                   ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_clock_reg                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_bitcount_reg[0]                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_bitcount_reg[0]                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serial_out_reg                                                                                     ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serial_out_reg                                                                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[50]                                                                                                          ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[50]                                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[58]                                                                                                          ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[58]                                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[59]                                                                                                          ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[59]                                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[65]                                                                                                          ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[65]                                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[61]                                                                                                          ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[61]                                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[60]                                                                                                          ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[60]                                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[26]                                                                                                          ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[26]                                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[93]                                                                                                          ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[93]                                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[84]                                                                                                          ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[84]                                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[29]                                                                                                          ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[29]                                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[27]                                                                                                          ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[27]                                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[28]                                                                                                          ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[28]                                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[91]                                                                                                          ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[91]                                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[0]                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[0]                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[1]                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[1]                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[5]                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[5]                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|first_line_of_instruction_reg                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|first_line_of_instruction_reg                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vscrol_last_enabled_reg                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vscrol_last_enabled_reg                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[4]                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[4]                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|last_line_of_instruction_reg                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|last_line_of_instruction_reg                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|nmist_reg[6]                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|nmist_reg[6]                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[18]                                                                                                          ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[18]                                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[89]                                                                                                          ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[89]                                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|shift_pressed_reg   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|shift_pressed_reg   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|break_pressed_reg   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|break_pressed_reg   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|control_pressed_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|control_pressed_reg ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[120]                                                                                                         ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[120]                                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|irqst_reg[0]                                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|irqst_reg[0]                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[3]                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[3]                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[2]                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[2]                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|count_reg[1]                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|count_reg[1]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|pmg_dma_state_reg[2]                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|pmg_dma_state_reg[2]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|pmg_dma_state_reg[0]                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|pmg_dma_state_reg[0]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[0]                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[0]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[1]                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[1]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[2]                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[2]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[3]                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[3]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[4]                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[4]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[5]                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[5]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[6]                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[6]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p2pf_reg[1]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p2pf_reg[1]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|count_reg[1]                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|count_reg[1]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[0]                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[0]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[7]                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[7]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pl_reg[2]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pl_reg[2]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile2|shift_reg[7]                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile2|shift_reg[7]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pf_reg[1]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pf_reg[1]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pl_reg[1]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pl_reg[1]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile0|count_reg[1]                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile0|count_reg[1]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile0|shift_reg[7]                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile0|shift_reg[7]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pl_reg[1]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pl_reg[1]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pf_reg[1]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pf_reg[1]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|count_reg[1]                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|count_reg[1]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[0]                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[0]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[1]                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[1]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[2]                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[2]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[3]                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[3]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[4]                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[4]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[5]                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[5]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[6]                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[6]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[7]                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0|shift_reg[7]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pf_reg[1]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pf_reg[1]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pl_reg[1]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pl_reg[1]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player3|shift_reg[7]                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player3|shift_reg[7]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|count_reg[1]                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|count_reg[1]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[7]                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[7]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pl_reg[0]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pl_reg[0]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pf_reg[0]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pf_reg[0]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pf_reg[0]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pf_reg[0]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pl_reg[2]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pl_reg[2]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p2pf_reg[0]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p2pf_reg[0]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pf_reg[0]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pf_reg[0]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pl_reg[0]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pl_reg[0]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pl_reg[0]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pl_reg[0]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pl_reg[3]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pl_reg[3]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pl_reg[0]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pl_reg[0]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pf_reg[0]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pf_reg[0]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pf_reg[0]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pf_reg[0]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p2pl_reg[3]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p2pl_reg[3]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pl_reg[2]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pl_reg[2]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pf_reg[2]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pf_reg[2]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pf_reg[2]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pf_reg[2]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pl_reg[2]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pl_reg[2]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pl_reg[2]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pl_reg[2]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                                                                                         ;
+-------+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                       ; To Node                                                                                         ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 0.453 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|buffer_select_reg                     ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|buffer_select_reg                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_hsync_reg                         ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_hsync_reg                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.746      ;
; 0.465 ; half_scandouble_enable_reg                                                                      ; half_scandouble_enable_reg                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.758      ;
; 0.494 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|hsync_in_reg                          ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|buffer_select_reg                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.787      ;
; 0.500 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[108] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[107] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.793      ;
; 0.500 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[105] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[104] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.793      ;
; 0.500 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[56]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[55]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.793      ;
; 0.500 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[50]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[49]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.793      ;
; 0.500 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[46]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[45]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.793      ;
; 0.501 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[121] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[120] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.794      ;
; 0.501 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[113] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[112] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.794      ;
; 0.501 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[109] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[108] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.794      ;
; 0.501 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[92]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[91]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.794      ;
; 0.501 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[87]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[86]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.794      ;
; 0.501 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[60]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[59]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.794      ;
; 0.501 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[51]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[50]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.794      ;
; 0.501 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[48]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[47]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.794      ;
; 0.501 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[26]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[25]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.794      ;
; 0.501 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[25]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[24]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.794      ;
; 0.501 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[15]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[14]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.794      ;
; 0.501 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[4]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[3]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.794      ;
; 0.501 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[2]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[1]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.794      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[123] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[122] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.795      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[122] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[121] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.795      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[120] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[119] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.795      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[111] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[110] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.795      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[107] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[106] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.795      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[106] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[105] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.795      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[101] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[100] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.795      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[91]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[90]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.795      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[90]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[89]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.795      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[88]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[87]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.795      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[86]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[85]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.795      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[85]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[84]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.795      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[79]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[78]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.794      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[76]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[75]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.794      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[68]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[67]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.794      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[63]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[62]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.795      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[61]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[60]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.795      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[59]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[58]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.795      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[58]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[57]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.795      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[57]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[56]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.795      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[43]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[42]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.795      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[42]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[41]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.795      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[34]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[33]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.794      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[27]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[26]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.795      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[23]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[22]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.795      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[22]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[21]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.795      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[17]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[16]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.795      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[14]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[13]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.795      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[12]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[11]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.795      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[11]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[10]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.795      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[7]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[6]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.795      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[6]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[5]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.795      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[127] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[126] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.796      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[125] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[124] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.796      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[124] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[123] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.796      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[116] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[115] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.796      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[104] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[103] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.796      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[102] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[101] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.796      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[94]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[93]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.796      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[77]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[76]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.795      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[73]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[72]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.795      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[47]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[46]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.796      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[40]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[39]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.795      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[35]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[34]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.795      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[33]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[32]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.795      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[31]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[30]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.796      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[30]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[29]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.796      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[20]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[19]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.796      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[8]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[7]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.796      ;
; 0.504 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[83]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[82]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.796      ;
; 0.504 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[78]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[77]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.796      ;
; 0.504 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[75]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[74]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.796      ;
; 0.504 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[71]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[70]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.796      ;
; 0.504 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[55]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[54]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.797      ;
; 0.504 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[36]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[35]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.796      ;
; 0.504 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[24]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[23]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.797      ;
; 0.508 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[10]                 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[10]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.801      ;
; 0.685 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[99]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[98]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.977      ;
; 0.685 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[16]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[15]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.978      ;
; 0.686 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[13]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[12]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.979      ;
; 0.687 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[100] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[99]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.979      ;
; 0.687 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[32]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[31]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.979      ;
; 0.690 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[41]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[40]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.983      ;
; 0.694 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[53]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[52]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.987      ;
; 0.695 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[84]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[83]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.988      ;
; 0.695 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[82]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[81]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.988      ;
; 0.697 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[118] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[117] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.990      ;
; 0.697 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[97]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[96]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.990      ;
; 0.698 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[117] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[116] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.991      ;
; 0.698 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[115] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[114] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.991      ;
; 0.698 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[81]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[80]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.991      ;
; 0.698 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[65]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[64]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.991      ;
; 0.698 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[62]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[61]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.991      ;
; 0.698 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[49]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[48]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.991      ;
; 0.698 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[29]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[28]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.991      ;
; 0.698 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[28]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[27]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.991      ;
; 0.698 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[21]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[20]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.991      ;
; 0.699 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[126] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[125] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.992      ;
+-------+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                   ;
+-------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                       ; To Node                                                   ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 0.454 ; sdram_request_complete_reg                                                                                      ; sdram_request_complete_reg                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; sdram_ctrl:sdram_controller|r_refr_act                                                                          ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_rd_act                                                                            ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_wr_act                                                                            ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                                      ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                           ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                                                                        ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.467 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.758      ;
; 0.467 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.758      ;
; 0.530 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.821      ;
; 0.543 ; seq_reg[11]                                                                                                     ; seq_reg[0]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.835      ;
; 0.568 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.859      ;
; 0.570 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.861      ;
; 0.678 ; sdram_ctrl:sdram_controller|r_rd_reg                                                                            ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.969      ;
; 0.679 ; sdram_ctrl:sdram_controller|r_rd_reg                                                                            ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.970      ;
; 0.717 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[19] ; ram_di_reg[3]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.177      ; 1.126      ;
; 0.717 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[20] ; ram_di_reg[4]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.177      ; 1.126      ;
; 0.717 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[25] ; ram_di_reg[9]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.177      ; 1.126      ;
; 0.717 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[28] ; ram_di_reg[12]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.177      ; 1.126      ;
; 0.736 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.027      ;
; 0.737 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.028      ;
; 0.737 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.028      ;
; 0.740 ; seq_reg[8]                                                                                                      ; seq_reg[9]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.032      ;
; 0.740 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.031      ;
; 0.740 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.031      ;
; 0.740 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.031      ;
; 0.741 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.032      ;
; 0.742 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.033      ;
; 0.743 ; sdram_ctrl:sdram_controller|r_psel_dly[0]                                                                       ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.034      ;
; 0.743 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.034      ;
; 0.749 ; seq_reg[4]                                                                                                      ; seq_reg[5]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.041      ;
; 0.750 ; sdram_ctrl:sdram_controller|r_rd_act                                                                            ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.041      ;
; 0.751 ; seq_reg[6]                                                                                                      ; seq_reg[7]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.043      ;
; 0.754 ; sdram_ctrl:sdram_controller|r_refr_act                                                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.047      ;
; 0.757 ; seq_reg[0]                                                                                                      ; seq_reg[1]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.049      ;
; 0.761 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.052      ;
; 0.800 ; sdram_ctrl:sdram_controller|r_rd_act                                                                            ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.091      ;
; 0.840 ; sdram_ctrl:sdram_controller|r_refr_req                                                                          ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.131      ;
; 0.846 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                                      ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.137      ;
; 0.864 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                                       ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.155      ;
; 0.867 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[18] ; ram_di_reg[2]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.176      ; 1.275      ;
; 0.868 ; seq_reg[10]                                                                                                     ; seq_reg[11]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.160      ;
; 0.875 ; sdram_ctrl:sdram_controller|r_refr_req                                                                          ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.166      ;
; 0.881 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[17] ; ram_di_reg[1]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.178      ; 1.291      ;
; 0.892 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[16] ; ram_di_reg[0]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.177      ; 1.301      ;
; 0.894 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[21] ; ram_di_reg[5]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.177      ; 1.303      ;
; 0.915 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                                      ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.206      ;
; 0.943 ; seq_reg[9]                                                                                                      ; seq_reg[10]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.235      ;
; 0.953 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                                       ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.244      ;
; 0.954 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.245      ;
; 0.958 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.249      ;
; 0.976 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[31] ; ram_di_reg[15]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.177      ; 1.385      ;
; 0.985 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[22] ; ram_di_reg[6]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.179      ; 1.396      ;
; 0.987 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[29] ; ram_di_reg[13]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.179      ; 1.398      ;
; 0.989 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[24] ; ram_di_reg[8]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.179      ; 1.400      ;
; 0.989 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[30] ; ram_di_reg[14]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.179      ; 1.400      ;
; 0.990 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[27] ; ram_di_reg[11]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.177      ; 1.399      ;
; 0.991 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.282      ;
; 0.992 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[23] ; ram_di_reg[7]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.177      ; 1.401      ;
; 1.006 ; sdram_ctrl:sdram_controller|r_wr_act                                                                            ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.297      ;
; 1.048 ; sdram_ctrl:sdram_controller|r_refr_req                                                                          ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.339      ;
; 1.091 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.382      ;
; 1.091 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.382      ;
; 1.092 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.383      ;
; 1.094 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.385      ;
; 1.095 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[11] ; ram_di_reg[11]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.177      ; 1.504      ;
; 1.101 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.392      ;
; 1.101 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.392      ;
; 1.102 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.393      ;
; 1.104 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.395      ;
; 1.110 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.401      ;
; 1.110 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.401      ;
; 1.111 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.402      ;
; 1.113 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.404      ;
; 1.162 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[26] ; ram_di_reg[10]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.176      ; 1.570      ;
; 1.174 ; sdram_ctrl:sdram_controller|r_refr_act                                                                          ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 1.454      ;
; 1.174 ; sdram_ctrl:sdram_controller|r_refr_act                                                                          ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 1.454      ;
; 1.183 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                                                                       ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.474      ;
; 1.184 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.475      ;
; 1.222 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.513      ;
; 1.222 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.513      ;
; 1.223 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.514      ;
; 1.225 ; seq_reg[5]                                                                                                      ; seq_reg[6]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.517      ;
; 1.226 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[5]  ; ram_di_reg[5]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.184      ; 1.642      ;
; 1.231 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.522      ;
; 1.231 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.522      ;
; 1.232 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.523      ;
; 1.241 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.532      ;
; 1.242 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.533      ;
; 1.244 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.535      ;
; 1.245 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[13] ; ram_di_reg[13]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.178      ; 1.655      ;
; 1.250 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                                       ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.092      ; 1.554      ;
; 1.250 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.541      ;
; 1.251 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.542      ;
; 1.253 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.544      ;
+-------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                       ;
+-------+---------------------------------------+-------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                                                                                                     ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+-------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 5.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_8BIT_WRITE_ENABLE_reg                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.176     ; 5.611      ;
; 5.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[23]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.175     ; 5.612      ;
; 5.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[8]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.181     ; 5.606      ;
; 5.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[25]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.175     ; 5.612      ;
; 5.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[28]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.175     ; 5.612      ;
; 5.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[10]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.172     ; 5.615      ;
; 5.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[12]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.172     ; 5.615      ;
; 5.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[9]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.172     ; 5.615      ;
; 5.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[31]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.173     ; 5.614      ;
; 5.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[11]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.172     ; 5.615      ;
; 5.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[21]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.175     ; 5.612      ;
; 5.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[29]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.175     ; 5.612      ;
; 5.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[13]                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.177     ; 5.610      ;
; 5.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[20]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.175     ; 5.612      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[4]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.196     ; 5.590      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.183     ; 5.603      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[31]                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 5.599      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[31]                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 5.599      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[31]                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 5.599      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[31]                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 5.599      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.181     ; 5.605      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[12]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.189     ; 5.597      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_READ_reg                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.188     ; 5.598      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[1]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.190     ; 5.596      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[0]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.190     ; 5.596      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[0]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.195     ; 5.591      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[0]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.189     ; 5.597      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[1]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.192     ; 5.594      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[1]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.189     ; 5.597      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[2]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.192     ; 5.594      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[2]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.189     ; 5.597      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[3]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.192     ; 5.594      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[3]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 5.599      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[4]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.192     ; 5.594      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[4]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.188     ; 5.598      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[5]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.189     ; 5.597      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[6]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.192     ; 5.594      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[6]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.189     ; 5.597      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[7]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.189     ; 5.597      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[8]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.190     ; 5.596      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[8]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.188     ; 5.598      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[9]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.190     ; 5.596      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[9]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.188     ; 5.598      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[10]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 5.599      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[11]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.195     ; 5.591      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[11]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.195     ; 5.591      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[12]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.189     ; 5.597      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[13]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.191     ; 5.595      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[14]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.189     ; 5.597      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[16]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.190     ; 5.596      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[0]                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.201     ; 5.585      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[17]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.190     ; 5.596      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[1]                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.201     ; 5.585      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[3]                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 5.599      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[2]                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 5.599      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[21]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.192     ; 5.594      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[5]                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.201     ; 5.585      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[20]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.191     ; 5.595      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[4]                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.201     ; 5.585      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[7]                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.201     ; 5.585      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[6]                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.201     ; 5.585      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[10]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 5.599      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[9]                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.188     ; 5.598      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[24]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.190     ; 5.596      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[8]                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.188     ; 5.598      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[6]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.189     ; 5.597      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[5]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.189     ; 5.597      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[4]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.189     ; 5.597      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[3]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.189     ; 5.597      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[2]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.189     ; 5.597      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[1]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.189     ; 5.597      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[0]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.189     ; 5.597      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[23]                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 5.599      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[23]                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 5.599      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[23]                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 5.599      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[23]                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 5.599      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[15]                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.201     ; 5.585      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[19]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.174     ; 5.612      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[13]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.179     ; 5.607      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|skctl_reg[3]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.190     ; 5.596      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|skctl_reg[5]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.190     ; 5.596      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|sio_in_reg                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.200     ; 5.586      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|skctl_reg[4]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.190     ; 5.596      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serin_bitcount_reg[0]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.193     ; 5.593      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serin_bitcount_reg[1]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.193     ; 5.593      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serin_bitcount_reg[3]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.193     ; 5.593      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serin_bitcount_reg[2]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.193     ; 5.593      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audctl_reg[3]                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.201     ; 5.585      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audctl_reg[5]                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.201     ; 5.585      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|syncreset_enable_divider:enable_64_div|count_reg[0]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.203     ; 5.583      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|syncreset_enable_divider:enable_64_div|count_reg[1]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.203     ; 5.583      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|syncreset_enable_divider:enable_64_div|count_reg[2]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.203     ; 5.583      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|syncreset_enable_divider:enable_64_div|count_reg[3]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.203     ; 5.583      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|syncreset_enable_divider:enable_64_div|count_reg[4]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.203     ; 5.583      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|syncreset_enable_divider:enable_64_div|enabled_out_reg ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.203     ; 5.583      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audctl_reg[0]                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.201     ; 5.585      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[2]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.190     ; 5.596      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[0]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.190     ; 5.596      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[1]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.190     ; 5.596      ;
; 5.855 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[3]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.190     ; 5.596      ;
+-------+---------------------------------------+-------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                      ;
+-------+------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                                   ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 7.443 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[7]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.399     ; 3.657      ;
; 7.443 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[15]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.375     ; 3.681      ;
; 7.443 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[9]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.389     ; 3.667      ;
; 7.443 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[8]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.385     ; 3.671      ;
; 7.443 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[4]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.403     ; 3.653      ;
; 7.443 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[13]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.375     ; 3.681      ;
; 7.443 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[5]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.401     ; 3.655      ;
; 7.443 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[14]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.375     ; 3.681      ;
; 7.444 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[1]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.398     ; 3.657      ;
; 7.444 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[2]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.398     ; 3.657      ;
; 7.444 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[0]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.398     ; 3.657      ;
; 7.444 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[6]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.397     ; 3.658      ;
; 7.444 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[3]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.399     ; 3.656      ;
; 7.451 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[4]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.201     ; 3.859      ;
; 7.451 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[8]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.202     ; 3.858      ;
; 7.451 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.202     ; 3.858      ;
; 7.452 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[0]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.216     ; 3.843      ;
; 7.452 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[1]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.216     ; 3.843      ;
; 7.452 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[2]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.216     ; 3.843      ;
; 7.452 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[3]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.216     ; 3.843      ;
; 7.452 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[5]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.202     ; 3.857      ;
; 7.452 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[6]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.203     ; 3.856      ;
; 7.452 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[7]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.203     ; 3.856      ;
; 7.452 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.214     ; 3.845      ;
; 7.452 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.216     ; 3.843      ;
; 7.452 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.216     ; 3.843      ;
; 7.455 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[11]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.377     ; 3.667      ;
; 7.455 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[10]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.377     ; 3.667      ;
; 7.455 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[12]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.377     ; 3.667      ;
; 7.461 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[0]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.271     ; 3.779      ;
; 7.461 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[1]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.271     ; 3.779      ;
; 7.461 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[2]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.271     ; 3.779      ;
; 7.461 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[13]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.248     ; 3.802      ;
; 7.461 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[14]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.248     ; 3.802      ;
; 7.461 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[15]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.248     ; 3.802      ;
; 7.463 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[8]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.258     ; 3.790      ;
; 7.464 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[7]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.272     ; 3.775      ;
; 7.465 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[4]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.276     ; 3.770      ;
; 7.465 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[5]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.274     ; 3.772      ;
; 7.466 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[3]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.272     ; 3.773      ;
; 7.467 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[6]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.270     ; 3.774      ;
; 7.467 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[9]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.262     ; 3.782      ;
; 7.479 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[10]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.250     ; 3.782      ;
; 7.479 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[11]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.250     ; 3.782      ;
; 7.479 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[12]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.250     ; 3.782      ;
; 7.507 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.190     ; 3.944      ;
; 7.507 ; sdram_reset_ctrl_n_reg ; ram_do_reg[14]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.190     ; 3.944      ;
; 7.507 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.184     ; 3.950      ;
; 7.552 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.192     ; 3.897      ;
; 7.552 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.192     ; 3.897      ;
; 7.552 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.192     ; 3.897      ;
; 7.552 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.192     ; 3.897      ;
; 7.552 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.192     ; 3.897      ;
; 7.552 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.192     ; 3.897      ;
; 7.552 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.192     ; 3.897      ;
; 7.552 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.192     ; 3.897      ;
; 7.552 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.192     ; 3.897      ;
; 7.702 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.214     ; 3.595      ;
; 7.702 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.214     ; 3.595      ;
; 7.702 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.214     ; 3.595      ;
; 7.702 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.214     ; 3.595      ;
; 7.996 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.180     ; 3.465      ;
; 7.996 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.180     ; 3.465      ;
; 7.996 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.180     ; 3.465      ;
; 7.996 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.180     ; 3.465      ;
; 7.996 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.180     ; 3.465      ;
; 7.996 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.180     ; 3.465      ;
; 7.996 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.185     ; 3.460      ;
; 7.996 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.196     ; 3.449      ;
; 7.996 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.195     ; 3.450      ;
; 7.996 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.196     ; 3.449      ;
; 7.996 ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.196     ; 3.449      ;
; 7.996 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.195     ; 3.450      ;
; 7.996 ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.195     ; 3.450      ;
; 7.996 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.195     ; 3.450      ;
; 7.996 ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.195     ; 3.450      ;
; 7.996 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.196     ; 3.449      ;
; 7.996 ; sdram_reset_ctrl_n_reg ; ram_di_reg[11]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.196     ; 3.449      ;
; 7.996 ; sdram_reset_ctrl_n_reg ; ram_di_reg[12]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.196     ; 3.449      ;
; 7.996 ; sdram_reset_ctrl_n_reg ; ram_di_reg[15]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.195     ; 3.450      ;
; 7.996 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.185     ; 3.460      ;
; 7.997 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.193     ; 3.451      ;
; 7.997 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.193     ; 3.451      ;
; 7.997 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.193     ; 3.451      ;
; 7.997 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.193     ; 3.451      ;
; 7.997 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.193     ; 3.451      ;
; 7.997 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.193     ; 3.451      ;
; 7.997 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.193     ; 3.451      ;
; 7.997 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.193     ; 3.451      ;
; 7.997 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.193     ; 3.451      ;
; 7.997 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.193     ; 3.451      ;
; 7.997 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.196     ; 3.448      ;
; 7.997 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.196     ; 3.448      ;
; 7.997 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.196     ; 3.448      ;
; 7.997 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.196     ; 3.448      ;
; 7.997 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.196     ; 3.448      ;
; 7.997 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.191     ; 3.453      ;
; 7.997 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.191     ; 3.453      ;
; 7.997 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.191     ; 3.453      ;
; 7.997 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.191     ; 3.453      ;
+-------+------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                        ;
+--------+-------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node         ; To Node                                                                                         ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 12.134 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vsync_reg                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.200     ; 4.997      ;
; 12.135 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|hsync_reg                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.200     ; 4.996      ;
; 12.135 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.199     ; 4.997      ;
; 12.135 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.199     ; 4.997      ;
; 12.135 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.199     ; 4.997      ;
; 12.135 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.199     ; 4.997      ;
; 12.135 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.200     ; 4.996      ;
; 12.135 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.200     ; 4.996      ;
; 12.135 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.199     ; 4.997      ;
; 12.135 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.199     ; 4.997      ;
; 12.137 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.256     ; 4.938      ;
; 12.137 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.256     ; 4.938      ;
; 12.141 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.234     ; 4.956      ;
; 12.154 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.235     ; 4.942      ;
; 12.679 ; sdram_reset_n_reg ; half_scandouble_enable_reg                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.187     ; 4.595      ;
; 12.679 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.187     ; 4.595      ;
; 12.679 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[1]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.187     ; 4.595      ;
; 12.679 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[2]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.187     ; 4.595      ;
; 12.679 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[3]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.187     ; 4.595      ;
; 12.679 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[4]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.187     ; 4.595      ;
; 12.679 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[5]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.187     ; 4.595      ;
; 12.679 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[6]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.187     ; 4.595      ;
; 12.679 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[7]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.187     ; 4.595      ;
; 12.679 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[8]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.187     ; 4.595      ;
; 12.679 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[9]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.187     ; 4.595      ;
; 12.679 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[10]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.187     ; 4.595      ;
; 12.679 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.181     ; 4.601      ;
; 12.679 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.181     ; 4.601      ;
; 12.679 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.181     ; 4.601      ;
; 12.679 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.181     ; 4.601      ;
; 12.679 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.181     ; 4.601      ;
; 12.679 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.181     ; 4.601      ;
; 12.679 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.181     ; 4.601      ;
; 12.679 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.181     ; 4.601      ;
; 12.679 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.181     ; 4.601      ;
; 12.680 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[10]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.182     ; 4.599      ;
; 12.680 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.182     ; 4.599      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[127] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.180     ; 4.588      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[126] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.180     ; 4.588      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[125] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.180     ; 4.588      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[124] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.180     ; 4.588      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[123] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.180     ; 4.588      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[122] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.180     ; 4.588      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[121] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.180     ; 4.588      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[120] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.180     ; 4.588      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[119] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.180     ; 4.588      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[118] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.180     ; 4.588      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[117] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.180     ; 4.588      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[116] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.180     ; 4.588      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[115] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.180     ; 4.588      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[114] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.180     ; 4.588      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[113] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.179     ; 4.589      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[112] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.179     ; 4.589      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[111] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.179     ; 4.589      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[110] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.179     ; 4.589      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[109] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.179     ; 4.589      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[108] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.179     ; 4.589      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[107] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.179     ; 4.589      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[106] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.179     ; 4.589      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[105] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.179     ; 4.589      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[104] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.179     ; 4.589      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[103] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.179     ; 4.589      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[102] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.179     ; 4.589      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[101] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.179     ; 4.589      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[100] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.179     ; 4.589      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[98]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.180     ; 4.588      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[97]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.180     ; 4.588      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[96]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.180     ; 4.588      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[95]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.180     ; 4.588      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[94]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.180     ; 4.588      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[93]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.180     ; 4.588      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[92]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.180     ; 4.588      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[91]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.180     ; 4.588      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[90]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.180     ; 4.588      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[89]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.180     ; 4.588      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[88]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.180     ; 4.588      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[87]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.180     ; 4.588      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[86]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.180     ; 4.588      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[85]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.180     ; 4.588      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[84]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.180     ; 4.588      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[81]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.179     ; 4.589      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[80]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.179     ; 4.589      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[66]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.178     ; 4.590      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[65]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.178     ; 4.590      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[64]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.178     ; 4.590      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[63]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.178     ; 4.590      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[62]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.178     ; 4.590      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[61]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.178     ; 4.590      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[60]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.178     ; 4.590      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[59]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.178     ; 4.590      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[58]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.178     ; 4.590      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[57]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.178     ; 4.590      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[56]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.178     ; 4.590      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[55]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.178     ; 4.590      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[54]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.178     ; 4.590      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[52]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.178     ; 4.590      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[51]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.178     ; 4.590      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[50]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.178     ; 4.590      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[49]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.178     ; 4.590      ;
; 12.693 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[48]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.178     ; 4.590      ;
+--------+-------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                      ;
+-------+------------------------+----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                                  ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 2.790 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.199      ; 3.221      ;
; 2.790 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.199      ; 3.221      ;
; 2.790 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.199      ; 3.221      ;
; 2.790 ; sdram_reset_ctrl_n_reg ; seq_reg[5]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.199      ; 3.221      ;
; 2.790 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.199      ; 3.221      ;
; 2.790 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.199      ; 3.221      ;
; 2.790 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.199      ; 3.221      ;
; 2.790 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.199      ; 3.221      ;
; 2.790 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.199      ; 3.221      ;
; 2.790 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[0]                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.199      ; 3.221      ;
; 2.790 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[1]                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.199      ; 3.221      ;
; 2.803 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.187      ; 3.222      ;
; 2.803 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.187      ; 3.222      ;
; 2.803 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.187      ; 3.222      ;
; 2.803 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.187      ; 3.222      ;
; 2.803 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.187      ; 3.222      ;
; 2.803 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.187      ; 3.222      ;
; 2.803 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.187      ; 3.222      ;
; 2.803 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.187      ; 3.222      ;
; 2.803 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.187      ; 3.222      ;
; 2.803 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.187      ; 3.222      ;
; 2.803 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.190      ; 3.225      ;
; 2.803 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.190      ; 3.225      ;
; 2.803 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.190      ; 3.225      ;
; 2.803 ; sdram_reset_ctrl_n_reg ; ram_do_reg[5]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.190      ; 3.225      ;
; 2.803 ; sdram_reset_ctrl_n_reg ; ram_do_reg[15]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.190      ; 3.225      ;
; 2.803 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.190      ; 3.225      ;
; 2.803 ; sdram_reset_ctrl_n_reg ; ram_do_reg[12]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.190      ; 3.225      ;
; 2.803 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.190      ; 3.225      ;
; 2.803 ; sdram_reset_ctrl_n_reg ; ram_do_reg[11]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.190      ; 3.225      ;
; 2.803 ; sdram_reset_ctrl_n_reg ; ram_do_reg[19]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.190      ; 3.225      ;
; 2.803 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.190      ; 3.225      ;
; 2.803 ; sdram_reset_ctrl_n_reg ; ram_do_reg[13]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.190      ; 3.225      ;
; 2.803 ; sdram_reset_ctrl_n_reg ; ram_do_reg[20]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.190      ; 3.225      ;
; 2.803 ; sdram_reset_ctrl_n_reg ; ram_di_reg[6]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.186      ; 3.221      ;
; 2.803 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.186      ; 3.221      ;
; 2.803 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.186      ; 3.221      ;
; 2.803 ; sdram_reset_ctrl_n_reg ; ram_di_reg[14]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.186      ; 3.221      ;
; 2.804 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.190      ; 3.226      ;
; 2.804 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.190      ; 3.226      ;
; 2.804 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.190      ; 3.226      ;
; 2.804 ; sdram_reset_ctrl_n_reg ; ram_do_reg[25]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.190      ; 3.226      ;
; 2.804 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.190      ; 3.226      ;
; 2.804 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.190      ; 3.226      ;
; 2.804 ; sdram_reset_ctrl_n_reg ; ram_do_reg[9]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.190      ; 3.226      ;
; 2.804 ; sdram_reset_ctrl_n_reg ; ram_do_reg[8]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.190      ; 3.226      ;
; 2.805 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.184      ; 3.221      ;
; 2.805 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.184      ; 3.221      ;
; 2.805 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.184      ; 3.221      ;
; 2.805 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.196      ; 3.233      ;
; 2.805 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.184      ; 3.221      ;
; 2.805 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.185      ; 3.222      ;
; 2.805 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.186      ; 3.223      ;
; 2.805 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.185      ; 3.222      ;
; 2.805 ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.185      ; 3.222      ;
; 2.805 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.186      ; 3.223      ;
; 2.805 ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.186      ; 3.223      ;
; 2.805 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.186      ; 3.223      ;
; 2.805 ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.186      ; 3.223      ;
; 2.805 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.185      ; 3.222      ;
; 2.805 ; sdram_reset_ctrl_n_reg ; ram_di_reg[11]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.185      ; 3.222      ;
; 2.805 ; sdram_reset_ctrl_n_reg ; ram_di_reg[12]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.185      ; 3.222      ;
; 2.805 ; sdram_reset_ctrl_n_reg ; ram_di_reg[15]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.186      ; 3.223      ;
; 2.805 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.184      ; 3.221      ;
; 2.805 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.184      ; 3.221      ;
; 2.805 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.184      ; 3.221      ;
; 2.805 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.196      ; 3.233      ;
; 2.806 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.201      ; 3.239      ;
; 2.806 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.201      ; 3.239      ;
; 2.806 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.201      ; 3.239      ;
; 2.806 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.201      ; 3.239      ;
; 2.806 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.201      ; 3.239      ;
; 2.806 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.201      ; 3.239      ;
; 2.806 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.171      ; 3.209      ;
; 2.806 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.171      ; 3.209      ;
; 2.806 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.171      ; 3.209      ;
; 2.806 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.171      ; 3.209      ;
; 2.806 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_act                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.171      ; 3.209      ;
; 2.806 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.171      ; 3.209      ;
; 2.807 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.184      ; 3.223      ;
; 2.807 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.184      ; 3.223      ;
; 2.807 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.184      ; 3.223      ;
; 2.807 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.184      ; 3.223      ;
; 2.807 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.184      ; 3.223      ;
; 2.807 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.188      ; 3.227      ;
; 3.039 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.170      ; 3.355      ;
; 3.039 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.171      ; 3.356      ;
; 3.039 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.171      ; 3.356      ;
; 3.039 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.170      ; 3.355      ;
; 3.204 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.189      ; 3.625      ;
; 3.204 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.189      ; 3.625      ;
; 3.204 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.189      ; 3.625      ;
; 3.204 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.189      ; 3.625      ;
; 3.204 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.189      ; 3.625      ;
; 3.204 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.189      ; 3.625      ;
; 3.204 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.189      ; 3.625      ;
; 3.204 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.189      ; 3.625      ;
; 3.204 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.189      ; 3.625      ;
; 3.263 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.190      ; 3.685      ;
; 3.263 ; sdram_reset_ctrl_n_reg ; ram_do_reg[14]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.190      ; 3.685      ;
+-------+------------------------+----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                        ;
+-------+-------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node         ; To Node                                                                                         ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 3.809 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[127] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.203      ; 4.244      ;
; 3.809 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[126] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.203      ; 4.244      ;
; 3.809 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[125] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.203      ; 4.244      ;
; 3.809 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[124] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.203      ; 4.244      ;
; 3.809 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[123] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.203      ; 4.244      ;
; 3.809 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[122] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.203      ; 4.244      ;
; 3.809 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[121] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.203      ; 4.244      ;
; 3.809 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[120] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.203      ; 4.244      ;
; 3.809 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[119] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.203      ; 4.244      ;
; 3.809 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[118] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.203      ; 4.244      ;
; 3.809 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[117] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.203      ; 4.244      ;
; 3.809 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[116] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.203      ; 4.244      ;
; 3.809 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[115] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.203      ; 4.244      ;
; 3.809 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[114] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.203      ; 4.244      ;
; 3.809 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[53]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.205      ; 4.246      ;
; 3.809 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[52]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.205      ; 4.246      ;
; 3.809 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[51]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.205      ; 4.246      ;
; 3.809 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[50]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.205      ; 4.246      ;
; 3.809 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[49]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.205      ; 4.246      ;
; 3.809 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[48]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.205      ; 4.246      ;
; 3.809 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[47]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.205      ; 4.246      ;
; 3.809 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[46]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.205      ; 4.246      ;
; 3.809 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[45]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.205      ; 4.246      ;
; 3.809 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[44]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.205      ; 4.246      ;
; 3.809 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[43]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.205      ; 4.246      ;
; 3.809 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[42]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.205      ; 4.246      ;
; 3.809 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[41]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.205      ; 4.246      ;
; 3.809 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.201      ; 4.242      ;
; 3.809 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.201      ; 4.242      ;
; 3.809 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.201      ; 4.242      ;
; 3.809 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.201      ; 4.242      ;
; 3.809 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.201      ; 4.242      ;
; 3.811 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|buffer_select_reg                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.202      ; 4.245      ;
; 3.811 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[12]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.205      ; 4.248      ;
; 3.811 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[11]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.205      ; 4.248      ;
; 3.811 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[10]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.205      ; 4.248      ;
; 3.811 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[9]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.205      ; 4.248      ;
; 3.811 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[8]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.205      ; 4.248      ;
; 3.811 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[7]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.205      ; 4.248      ;
; 3.811 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[6]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.205      ; 4.248      ;
; 3.811 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[5]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.205      ; 4.248      ;
; 3.811 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[4]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.205      ; 4.248      ;
; 3.811 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[3]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.205      ; 4.248      ;
; 3.811 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[2]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.205      ; 4.248      ;
; 3.811 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[1]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.205      ; 4.248      ;
; 3.811 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[0]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.205      ; 4.248      ;
; 3.811 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.202      ; 4.245      ;
; 3.811 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.202      ; 4.245      ;
; 3.812 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[113] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.204      ; 4.248      ;
; 3.812 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[112] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.204      ; 4.248      ;
; 3.812 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[111] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.204      ; 4.248      ;
; 3.812 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[110] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.204      ; 4.248      ;
; 3.812 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[109] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.204      ; 4.248      ;
; 3.812 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[108] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.204      ; 4.248      ;
; 3.812 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[107] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.204      ; 4.248      ;
; 3.812 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[106] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.204      ; 4.248      ;
; 3.812 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[105] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.204      ; 4.248      ;
; 3.812 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[104] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.204      ; 4.248      ;
; 3.812 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[103] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.204      ; 4.248      ;
; 3.812 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[102] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.204      ; 4.248      ;
; 3.812 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[101] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.204      ; 4.248      ;
; 3.812 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[100] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.204      ; 4.248      ;
; 3.812 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[99]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.203      ; 4.247      ;
; 3.812 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[98]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.203      ; 4.247      ;
; 3.812 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[97]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.203      ; 4.247      ;
; 3.812 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[96]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.203      ; 4.247      ;
; 3.812 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[95]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.203      ; 4.247      ;
; 3.812 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[94]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.203      ; 4.247      ;
; 3.812 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[93]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.203      ; 4.247      ;
; 3.812 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[92]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.203      ; 4.247      ;
; 3.812 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[91]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.203      ; 4.247      ;
; 3.812 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[90]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.203      ; 4.247      ;
; 3.812 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[89]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.203      ; 4.247      ;
; 3.812 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[88]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.203      ; 4.247      ;
; 3.812 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[87]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.203      ; 4.247      ;
; 3.812 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[86]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.203      ; 4.247      ;
; 3.812 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[85]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.203      ; 4.247      ;
; 3.812 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[84]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.203      ; 4.247      ;
; 3.812 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[83]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.203      ; 4.247      ;
; 3.812 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[82]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.203      ; 4.247      ;
; 3.812 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[81]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.204      ; 4.248      ;
; 3.812 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[80]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.204      ; 4.248      ;
; 3.812 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[79]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.203      ; 4.247      ;
; 3.812 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[78]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.203      ; 4.247      ;
; 3.812 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[77]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.203      ; 4.247      ;
; 3.812 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[76]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.203      ; 4.247      ;
; 3.812 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[75]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.203      ; 4.247      ;
; 3.812 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[74]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.203      ; 4.247      ;
; 3.812 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[73]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.203      ; 4.247      ;
; 3.812 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[72]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.203      ; 4.247      ;
; 3.812 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[71]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.203      ; 4.247      ;
; 3.812 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[70]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.203      ; 4.247      ;
; 3.812 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[69]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.203      ; 4.247      ;
; 3.812 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[68]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.203      ; 4.247      ;
; 3.812 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[67]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.203      ; 4.247      ;
; 3.812 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[66]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.205      ; 4.249      ;
; 3.812 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[65]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.205      ; 4.249      ;
; 3.812 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[64]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.205      ; 4.249      ;
; 3.812 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[63]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.205      ; 4.249      ;
; 3.812 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[62]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.205      ; 4.249      ;
+-------+-------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                            ;
+-------+---------------------------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                                                                                         ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[5]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.199      ; 5.214      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[2]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.199      ; 5.214      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[3]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.199      ; 5.214      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[27]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.207      ; 5.222      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[15]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.196      ; 5.211      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[8]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 5.209      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[15]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.211      ; 5.226      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[25]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.205      ; 5.220      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[27]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.205      ; 5.220      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[7]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.205      ; 5.220      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[7]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.205      ; 5.220      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[7]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.206      ; 5.221      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[7]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.206      ; 5.221      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[6]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.206      ; 5.221      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[2]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.206      ; 5.221      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[3]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.206      ; 5.221      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[9]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.205      ; 5.220      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[9]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.206      ; 5.221      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[14]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.211      ; 5.226      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[6]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.205      ; 5.220      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[6]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.205      ; 5.220      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[6]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.206      ; 5.221      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[22]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.205      ; 5.220      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[22]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.205      ; 5.220      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[3]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.205      ; 5.220      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[3]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.205      ; 5.220      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[3]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.206      ; 5.221      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[19]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.207      ; 5.222      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[5]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.200      ; 5.215      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[13]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.211      ; 5.226      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[8]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.211      ; 5.226      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[0]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.205      ; 5.220      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[0]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.206      ; 5.221      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[0]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.210      ; 5.225      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[20]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.205      ; 5.220      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[20]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.205      ; 5.220      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[14]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.196      ; 5.211      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[2]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.205      ; 5.220      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[2]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.205      ; 5.220      ;
; 4.783 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[2]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.206      ; 5.221      ;
; 4.784 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[15]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 5.210      ;
; 4.784 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[15]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 5.210      ;
; 4.784 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[5]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.196      ; 5.212      ;
; 4.784 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|delay_line:serout_clock_delay|shift_reg[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 5.197      ;
; 4.784 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|delay_line:serout_clock_delay|shift_reg[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 5.197      ;
; 4.784 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_clock_reg                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 5.197      ;
; 4.784 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_clock_last_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 5.197      ;
; 4.784 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_holding_full_reg                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 5.197      ;
; 4.784 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_active_reg                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 5.197      ;
; 4.784 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serial_out_reg                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 5.197      ;
; 4.784 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[27]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 5.210      ;
; 4.784 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[10]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 5.210      ;
; 4.784 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[12]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 5.210      ;
; 4.784 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[11]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 5.210      ;
; 4.784 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[11]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 5.210      ;
; 4.784 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[21]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 5.210      ;
; 4.784 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[21]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 5.210      ;
; 4.784 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|irqst_reg[3]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 5.197      ;
; 4.784 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[19]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 5.210      ;
; 4.784 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[19]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 5.210      ;
; 4.784 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[13]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 5.210      ;
; 4.784 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[13]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 5.210      ;
; 4.784 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[18]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 5.210      ;
; 4.784 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[18]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 5.210      ;
; 4.784 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[16]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.197      ; 5.213      ;
; 4.784 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[6]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.196      ; 5.212      ;
; 4.785 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|state                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.179      ; 5.196      ;
; 4.785 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|busy                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.179      ; 5.196      ;
; 4.785 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|ss_n[0]                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.179      ; 5.196      ;
; 4.785 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[25]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.193      ; 5.210      ;
; 4.785 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[25]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.193      ; 5.210      ;
; 4.785 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[27]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.193      ; 5.210      ;
; 4.785 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[27]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.193      ; 5.210      ;
; 4.785 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[26]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 5.211      ;
; 4.785 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[26]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 5.211      ;
; 4.785 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[10]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 5.211      ;
; 4.785 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[10]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 5.211      ;
; 4.785 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[12]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 5.211      ;
; 4.785 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[12]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 5.211      ;
; 4.785 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[22]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.193      ; 5.210      ;
; 4.785 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[22]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.193      ; 5.210      ;
; 4.785 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[11]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 5.211      ;
; 4.785 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[21]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.193      ; 5.210      ;
; 4.785 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[19]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.193      ; 5.210      ;
; 4.785 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[19]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.193      ; 5.210      ;
; 4.785 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[13]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 5.211      ;
; 4.785 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[20]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.193      ; 5.210      ;
; 4.785 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[20]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.193      ; 5.210      ;
; 4.785 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[14]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.193      ; 5.210      ;
; 4.785 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[18]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.193      ; 5.210      ;
; 4.785 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[18]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.193      ; 5.210      ;
; 4.785 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|irqen_reg[2]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 5.197      ;
; 4.785 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[16]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.196      ; 5.213      ;
; 4.785 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[8]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 5.211      ;
; 4.785 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|mosi~en                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.179      ; 5.196      ;
; 4.797 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[19]                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.207      ; 5.236      ;
; 4.797 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[9]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.204      ; 5.233      ;
; 4.797 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[10]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.203      ; 5.232      ;
; 4.797 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[12]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.204      ; 5.233      ;
; 4.797 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[11]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.204      ; 5.233      ;
+-------+---------------------------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                        ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                          ; Clock Edge ; Target                                                    ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; 5.517 ; 5.737        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[13]                                            ;
; 5.517 ; 5.737        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[14]                                            ;
; 5.517 ; 5.737        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[6]                                             ;
; 5.517 ; 5.737        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[8]                                             ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[11]                                            ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[12]                                            ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[13]                                            ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[14]                                            ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[15]                                            ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[19]                                            ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[20]                                            ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[23]                                            ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[28]                                            ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[29]                                            ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[31]                                            ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[4]                                             ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[5]                                             ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[6]                                             ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[7]                                             ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[0]                                             ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[10]                                            ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[1]                                             ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[25]                                            ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[2]                                             ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[3]                                             ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[8]                                             ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[9]                                             ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[0]                                             ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[10]                                            ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[11]                                            ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[12]                                            ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[15]                                            ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[1]                                             ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[2]                                             ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[3]                                             ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[4]                                             ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[5]                                             ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[7]                                             ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[9]                                             ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[16]                                            ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[17]                                            ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[18]                                            ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[21]                                            ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[22]                                            ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[24]                                            ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[26]                                            ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[27]                                            ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[30]                                            ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_act                      ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_reg                      ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_req                    ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_act                      ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_reg                      ;
; 5.521 ; 5.741        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[0]                                           ;
; 5.521 ; 5.741        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[1]                                           ;
; 5.521 ; 5.741        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel[0]                     ;
; 5.521 ; 5.741        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_act                    ;
; 5.521 ; 5.741        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ;
; 5.521 ; 5.741        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_reg                                         ;
; 5.521 ; 5.741        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[0]                                                ;
; 5.521 ; 5.741        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[10]                                               ;
; 5.521 ; 5.741        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[11]                                               ;
; 5.521 ; 5.741        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[1]                                                ;
; 5.521 ; 5.741        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[2]                                                ;
; 5.521 ; 5.741        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[3]                                                ;
; 5.521 ; 5.741        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[4]                                                ;
; 5.521 ; 5.741        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[5]                                                ;
; 5.521 ; 5.741        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[6]                                                ;
; 5.521 ; 5.741        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[7]                                                ;
; 5.521 ; 5.741        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[8]                                                ;
; 5.521 ; 5.741        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[9]                                                ;
; 5.522 ; 5.742        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ;
; 5.522 ; 5.742        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ;
; 5.522 ; 5.742        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ;
; 5.522 ; 5.742        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ;
; 5.522 ; 5.742        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ;
; 5.522 ; 5.742        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|sdram_rdy                     ;
; 5.522 ; 5.742        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_complete_reg                                ;
; 5.608 ; 5.766        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[0]                   ;
; 5.608 ; 5.766        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[1]                   ;
; 5.608 ; 5.766        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[2]                   ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+-----------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                              ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                          ; Clock Edge ; Target                                                                                          ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------------------------+
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; half_scandouble_enable_reg                                                                      ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|buffer_select_reg                     ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                         ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                         ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                         ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                         ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                         ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                         ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                         ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[0]   ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[100] ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[101] ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[102] ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[103] ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[104] ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[105] ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[106] ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[107] ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[108] ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[109] ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[10]  ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[110] ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[111] ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[112] ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[113] ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[114] ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[115] ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[116] ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[117] ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[118] ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[119] ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[11]  ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[120] ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[121] ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[122] ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[123] ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[124] ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[125] ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[126] ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[127] ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[12]  ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[13]  ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[14]  ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[15]  ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[16]  ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[17]  ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[18]  ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[19]  ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[1]   ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[20]  ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[21]  ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[22]  ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[23]  ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[24]  ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[25]  ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[26]  ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[27]  ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[28]  ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[29]  ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[2]   ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[30]  ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[31]  ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[3]   ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[41]  ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[42]  ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[43]  ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[44]  ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[45]  ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[46]  ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[47]  ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[48]  ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[49]  ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[4]   ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[50]  ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[51]  ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[52]  ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[53]  ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[54]  ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[55]  ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[56]  ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[57]  ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[58]  ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[59]  ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[5]   ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[60]  ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[61]  ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[62]  ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[63]  ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[64]  ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[65]  ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[66]  ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[6]   ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[7]   ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[80]  ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[81]  ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[84]  ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[85]  ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[86]  ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[87]  ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[88]  ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                         ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                          ; Clock Edge ; Target                                                                                                                                    ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------+
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[0]                    ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[19]                   ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[37]                   ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[42]                   ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p1[10]                                                                                                        ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p1[11]                                                                                                        ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p1[12]                                                                                                        ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p1[2]                                                                                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p1[3]                                                                                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p1[4]                                                                                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p1[5]                                                                                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p1[6]                                                                                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p1[7]                                                                                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p1[8]                                                                                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p1[9]                                                                                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p2[0]                                                                                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p2[10]                                                                                                        ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p2[11]                                                                                                        ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p2[1]                                                                                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p2[2]                                                                                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p2[3]                                                                                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p2[4]                                                                                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p2[5]                                                                                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p2[6]                                                                                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p2[7]                                                                                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p2[8]                                                                                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p2[9]                                                                                                         ;
; 17.159 ; 17.379       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[17][1]        ;
; 17.159 ; 17.379       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[18][1]        ;
; 17.159 ; 17.379       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[19][1]        ;
; 17.159 ; 17.379       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[20][1]        ;
; 17.159 ; 17.379       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[21][1]        ;
; 17.159 ; 17.379       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[22][1]        ;
; 17.159 ; 17.379       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[23][1]        ;
; 17.159 ; 17.379       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[24][1]        ;
; 17.159 ; 17.379       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[25][1]        ;
; 17.159 ; 17.379       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[26][1]        ;
; 17.159 ; 17.379       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[27][1]        ;
; 17.159 ; 17.379       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                    ;
; 17.159 ; 17.379       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_lpf_p2[0]                                                                                                         ;
; 17.159 ; 17.379       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_lpf_p2[10]                                                                                                        ;
; 17.159 ; 17.379       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_lpf_p2[11]                                                                                                        ;
; 17.159 ; 17.379       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_lpf_p2[1]                                                                                                         ;
; 17.159 ; 17.379       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_lpf_p2[2]                                                                                                         ;
; 17.159 ; 17.379       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_lpf_p2[3]                                                                                                         ;
; 17.159 ; 17.379       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_lpf_p2[4]                                                                                                         ;
; 17.159 ; 17.379       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_lpf_p2[5]                                                                                                         ;
; 17.159 ; 17.379       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_lpf_p2[6]                                                                                                         ;
; 17.159 ; 17.379       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_lpf_p2[7]                                                                                                         ;
; 17.159 ; 17.379       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_lpf_p2[8]                                                                                                         ;
; 17.159 ; 17.379       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_lpf_p2[9]                                                                                                         ;
; 17.160 ; 17.380       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|irqActive                     ;
; 17.160 ; 17.380       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[14]                   ;
; 17.160 ; 17.380       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[24]                   ;
; 17.160 ; 17.380       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[25]                   ;
; 17.160 ; 17.380       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[31]                   ;
; 17.160 ; 17.380       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]                   ;
; 17.160 ; 17.380       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[35]                   ;
; 17.160 ; 17.380       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[39]                   ;
; 17.160 ; 17.380       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[40]                   ;
; 17.160 ; 17.380       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[5]                    ;
; 17.160 ; 17.380       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[6]                    ;
; 17.160 ; 17.380       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|processInt                    ;
; 17.160 ; 17.380       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theOpcode[5]                  ;
; 17.160 ; 17.380       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theOpcode[6]                  ;
; 17.160 ; 17.380       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theOpcode[7]                  ;
; 17.160 ; 17.380       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p1[13]                                                                                                        ;
; 17.160 ; 17.380       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p1[14]                                                                                                        ;
; 17.160 ; 17.380       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p1[15]                                                                                                        ;
; 17.160 ; 17.380       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p1[16]                                                                                                        ;
; 17.160 ; 17.380       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p1[17]                                                                                                        ;
; 17.160 ; 17.380       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p1[18]                                                                                                        ;
; 17.160 ; 17.380       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p1[19]                                                                                                        ;
; 17.160 ; 17.380       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p1[20]                                                                                                        ;
; 17.160 ; 17.380       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p1[21]                                                                                                        ;
; 17.160 ; 17.380       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p1[22]                                                                                                        ;
; 17.160 ; 17.380       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p1[23]                                                                                                        ;
; 17.160 ; 17.380       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[10]                                                                                      ;
; 17.161 ; 17.381       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[13]                                 ;
; 17.161 ; 17.381       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[14]                                 ;
; 17.161 ; 17.381       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[15]                                 ;
; 17.161 ; 17.381       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[16]                                 ;
; 17.161 ; 17.381       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[18]                                 ;
; 17.161 ; 17.381       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[19]                                 ;
; 17.161 ; 17.381       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[20]                                 ;
; 17.161 ; 17.381       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[21]                                 ;
; 17.161 ; 17.381       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[22]                                 ;
; 17.161 ; 17.381       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[23]                                 ;
; 17.161 ; 17.381       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|antic_fetch_real_reg                         ;
; 17.161 ; 17.381       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|cpu_fetch_real_reg                           ;
; 17.161 ; 17.381       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                 ;
; 17.161 ; 17.381       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                 ;
; 17.161 ; 17.381       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                   ;
; 17.161 ; 17.381       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|antic_dma_clock:antic_dma_clock1|dma_shiftreg_reg[0] ;
; 17.161 ; 17.381       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|antic_dma_clock:antic_dma_clock1|dma_shiftreg_reg[1] ;
; 17.161 ; 17.381       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|antic_dma_clock:antic_dma_clock1|dma_shiftreg_reg[2] ;
; 17.161 ; 17.381       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|antic_dma_clock:antic_dma_clock1|dma_shiftreg_reg[3] ;
; 17.161 ; 17.381       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|antic_dma_clock:antic_dma_clock1|dma_shiftreg_reg[4] ;
; 17.161 ; 17.381       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|antic_dma_clock:antic_dma_clock1|dma_shiftreg_reg[5] ;
; 17.161 ; 17.381       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|antic_dma_clock:antic_dma_clock1|dma_shiftreg_reg[6] ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                   ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                         ; Clock Edge ; Target                                                                                              ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------+
; 17.423 ; 17.423       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.423 ; 17.423       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.423 ; 17.423       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.423 ; 17.423       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]                      ;
; 17.423 ; 17.423       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 17.428 ; 17.428       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.428 ; 17.428       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.435 ; 17.435       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.484 ; 17.484       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.491 ; 17.491       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.491 ; 17.491       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.496 ; 17.496       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.496 ; 17.496       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.496 ; 17.496       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.496 ; 17.496       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]                      ;
; 17.496 ; 17.496       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'FPGA_CLK'                                                                                                                        ;
+---------+--------------+----------------+------------------+----------+------------+-----------------------------------------------------------------------------------------+
; Slack   ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                                                  ;
+---------+--------------+----------------+------------------+----------+------------+-----------------------------------------------------------------------------------------+
; 99.862  ; 99.862       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 99.862  ; 99.862       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 99.888  ; 99.888       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                        ;
; 99.929  ; 99.929       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 100.000 ; 100.000      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                        ;
; 100.000 ; 100.000      ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                        ;
; 100.070 ; 100.070      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 100.112 ; 100.112      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                        ;
; 100.137 ; 100.137      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 100.137 ; 100.137      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 196.000 ; 200.000      ; 4.000          ; Port Rate        ; FPGA_CLK ; Rise       ; FPGA_CLK                                                                                ;
+---------+--------------+----------------+------------------+----------+------------+-----------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                              ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 3.046 ; 3.153 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.025 ; 3.132 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.025 ; 3.132 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.025 ; 3.132 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.036 ; 3.143 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.040 ; 3.147 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.038 ; 3.145 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.034 ; 3.141 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.046 ; 3.153 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.032 ; 3.139 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.036 ; 3.143 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.024 ; 3.131 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.024 ; 3.131 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.014 ; 3.121 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 3.012 ; 3.119 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 3.002 ; 3.109 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 3.012 ; 3.119 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; 6.415 ; 6.835 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; 4.015 ; 4.221 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; 5.075 ; 5.301 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; 4.900 ; 5.203 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; 4.624 ; 4.861 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; 6.415 ; 6.835 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; 6.008 ; 6.437 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; 3.738 ; 3.948 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; 4.790 ; 4.942 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; 4.515 ; 4.739 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; 4.431 ; 4.674 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; 6.008 ; 6.437 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; 7.279 ; 7.561 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; 7.135 ; 7.445 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; 4.810 ; 4.949 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                 ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; -2.005 ; -2.112 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; -2.030 ; -2.137 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; -2.030 ; -2.137 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; -2.030 ; -2.137 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; -2.040 ; -2.147 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; -2.045 ; -2.152 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; -2.042 ; -2.149 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; -2.039 ; -2.146 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; -2.050 ; -2.157 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; -2.036 ; -2.143 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; -2.040 ; -2.147 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; -2.028 ; -2.135 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; -2.028 ; -2.135 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; -2.018 ; -2.125 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; -2.015 ; -2.122 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; -2.005 ; -2.112 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; -2.015 ; -2.122 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; -2.938 ; -3.131 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; -2.938 ; -3.131 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; -3.927 ; -4.111 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; -3.759 ; -4.017 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; -3.490 ; -3.691 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; -3.101 ; -3.282 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; -2.676 ; -2.869 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; -2.676 ; -2.869 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; -3.685 ; -3.823 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; -3.338 ; -3.533 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; -3.342 ; -3.568 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; -3.030 ; -3.226 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; -6.083 ; -6.357 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; -5.950 ; -6.247 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; -3.719 ; -3.857 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                      ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 4.389 ; 3.932 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 3.289 ; 3.000 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 3.279 ; 2.990 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 3.279 ; 2.990 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 3.279 ; 2.990 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 3.284 ; 2.995 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 3.293 ; 3.004 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 3.302 ; 3.013 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 4.389 ; 3.932 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 3.303 ; 3.014 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 3.313 ; 3.024 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 3.289 ; 3.000 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 4.376 ; 3.919 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 3.290 ; 3.001 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 4.376 ; 3.919 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 4.388 ; 3.931 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 3.300 ; 3.011 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 4.455 ; 4.000 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 3.574 ; 3.263 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 3.574 ; 3.263 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 3.574 ; 3.263 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 4.430 ; 3.975 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 4.425 ; 3.970 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 2.356 ; 2.151 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 3.477 ; 3.180 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 3.486 ; 3.189 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 3.608 ; 3.297 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 4.450 ; 3.995 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 3.616 ; 3.305 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 3.616 ; 3.305 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 3.606 ; 3.295 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 4.455 ; 4.000 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 3.599 ; 3.288 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 3.609 ; 3.298 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 4.166 ; 4.476 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 3.783 ; 4.085 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 4.166 ; 4.476 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 3.300 ; 3.011 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 3.311 ; 3.022 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 6.177 ; 6.514 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 4.895 ; 4.869 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 4.936 ; 4.662 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 7.136 ; 7.372 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 3.865 ; 4.029 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 9.089 ;       ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 8.849 ; Fall       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]        ; FPGA_CLK   ; 5.179 ; 5.520 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]       ; FPGA_CLK   ; 2.605 ; 2.568 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]       ; FPGA_CLK   ; 5.179 ; 5.520 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]       ; FPGA_CLK   ; 2.375 ; 2.318 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]       ; FPGA_CLK   ; 5.157 ; 5.498 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]        ; FPGA_CLK   ; 5.068 ; 5.354 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]       ; FPGA_CLK   ; 5.068 ; 5.354 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]       ; FPGA_CLK   ; 2.307 ; 2.183 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]       ; FPGA_CLK   ; 2.317 ; 2.193 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]       ; FPGA_CLK   ; 2.307 ; 2.183 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_HS          ; FPGA_CLK   ; 5.057 ; 5.343 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_R[*]        ; FPGA_CLK   ; 2.297 ; 2.173 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[0]       ; FPGA_CLK   ; 2.286 ; 2.162 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[1]       ; FPGA_CLK   ; 2.296 ; 2.172 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[2]       ; FPGA_CLK   ; 2.297 ; 2.173 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[3]       ; FPGA_CLK   ; 2.287 ; 2.163 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_VS          ; FPGA_CLK   ; 2.296 ; 2.172 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                              ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 2.417 ; 2.133 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 2.427 ; 2.143 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 2.417 ; 2.133 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 2.417 ; 2.133 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 2.417 ; 2.133 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 2.422 ; 2.138 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 2.431 ; 2.147 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 2.440 ; 2.156 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 3.573 ; 3.117 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 2.441 ; 2.157 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 2.451 ; 2.167 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 2.427 ; 2.143 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 2.429 ; 2.145 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 2.429 ; 2.145 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 3.560 ; 3.104 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 3.572 ; 3.116 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 2.439 ; 2.155 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 1.542 ; 1.338 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 2.712 ; 2.407 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 2.712 ; 2.407 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 2.712 ; 2.407 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 3.616 ; 3.162 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 3.612 ; 3.158 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 1.542 ; 1.338 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 2.615 ; 2.324 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 2.623 ; 2.332 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 2.745 ; 2.440 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 3.636 ; 3.182 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 2.753 ; 2.448 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 2.753 ; 2.448 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 2.743 ; 2.438 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 3.640 ; 3.186 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 2.735 ; 2.430 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 2.745 ; 2.440 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 2.902 ; 3.198 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 2.902 ; 3.198 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 3.270 ; 3.574 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 2.439 ; 2.155 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 2.449 ; 2.165 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 5.328 ; 5.666 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 3.994 ; 3.968 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 4.020 ; 3.753 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 6.242 ; 6.481 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 2.987 ; 3.149 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 8.319 ;       ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 8.083 ; Fall       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]        ; FPGA_CLK   ; 1.561 ; 1.505 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]       ; FPGA_CLK   ; 1.790 ; 1.754 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]       ; FPGA_CLK   ; 4.364 ; 4.706 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]       ; FPGA_CLK   ; 1.561 ; 1.505 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]       ; FPGA_CLK   ; 4.343 ; 4.685 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]        ; FPGA_CLK   ; 1.490 ; 1.367 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]       ; FPGA_CLK   ; 4.251 ; 4.538 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]       ; FPGA_CLK   ; 1.490 ; 1.367 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]       ; FPGA_CLK   ; 1.500 ; 1.377 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]       ; FPGA_CLK   ; 1.490 ; 1.367 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_HS          ; FPGA_CLK   ; 4.240 ; 4.527 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_R[*]        ; FPGA_CLK   ; 1.469 ; 1.346 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[0]       ; FPGA_CLK   ; 1.469 ; 1.346 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[1]       ; FPGA_CLK   ; 1.479 ; 1.356 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[2]       ; FPGA_CLK   ; 1.480 ; 1.357 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[3]       ; FPGA_CLK   ; 1.470 ; 1.347 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_VS          ; FPGA_CLK   ; 1.479 ; 1.356 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                                      ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.576 ; 2.576 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.354 ; 3.354 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.354 ; 3.354 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.354 ; 3.354 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.404 ; 3.404 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.816 ; 3.816 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 4.161 ; 4.161 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 4.187 ; 4.187 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 4.212 ; 4.212 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.836 ; 3.836 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.416 ; 3.416 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.961 ; 2.961 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.961 ; 2.961 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.951 ; 2.951 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.586 ; 2.586 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.576 ; 2.576 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.586 ; 2.586 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 4.504 ; 4.120 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                              ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.251 ; 1.280 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.997 ; 2.026 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.997 ; 2.026 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.997 ; 2.026 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.046 ; 2.075 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.441 ; 2.470 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.772 ; 2.801 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.797 ; 2.826 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.821 ; 2.850 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.461 ; 2.490 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.057 ; 2.086 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.621 ; 1.650 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.621 ; 1.650 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.611 ; 1.640 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 1.261 ; 1.290 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.251 ; 1.280 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.261 ; 1.290 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.509 ; 3.141 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                             ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.344     ; 2.584     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.075     ; 3.315     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.075     ; 3.315     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.075     ; 3.315     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.148     ; 3.388     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.538     ; 3.778     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.840     ; 4.080     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.890     ; 4.130     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.913     ; 4.153     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.503     ; 3.743     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.136     ; 3.376     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.699     ; 2.939     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.699     ; 2.939     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.689     ; 2.929     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.354     ; 2.594     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.344     ; 2.584     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.354     ; 2.594     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 4.048     ; 4.432     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                                     ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.258     ; 1.258     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.959     ; 1.959     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.959     ; 1.959     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.959     ; 1.959     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.030     ; 2.030     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.405     ; 2.405     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.694     ; 2.694     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.742     ; 2.742     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.765     ; 2.765     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.371     ; 2.371     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.019     ; 2.019     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.599     ; 1.599     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.599     ; 1.599     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.589     ; 1.589     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 1.268     ; 1.268     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.258     ; 1.258     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.268     ; 1.268     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.071     ; 3.439     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+


----------------------------------------------
; Slow 1200mV 85C Model Metastability Report ;
----------------------------------------------
No synchronizer chains to report.


+----------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Fmax Summary                                                                                    ;
+------------+-----------------+--------------------------------------------------------------------------------+------+
; Fmax       ; Restricted Fmax ; Clock Name                                                                     ; Note ;
+------------+-----------------+--------------------------------------------------------------------------------+------+
; 48.53 MHz  ; 48.53 MHz       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;      ;
; 121.15 MHz ; 121.15 MHz      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;      ;
; 143.27 MHz ; 143.27 MHz      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;      ;
+------------+-----------------+--------------------------------------------------------------------------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+---------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup Summary                                                                      ;
+--------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                          ; Slack  ; End Point TNS ;
+--------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.706  ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 2.858  ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 10.480 ; 0.000         ;
+--------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold Summary                                                                      ;
+--------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                          ; Slack ; End Point TNS ;
+--------------------------------------------------------------------------------+-------+---------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.402 ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.402 ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.402 ; 0.000         ;
+--------------------------------------------------------------------------------+-------+---------------+


+---------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery Summary                                                                   ;
+--------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                          ; Slack  ; End Point TNS ;
+--------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 6.355  ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 7.792  ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 12.524 ; 0.000         ;
+--------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal Summary                                                                   ;
+--------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                          ; Slack ; End Point TNS ;
+--------------------------------------------------------------------------------+-------+---------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 2.493 ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 3.412 ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 4.369 ; 0.000         ;
+--------------------------------------------------------------------------------+-------+---------------+


+---------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width Summary                                                        ;
+--------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                          ; Slack  ; End Point TNS ;
+--------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.518  ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 8.431  ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.158 ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]  ; 17.426 ; 0.000         ;
; FPGA_CLK                                                                       ; 99.837 ; 0.000         ;
+--------------------------------------------------------------------------------+--------+---------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                        ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                         ; To Node                                      ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 0.706 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.186     ; 10.624     ;
; 0.985 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.186     ; 10.345     ;
; 1.062 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.186     ; 10.268     ;
; 1.307 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.183     ; 10.026     ;
; 1.316 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.186     ; 10.014     ;
; 1.379 ; sdram_reset_n_reg                                                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.186     ; 9.951      ;
; 1.391 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.186     ; 9.939      ;
; 1.461 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.183     ; 9.872      ;
; 1.466 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.184     ; 9.866      ;
; 1.495 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.183     ; 9.838      ;
; 1.558 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.188     ; 9.770      ;
; 1.560 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.183     ; 9.773      ;
; 1.562 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.187     ; 9.767      ;
; 1.581 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.184     ; 9.751      ;
; 1.622 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[5]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.180     ; 9.714      ;
; 1.686 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.187     ; 9.643      ;
; 1.745 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.200     ; 9.571      ;
; 1.763 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.187     ; 9.566      ;
; 1.784 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.184     ; 9.548      ;
; 1.811 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.188     ; 9.517      ;
; 1.837 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.200     ; 9.479      ;
; 1.837 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.188     ; 9.491      ;
; 1.914 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.188     ; 9.414      ;
; 1.945 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.184     ; 9.387      ;
; 1.955 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.200     ; 9.361      ;
; 1.969 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[14]                                                                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.183     ; 9.364      ;
; 2.007 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.187     ; 9.322      ;
; 2.017 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[5]                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.184     ; 9.315      ;
; 2.024 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.200     ; 9.292      ;
; 2.026 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[4]                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.180     ; 9.310      ;
; 2.035 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[6]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.179     ; 9.302      ;
; 2.068 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[15]                                                                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.183     ; 9.265      ;
; 2.074 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.198     ; 9.244      ;
; 2.090 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.188     ; 9.238      ;
; 2.101 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.200     ; 9.215      ;
; 2.115 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[4]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.180     ; 9.221      ;
; 2.116 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.200     ; 9.200      ;
; 2.151 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.185     ; 9.180      ;
; 2.159 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.185     ; 9.172      ;
; 2.167 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.188     ; 9.161      ;
; 2.168 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.188     ; 9.160      ;
; 2.170 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.198     ; 9.148      ;
; 2.176 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.185     ; 9.155      ;
; 2.188 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.184     ; 9.144      ;
; 2.189 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.187     ; 9.140      ;
; 2.193 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.200     ; 9.123      ;
; 2.230 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.188     ; 9.098      ;
; 2.231 ; sdram_reset_n_reg                                                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.188     ; 9.097      ;
; 2.234 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.200     ; 9.082      ;
; 2.243 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.188     ; 9.085      ;
; 2.245 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.188     ; 9.083      ;
; 2.263 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.186     ; 9.067      ;
; 2.266 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.197     ; 9.053      ;
; 2.267 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.198     ; 9.051      ;
; 2.268 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|antic_fetch_real_reg                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.184     ; 9.064      ;
; 2.311 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.200     ; 9.005      ;
; 2.313 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.185     ; 9.018      ;
; 2.318 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.186     ; 9.012      ;
; 2.332 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.184     ; 9.000      ;
; 2.334 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.197     ; 8.985      ;
; 2.340 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[5]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.182     ; 8.994      ;
; 2.344 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.197     ; 8.975      ;
; 2.346 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.197     ; 8.973      ;
; 2.355 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.200     ; 8.961      ;
; 2.357 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.185     ; 8.974      ;
; 2.360 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[8]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.184     ; 8.972      ;
; 2.366 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.184     ; 8.966      ;
; 2.376 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.198     ; 8.942      ;
; 2.385 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.198     ; 8.933      ;
; 2.394 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.185     ; 8.937      ;
; 2.398 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.185     ; 8.933      ;
; 2.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.185     ; 8.919      ;
; 2.413 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.187     ; 8.916      ;
; 2.414 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.189     ; 8.913      ;
; 2.418 ; sdram_reset_n_reg                                                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.200     ; 8.898      ;
; 2.421 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.188     ; 8.907      ;
; 2.426 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.187     ; 8.903      ;
; 2.430 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.200     ; 8.886      ;
; 2.430 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.197     ; 8.889      ;
; 2.436 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.189     ; 8.891      ;
; 2.438 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.197     ; 8.881      ;
; 2.447 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.200     ; 8.869      ;
; 2.448 ; sdram_reset_n_reg                                                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.187     ; 8.881      ;
; 2.456 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.197     ; 8.863      ;
; 2.458 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.198     ; 8.860      ;
; 2.469 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.187     ; 8.860      ;
; 2.472 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.198     ; 8.846      ;
; 2.474 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[5]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.182     ; 8.860      ;
; 2.478 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.185     ; 8.853      ;
; 2.484 ; sdram_reset_n_reg                                                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.188     ; 8.844      ;
; 2.494 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.185     ; 8.837      ;
; 2.494 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.198     ; 8.824      ;
; 2.496 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.188     ; 8.832      ;
; 2.496 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[6]                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.183     ; 8.837      ;
; 2.506 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[5]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.181     ; 8.829      ;
; 2.510 ; sdram_reset_n_reg                                                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.200     ; 8.806      ;
; 2.511 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.185     ; 8.820      ;
; 2.522 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.200     ; 8.794      ;
; 2.524 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.188     ; 8.804      ;
; 2.534 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[6]                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.182     ; 8.800      ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                               ;
+-------+----------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                  ; To Node                                                                                                                                                    ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 2.858 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.160     ; 8.624      ;
; 3.143 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.160     ; 8.339      ;
; 3.258 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.157     ; 8.227      ;
; 3.284 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[37]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.179     ; 8.179      ;
; 3.325 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.156     ; 8.161      ;
; 3.335 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[35]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.176     ; 8.131      ;
; 3.338 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[35]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.176     ; 8.128      ;
; 3.353 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.178     ; 8.111      ;
; 3.357 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.177     ; 8.108      ;
; 3.360 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[31]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.177     ; 8.105      ;
; 3.408 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[0]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.175     ; 8.059      ;
; 3.408 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[1]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.175     ; 8.059      ;
; 3.408 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[2]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.175     ; 8.059      ;
; 3.408 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[3]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.175     ; 8.059      ;
; 3.408 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[4]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.175     ; 8.059      ;
; 3.408 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[5]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.175     ; 8.059      ;
; 3.408 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[6]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.175     ; 8.059      ;
; 3.408 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[7]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.175     ; 8.059      ;
; 3.439 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[0]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.174     ; 8.029      ;
; 3.439 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[1]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.174     ; 8.029      ;
; 3.439 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[2]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.174     ; 8.029      ;
; 3.439 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[3]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.174     ; 8.029      ;
; 3.439 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[4]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.174     ; 8.029      ;
; 3.439 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[5]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.174     ; 8.029      ;
; 3.439 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[6]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.174     ; 8.029      ;
; 3.439 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[7]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.174     ; 8.029      ;
; 3.439 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.178     ; 8.025      ;
; 3.527 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[0]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.188     ; 7.927      ;
; 3.527 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[1]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.188     ; 7.927      ;
; 3.536 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[5]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.185     ; 7.921      ;
; 3.545 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[11]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.169     ; 7.928      ;
; 3.615 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.179     ; 7.848      ;
; 3.621 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[26]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.156     ; 7.865      ;
; 3.644 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[4]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.185     ; 7.813      ;
; 3.651 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[0]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.179     ; 7.812      ;
; 3.656 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.179     ; 7.807      ;
; 3.673 ; ram_do_reg[5]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.158     ; 7.811      ;
; 3.718 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.185     ; 7.739      ;
; 3.718 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[2]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.185     ; 7.739      ;
; 3.718 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[3]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.185     ; 7.739      ;
; 3.729 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[0]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.178     ; 7.735      ;
; 3.735 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.155     ; 7.752      ;
; 3.744 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[6]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.183     ; 7.715      ;
; 3.744 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[7]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.183     ; 7.715      ;
; 3.753 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[37]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.179     ; 7.710      ;
; 3.755 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[0]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.178     ; 7.709      ;
; 3.755 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[1]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.178     ; 7.709      ;
; 3.755 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[2]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.178     ; 7.709      ;
; 3.755 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[3]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.178     ; 7.709      ;
; 3.755 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[4]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.178     ; 7.709      ;
; 3.755 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[5]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.178     ; 7.709      ;
; 3.755 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[6]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.178     ; 7.709      ;
; 3.755 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[7]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.178     ; 7.709      ;
; 3.757 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[5]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.188     ; 7.697      ;
; 3.757 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[2]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.188     ; 7.697      ;
; 3.757 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[1]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.188     ; 7.697      ;
; 3.757 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[0]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.188     ; 7.697      ;
; 3.757 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[3]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.188     ; 7.697      ;
; 3.757 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[4]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.188     ; 7.697      ;
; 3.757 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[6]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.188     ; 7.697      ;
; 3.757 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[7]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.188     ; 7.697      ;
; 3.760 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[0]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.175     ; 7.707      ;
; 3.760 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[1]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.175     ; 7.707      ;
; 3.760 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[2]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.175     ; 7.707      ;
; 3.760 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[3]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.175     ; 7.707      ;
; 3.760 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[4]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.175     ; 7.707      ;
; 3.760 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[5]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.175     ; 7.707      ;
; 3.760 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[6]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.175     ; 7.707      ;
; 3.760 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[7]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.175     ; 7.707      ;
; 3.820 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[40]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.176     ; 7.646      ;
; 3.821 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[37]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.178     ; 7.643      ;
; 3.832 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[31]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.178     ; 7.632      ;
; 3.834 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[1]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.181     ; 7.627      ;
; 3.834 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[2]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.181     ; 7.627      ;
; 3.834 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[3]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.181     ; 7.627      ;
; 3.835 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[42]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.179     ; 7.628      ;
; 3.835 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer3|delay_line:underflow0_delay|shift_reg[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.176     ; 7.631      ;
; 3.869 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[31]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.176     ; 7.597      ;
; 3.892 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.157     ; 7.593      ;
; 3.898 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[19]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.179     ; 7.565      ;
; 3.900 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[1]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.183     ; 7.559      ;
; 3.900 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[0]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.183     ; 7.559      ;
; 3.900 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[2]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.183     ; 7.559      ;
; 3.900 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[3]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.183     ; 7.559      ;
; 3.900 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[4]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.183     ; 7.559      ;
; 3.900 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[5]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.183     ; 7.559      ;
; 3.912 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[7]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.185     ; 7.545      ;
; 3.912 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[6]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.185     ; 7.545      ;
; 3.912 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[5]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.185     ; 7.545      ;
; 3.912 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[4]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.185     ; 7.545      ;
; 3.912 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[3]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.185     ; 7.545      ;
; 3.912 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[2]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.185     ; 7.545      ;
; 3.912 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[1]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.185     ; 7.545      ;
; 3.912 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[0]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.185     ; 7.545      ;
; 3.921 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[1]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.183     ; 7.538      ;
; 3.921 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[5]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.183     ; 7.538      ;
; 3.921 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[4]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.183     ; 7.538      ;
; 3.921 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[0]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.183     ; 7.538      ;
; 3.921 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[2]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.183     ; 7.538      ;
; 3.921 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[3]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.183     ; 7.538      ;
+-------+----------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                                                                                                                                                   ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                ; To Node                                                                         ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 10.480 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.139     ; 6.717      ;
; 10.641 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.139     ; 6.556      ;
; 10.684 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.139     ; 6.513      ;
; 10.768 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.087     ; 6.481      ;
; 10.828 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.140     ; 6.368      ;
; 10.835 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.087     ; 6.414      ;
; 10.875 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.086     ; 6.375      ;
; 10.922 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.087     ; 6.327      ;
; 11.035 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.139     ; 6.162      ;
; 11.076 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.087     ; 6.173      ;
; 11.200 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.086     ; 6.050      ;
; 11.240 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.086     ; 6.010      ;
; 11.261 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.086     ; 5.989      ;
; 11.278 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.118     ; 5.940      ;
; 11.280 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.086     ; 5.970      ;
; 11.283 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.140     ; 5.913      ;
; 11.300 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.118     ; 5.918      ;
; 11.305 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.118     ; 5.913      ;
; 11.306 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.141     ; 5.889      ;
; 11.331 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.119     ; 5.886      ;
; 11.337 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.086     ; 5.913      ;
; 11.351 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.086     ; 5.899      ;
; 11.377 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.087     ; 5.872      ;
; 11.414 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.087     ; 5.835      ;
; 11.455 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.086     ; 5.795      ;
; 11.477 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.086     ; 5.773      ;
; 11.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.139     ; 5.694      ;
; 11.506 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.086     ; 5.744      ;
; 11.520 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.118     ; 5.698      ;
; 11.521 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.139     ; 5.676      ;
; 11.523 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.087     ; 5.726      ;
; 11.530 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.086     ; 5.720      ;
; 11.549 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.087     ; 5.700      ;
; 11.549 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.118     ; 5.669      ;
; 11.550 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.086     ; 5.700      ;
; 11.558 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.086     ; 5.692      ;
; 11.585 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.086     ; 5.665      ;
; 11.593 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.086     ; 5.657      ;
; 11.649 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.118     ; 5.569      ;
; 11.660 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.086     ; 5.590      ;
; 11.678 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.087     ; 5.571      ;
; 11.679 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.087     ; 5.570      ;
; 11.680 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.086     ; 5.570      ;
; 11.690 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.139     ; 5.507      ;
; 11.735 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.118     ; 5.483      ;
; 11.750 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.086     ; 5.500      ;
; 11.781 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.119     ; 5.436      ;
; 11.785 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.087     ; 5.464      ;
; 11.795 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.087     ; 5.454      ;
; 11.824 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hsync_reg                                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[0]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 5.490      ;
; 11.824 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hsync_reg                                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[1]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 5.490      ;
; 11.824 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hsync_reg                                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 5.490      ;
; 11.824 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hsync_reg                                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 5.490      ;
; 11.824 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hsync_reg                                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 5.490      ;
; 11.824 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hsync_reg                                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 5.490      ;
; 11.824 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hsync_reg                                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 5.490      ;
; 11.824 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hsync_reg                                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[7]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 5.490      ;
; 11.824 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hsync_reg                                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 5.490      ;
; 11.824 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hsync_reg                                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[9]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 5.490      ;
; 11.824 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hsync_reg                                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 5.490      ;
; 11.861 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.086     ; 5.389      ;
; 11.882 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.086     ; 5.368      ;
; 11.997 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.414     ; 5.051      ;
; 12.006 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.118     ; 5.212      ;
; 12.011 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.086     ; 5.239      ;
; 12.026 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.119     ; 5.191      ;
; 12.047 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.118     ; 5.171      ;
; 12.091 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.087     ; 5.158      ;
; 12.106 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.414     ; 4.942      ;
; 12.132 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.087     ; 5.117      ;
; 12.154 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.088     ; 5.094      ;
; 12.165 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.087     ; 5.084      ;
; 12.173 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.088     ; 5.075      ;
; 12.178 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.087     ; 5.071      ;
; 12.227 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.086     ; 5.023      ;
; 12.306 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.414     ; 4.742      ;
; 12.368 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.139     ; 4.829      ;
; 12.378 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.414     ; 4.670      ;
; 12.415 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.086     ; 4.835      ;
; 12.429 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.414     ; 4.619      ;
; 12.451 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.087     ; 4.798      ;
; 12.453 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.414     ; 4.595      ;
; 12.512 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.086     ; 4.738      ;
; 12.541 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.140     ; 4.655      ;
; 12.579 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.412     ; 4.471      ;
; 12.605 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.414     ; 4.443      ;
; 12.612 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.413     ; 4.437      ;
; 12.729 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.086     ; 4.521      ;
; 12.730 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.087     ; 4.519      ;
; 12.739 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.413     ; 4.310      ;
; 12.742 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.088     ; 4.506      ;
; 12.743 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.087     ; 4.506      ;
; 12.762 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.088     ; 4.486      ;
; 12.843 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.139     ; 4.354      ;
; 12.976 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.413     ; 4.073      ;
; 12.977 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.413     ; 4.072      ;
; 12.990 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.086     ; 4.260      ;
; 12.994 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.139     ; 4.203      ;
; 13.012 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.087     ; 4.237      ;
; 13.056 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.118     ; 4.162      ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                    ;
+-------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                       ; To Node                                                   ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 0.402 ; sdram_ctrl:sdram_controller|r_refr_act                                                                          ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.403 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; sdram_ctrl:sdram_controller|r_rd_act                                                                            ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; sdram_ctrl:sdram_controller|r_wr_act                                                                            ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                                      ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                           ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                                                                        ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; sdram_request_complete_reg                                                                                      ; sdram_request_complete_reg                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.418 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.684      ;
; 0.418 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.684      ;
; 0.488 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.754      ;
; 0.501 ; seq_reg[11]                                                                                                     ; seq_reg[0]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.767      ;
; 0.535 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.801      ;
; 0.535 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.801      ;
; 0.631 ; sdram_ctrl:sdram_controller|r_rd_reg                                                                            ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.897      ;
; 0.631 ; sdram_ctrl:sdram_controller|r_rd_reg                                                                            ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.897      ;
; 0.639 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[19] ; ram_di_reg[3]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.156      ; 1.010      ;
; 0.639 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[20] ; ram_di_reg[4]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.156      ; 1.010      ;
; 0.639 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[25] ; ram_di_reg[9]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.156      ; 1.010      ;
; 0.639 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[28] ; ram_di_reg[12]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.156      ; 1.010      ;
; 0.684 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.950      ;
; 0.685 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.951      ;
; 0.686 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.952      ;
; 0.687 ; seq_reg[8]                                                                                                      ; seq_reg[9]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.953      ;
; 0.687 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.953      ;
; 0.688 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.954      ;
; 0.689 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.955      ;
; 0.690 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.956      ;
; 0.691 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.957      ;
; 0.692 ; sdram_ctrl:sdram_controller|r_psel_dly[0]                                                                       ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.958      ;
; 0.692 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.958      ;
; 0.693 ; seq_reg[6]                                                                                                      ; seq_reg[7]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.959      ;
; 0.694 ; seq_reg[4]                                                                                                      ; seq_reg[5]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.961      ;
; 0.698 ; sdram_ctrl:sdram_controller|r_rd_act                                                                            ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.964      ;
; 0.701 ; seq_reg[0]                                                                                                      ; seq_reg[1]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.967      ;
; 0.702 ; sdram_ctrl:sdram_controller|r_refr_act                                                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.969      ;
; 0.712 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.978      ;
; 0.744 ; sdram_ctrl:sdram_controller|r_rd_act                                                                            ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.010      ;
; 0.766 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[18] ; ram_di_reg[2]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.155      ; 1.136      ;
; 0.782 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[17] ; ram_di_reg[1]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.157      ; 1.154      ;
; 0.787 ; sdram_ctrl:sdram_controller|r_refr_req                                                                          ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.053      ;
; 0.793 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                                      ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.059      ;
; 0.802 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[16] ; ram_di_reg[0]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.156      ; 1.173      ;
; 0.803 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[21] ; ram_di_reg[5]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.156      ; 1.174      ;
; 0.804 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                                       ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.070      ;
; 0.811 ; seq_reg[10]                                                                                                     ; seq_reg[11]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.077      ;
; 0.814 ; sdram_ctrl:sdram_controller|r_refr_req                                                                          ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.080      ;
; 0.864 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                                      ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.130      ;
; 0.867 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.133      ;
; 0.868 ; seq_reg[9]                                                                                                      ; seq_reg[10]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.134      ;
; 0.871 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[31] ; ram_di_reg[15]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.156      ; 1.242      ;
; 0.879 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.145      ;
; 0.880 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[22] ; ram_di_reg[6]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.156      ; 1.251      ;
; 0.884 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                                       ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.150      ;
; 0.886 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.152      ;
; 0.897 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[23] ; ram_di_reg[7]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.156      ; 1.268      ;
; 0.906 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[24] ; ram_di_reg[8]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.156      ; 1.277      ;
; 0.906 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[27] ; ram_di_reg[11]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.156      ; 1.277      ;
; 0.906 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[29] ; ram_di_reg[13]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.156      ; 1.277      ;
; 0.907 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[30] ; ram_di_reg[14]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.156      ; 1.278      ;
; 0.932 ; sdram_ctrl:sdram_controller|r_wr_act                                                                            ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.198      ;
; 0.969 ; sdram_ctrl:sdram_controller|r_refr_req                                                                          ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.235      ;
; 0.979 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[11] ; ram_di_reg[11]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.156      ; 1.350      ;
; 1.006 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.272      ;
; 1.006 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.272      ;
; 1.006 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.272      ;
; 1.007 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.273      ;
; 1.007 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.273      ;
; 1.010 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.276      ;
; 1.010 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.276      ;
; 1.012 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.278      ;
; 1.021 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.287      ;
; 1.023 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.289      ;
; 1.024 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.290      ;
; 1.027 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.293      ;
; 1.029 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[26] ; ram_di_reg[10]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.155      ; 1.399      ;
; 1.056 ; sdram_ctrl:sdram_controller|r_refr_act                                                                          ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.314      ;
; 1.057 ; sdram_ctrl:sdram_controller|r_refr_act                                                                          ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.315      ;
; 1.099 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.365      ;
; 1.099 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[5]  ; ram_di_reg[5]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.163      ; 1.477      ;
; 1.101 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.367      ;
; 1.104 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.370      ;
; 1.108 ; seq_reg[5]                                                                                                      ; seq_reg[6]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.374      ;
; 1.108 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[13] ; ram_di_reg[13]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.155      ; 1.478      ;
; 1.113 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                                                                       ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.379      ;
; 1.114 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.380      ;
; 1.121 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                                       ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.082      ; 1.398      ;
; 1.128 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.394      ;
; 1.128 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.394      ;
; 1.129 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.395      ;
; 1.129 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.395      ;
; 1.132 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.398      ;
; 1.132 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.398      ;
; 1.135 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[10] ; ram_di_reg[10]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.155      ; 1.505      ;
; 1.139 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[14] ; ram_di_reg[14]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.156      ; 1.510      ;
; 1.142 ; seq_reg[2]                                                                                                      ; seq_reg[3]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.409      ;
+-------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                            ;
+-------+--------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                        ; To Node                                                                                                                                          ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[20]                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[20]                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[18]                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[18]                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[19]                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[19]                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[22]                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[22]                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[21]                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[21]                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cyclePreRead             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cyclePreRead             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Creg                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Creg                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Vreg                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Vreg                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[13]                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[13]                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|antic_fetch_real_reg                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|antic_fetch_real_reg                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[23]                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[23]                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[1]   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[1]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[2]   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[2]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[3]   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[3]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[16]                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[16]                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[9]                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[9]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[12]                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[12]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[13]                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[13]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[15]                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[15]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[2]                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[2]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[5]                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[5]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[7]                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[7]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[3]                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[3]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[4]                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[4]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[6]                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[6]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vblank_reg                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vblank_reg                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_ready_reg                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_ready_reg                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|assert_data                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|assert_data                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|ss_n[0]                                                                           ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|ss_n[0]                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[2]                                                                                       ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[2]                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[3]                                                                                       ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[3]                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[2]                                                                                ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[2]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[0]                                                                                ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[0]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[1]                                                                                ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[1]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[3]                                                                                ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[3]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[4]                                                                                ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[4]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[5]                                                                                ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[5]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[6]                                                                                ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[6]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[7]                                                                                ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[7]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer2|delay_line:underflow0_delay|shift_reg[0]                       ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer2|delay_line:underflow0_delay|shift_reg[0]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[2]                                                                                ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[2]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[3]                                                                                ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[3]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[5]                                                                                ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[5]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer3|delay_line:underflow0_delay|shift_reg[0]                       ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer3|delay_line:underflow0_delay|shift_reg[0]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[2]                                                                                ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[2]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[3]                                                                                ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[3]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0]                       ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer1|delay_line:underflow0_delay|shift_reg[0]                       ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer1|delay_line:underflow0_delay|shift_reg[0]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_clock_reg                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_clock_reg                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_bitcount_reg[0]                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_bitcount_reg[0]                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serial_out_reg                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serial_out_reg                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|twotone_reg                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|twotone_reg                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|idle_reg[1]                                                                                 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|idle_reg[1]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|idle_reg[2]                                                                                 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|idle_reg[2]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|idle_reg[3]                                                                                 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|idle_reg[3]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|bitcount_reg[2]                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|bitcount_reg[2]                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|bitcount_reg[1]                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|bitcount_reg[1]                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|bitcount_reg[3]                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|bitcount_reg[3]                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|bitcount_reg[0]                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|bitcount_reg[0]                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[12]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[12]                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[50]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[50]                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[62]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[62]                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[58]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[58]                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[3]                                                                                                    ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[3]                                                                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[59]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[59]                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[41]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[41]                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[65]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[65]                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[51]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[51]                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[43]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[43]                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[53]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[53]                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[61]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[61]                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[35]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[35]                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[60]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[60]                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[5]                                                                                                    ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[5]                                                                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[33]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[33]                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[54]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[54]                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[4]                                                                                                    ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[4]                                                                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[26]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[26]                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[93]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[93]                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[84]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[84]                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[29]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[29]                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[27]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[27]                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[30]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[30]                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[22]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[22]                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[28]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[28]                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[91]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[91]                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[21]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[21]                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|state_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|state_reg[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|state_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|state_reg[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[0]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[0]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[1]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[1]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[5]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[5]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|first_line_of_instruction_reg                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|first_line_of_instruction_reg                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vscrol_last_enabled_reg                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vscrol_last_enabled_reg                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vsync_reg                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vsync_reg                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[4]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[4]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[11]                                                                                                   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[11]                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
+-------+--------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                                                                                          ;
+-------+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                       ; To Node                                                                                         ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 0.402 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|buffer_select_reg                     ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|buffer_select_reg                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_hsync_reg                         ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_hsync_reg                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.669      ;
; 0.417 ; half_scandouble_enable_reg                                                                      ; half_scandouble_enable_reg                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.684      ;
; 0.457 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|hsync_in_reg                          ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|buffer_select_reg                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.724      ;
; 0.468 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[46]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[45]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.735      ;
; 0.469 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[10]                 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[10]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.736      ;
; 0.469 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[108] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[107] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.736      ;
; 0.469 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[105] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[104] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.736      ;
; 0.469 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[56]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[55]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.736      ;
; 0.469 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[15]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[14]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.736      ;
; 0.469 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[2]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[1]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.736      ;
; 0.470 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[121] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[120] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.737      ;
; 0.470 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[113] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[112] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.737      ;
; 0.470 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[111] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[110] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.737      ;
; 0.470 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[109] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[108] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.737      ;
; 0.470 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[106] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[105] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.737      ;
; 0.470 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[104] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[103] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.737      ;
; 0.470 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[92]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[91]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.737      ;
; 0.470 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[86]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[85]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.737      ;
; 0.470 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[79]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[78]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.737      ;
; 0.470 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[77]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[76]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.737      ;
; 0.470 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[73]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[72]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.737      ;
; 0.470 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[68]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[67]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.737      ;
; 0.470 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[61]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[60]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.737      ;
; 0.470 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[58]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[57]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.737      ;
; 0.470 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[50]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[49]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.737      ;
; 0.470 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[7]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[6]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.737      ;
; 0.470 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[6]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[5]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.737      ;
; 0.470 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[4]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[3]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.737      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[127] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[126] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.738      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[125] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[124] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.738      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[123] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[122] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.738      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[122] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[121] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.738      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[120] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[119] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.738      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[107] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[106] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.738      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[102] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[101] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.738      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[101] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[100] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.738      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[94]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[93]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.738      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[91]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[90]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.738      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[90]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[89]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.738      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[88]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[87]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.738      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[87]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[86]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.738      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[85]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[84]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.738      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[83]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[82]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.738      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[78]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[77]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.738      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[75]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[74]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.738      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[63]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[62]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.738      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[60]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[59]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.738      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[59]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[58]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.738      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[57]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[56]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.738      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[51]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[50]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.738      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[48]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[47]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.738      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[47]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[46]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.738      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[43]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[42]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.738      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[42]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[41]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.738      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[40]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[39]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[27]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[26]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[25]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[24]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[14]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[13]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.738      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[12]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[11]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.738      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[11]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[10]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[124] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[123] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.739      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[116] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[115] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.739      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[76]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[75]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.739      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[71]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[70]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.739      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[35]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[34]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[34]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[33]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[33]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[32]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[31]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[30]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[26]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[25]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[23]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[22]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[22]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[21]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[17]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[16]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[8]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[7]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.739      ;
; 0.473 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[55]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[54]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.740      ;
; 0.473 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[36]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[35]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.739      ;
; 0.473 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[30]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[29]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.739      ;
; 0.473 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[24]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[23]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.739      ;
; 0.473 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[20]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[19]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.739      ;
; 0.608 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[99]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[98]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.874      ;
; 0.609 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[100] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[99]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.876      ;
; 0.610 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[16]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[15]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.876      ;
; 0.610 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[13]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[12]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.877      ;
; 0.611 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[32]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[31]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.877      ;
; 0.614 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[41]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[40]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.881      ;
; 0.621 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[84]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[83]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.073      ; 0.889      ;
; 0.621 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[53]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[52]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.888      ;
; 0.622 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[82]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[81]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.889      ;
; 0.645 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[117] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[116] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.912      ;
; 0.645 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[115] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[114] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.912      ;
; 0.645 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[81]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[80]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.912      ;
; 0.645 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[74]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[73]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.912      ;
; 0.645 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[72]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[71]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.912      ;
; 0.645 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[65]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[64]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.912      ;
; 0.645 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[49]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[48]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.912      ;
; 0.646 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[126] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[125] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.913      ;
; 0.646 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[118] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[117] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.913      ;
; 0.646 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[97]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[96]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.913      ;
; 0.646 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[95]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[94]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.913      ;
; 0.646 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[64]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[63]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.913      ;
+-------+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                      ;
+-------+---------------------------------------+---------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                                                                   ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+---------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.160     ; 5.127      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[31]                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.163     ; 5.124      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[31]                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.163     ; 5.124      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.159     ; 5.128      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[1]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.168     ; 5.119      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[0]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.168     ; 5.119      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_8BIT_WRITE_ENABLE_reg               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.153     ; 5.134      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[13]                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.168     ; 5.119      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[20]                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.168     ; 5.119      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[6] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.166     ; 5.121      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[5] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.166     ; 5.121      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.166     ; 5.121      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[3] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.166     ; 5.121      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[2] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.166     ; 5.121      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.166     ; 5.121      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.166     ; 5.121      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[23]                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.163     ; 5.124      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[23]                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.163     ; 5.124      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[19]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.153     ; 5.134      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[13]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.157     ; 5.130      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|skctl_reg[3]         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.168     ; 5.119      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|skctl_reg[5]         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.168     ; 5.119      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|skctl_reg[4]         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.168     ; 5.119      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[2]         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.168     ; 5.119      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[0]         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.168     ; 5.119      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[1]         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.168     ; 5.119      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[3]         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.168     ; 5.119      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[4]         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.168     ; 5.119      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[5]         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.168     ; 5.119      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[6]         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.168     ; 5.119      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[7]         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.168     ; 5.119      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|skctl_reg[6]         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.168     ; 5.119      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|skctl_reg[7]         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.168     ; 5.119      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[11]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.160     ; 5.127      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[9]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.156     ; 5.131      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[10]                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.157     ; 5.130      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[25]                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.164     ; 5.123      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[30]                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.168     ; 5.119      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[30]                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.163     ; 5.124      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[30]                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.163     ; 5.124      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[30]                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.149     ; 5.138      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[26]                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.163     ; 5.124      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[26]                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.163     ; 5.124      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[26]                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.149     ; 5.138      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[28]                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.168     ; 5.119      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[28]                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.163     ; 5.124      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[28]                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.163     ; 5.124      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.161     ; 5.126      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[10]                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.148     ; 5.139      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[12]                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.156     ; 5.131      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[12]                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.148     ; 5.139      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.154     ; 5.133      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[9]                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.148     ; 5.139      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[9]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.159     ; 5.128      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[31]                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.150     ; 5.137      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[6]                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.149     ; 5.138      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[22]                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.149     ; 5.138      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[11]                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.148     ; 5.139      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[11]                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.156     ; 5.131      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[3]                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.149     ; 5.138      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[29]                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.168     ; 5.119      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[29]                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.163     ; 5.124      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[29]                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.163     ; 5.124      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[20]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.153     ; 5.134      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|irqst_reg[0]         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.168     ; 5.119      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[0]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.159     ; 5.128      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[18]                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.149     ; 5.138      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[17]                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.149     ; 5.138      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[16]                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.149     ; 5.138      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[24]                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.163     ; 5.124      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[24]                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.163     ; 5.124      ;
; 6.355 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[24]                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.149     ; 5.138      ;
; 6.356 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[4]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.172     ; 5.114      ;
; 6.356 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[31]                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.163     ; 5.123      ;
; 6.356 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[31]                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.163     ; 5.123      ;
; 6.356 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[12]                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.166     ; 5.120      ;
; 6.356 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_READ_reg                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.164     ; 5.122      ;
; 6.356 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[23]                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.151     ; 5.135      ;
; 6.356 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[23]                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.170     ; 5.116      ;
; 6.356 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[13]           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.177     ; 5.109      ;
; 6.356 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[12]           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.177     ; 5.109      ;
; 6.356 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[0]                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.171     ; 5.115      ;
; 6.356 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[0]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.166     ; 5.120      ;
; 6.356 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[1]                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.169     ; 5.117      ;
; 6.356 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[1]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.166     ; 5.120      ;
; 6.356 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[2]                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.169     ; 5.117      ;
; 6.356 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[2]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.166     ; 5.120      ;
; 6.356 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[3]                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.169     ; 5.117      ;
; 6.356 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[3]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.164     ; 5.122      ;
; 6.356 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[4]                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.169     ; 5.117      ;
; 6.356 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[4]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.164     ; 5.122      ;
; 6.356 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[5]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.166     ; 5.120      ;
; 6.356 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[6]                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.169     ; 5.117      ;
; 6.356 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[6]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.166     ; 5.120      ;
; 6.356 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[7]                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.171     ; 5.115      ;
; 6.356 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[7]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.166     ; 5.120      ;
; 6.356 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[8]                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.166     ; 5.120      ;
; 6.356 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[8]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.164     ; 5.122      ;
; 6.356 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[9]                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.166     ; 5.120      ;
; 6.356 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[9]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.164     ; 5.122      ;
+-------+---------------------------------------+---------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                       ;
+-------+------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                                   ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 7.792 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[5]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.181     ; 3.543      ;
; 7.793 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[0]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.193     ; 3.530      ;
; 7.793 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[1]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.193     ; 3.530      ;
; 7.793 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[2]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.193     ; 3.530      ;
; 7.793 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[3]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.193     ; 3.530      ;
; 7.793 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[4]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.179     ; 3.544      ;
; 7.793 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[6]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.181     ; 3.542      ;
; 7.793 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[7]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.181     ; 3.542      ;
; 7.793 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[8]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.180     ; 3.543      ;
; 7.793 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.191     ; 3.532      ;
; 7.793 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.193     ; 3.530      ;
; 7.793 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.180     ; 3.543      ;
; 7.793 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.193     ; 3.530      ;
; 7.800 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[7]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.360     ; 3.345      ;
; 7.800 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[15]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.342     ; 3.363      ;
; 7.800 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[1]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.360     ; 3.345      ;
; 7.800 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[9]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.354     ; 3.351      ;
; 7.800 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[2]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.360     ; 3.345      ;
; 7.800 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[0]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.360     ; 3.345      ;
; 7.800 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[8]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.348     ; 3.357      ;
; 7.800 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[13]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.342     ; 3.363      ;
; 7.800 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[14]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.342     ; 3.363      ;
; 7.800 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[3]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.364     ; 3.341      ;
; 7.801 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[4]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.367     ; 3.337      ;
; 7.801 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[5]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.365     ; 3.339      ;
; 7.801 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[6]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.361     ; 3.343      ;
; 7.811 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[11]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.343     ; 3.351      ;
; 7.811 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[10]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.343     ; 3.351      ;
; 7.811 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[12]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.343     ; 3.351      ;
; 7.837 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[0]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.240     ; 3.439      ;
; 7.837 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[1]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.240     ; 3.439      ;
; 7.837 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[2]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.240     ; 3.439      ;
; 7.837 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[3]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.244     ; 3.435      ;
; 7.837 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[7]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.240     ; 3.439      ;
; 7.837 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[8]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.228     ; 3.451      ;
; 7.837 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[9]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.234     ; 3.445      ;
; 7.837 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[13]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.222     ; 3.457      ;
; 7.837 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[14]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.222     ; 3.457      ;
; 7.837 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[15]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.222     ; 3.457      ;
; 7.838 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[4]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.247     ; 3.431      ;
; 7.838 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[5]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.245     ; 3.433      ;
; 7.838 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[6]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.241     ; 3.437      ;
; 7.848 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[10]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.223     ; 3.445      ;
; 7.848 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[11]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.223     ; 3.445      ;
; 7.848 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[12]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.223     ; 3.445      ;
; 7.854 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.164     ; 3.624      ;
; 7.855 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.168     ; 3.619      ;
; 7.855 ; sdram_reset_ctrl_n_reg ; ram_do_reg[14]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.168     ; 3.619      ;
; 7.904 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.168     ; 3.570      ;
; 7.904 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.168     ; 3.570      ;
; 7.904 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.168     ; 3.570      ;
; 7.904 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.168     ; 3.570      ;
; 7.904 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.168     ; 3.570      ;
; 7.904 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.168     ; 3.570      ;
; 7.904 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.168     ; 3.570      ;
; 7.904 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.168     ; 3.570      ;
; 7.904 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.168     ; 3.570      ;
; 8.025 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.191     ; 3.300      ;
; 8.025 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.191     ; 3.300      ;
; 8.025 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.191     ; 3.300      ;
; 8.025 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.191     ; 3.300      ;
; 8.318 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.172     ; 3.152      ;
; 8.318 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.172     ; 3.152      ;
; 8.318 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.172     ; 3.152      ;
; 8.318 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.172     ; 3.152      ;
; 8.318 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.172     ; 3.152      ;
; 8.318 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.172     ; 3.152      ;
; 8.318 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.172     ; 3.152      ;
; 8.318 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.172     ; 3.152      ;
; 8.318 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.172     ; 3.152      ;
; 8.318 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.172     ; 3.152      ;
; 8.318 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.183     ; 3.141      ;
; 8.318 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.173     ; 3.151      ;
; 8.318 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.183     ; 3.141      ;
; 8.318 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.183     ; 3.141      ;
; 8.318 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.183     ; 3.141      ;
; 8.318 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.173     ; 3.151      ;
; 8.318 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.183     ; 3.141      ;
; 8.318 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.183     ; 3.141      ;
; 8.318 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.173     ; 3.151      ;
; 8.318 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.165     ; 3.159      ;
; 8.318 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.173     ; 3.151      ;
; 8.318 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.171     ; 3.153      ;
; 8.318 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.171     ; 3.153      ;
; 8.318 ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.171     ; 3.153      ;
; 8.318 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.171     ; 3.153      ;
; 8.318 ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.171     ; 3.153      ;
; 8.318 ; sdram_reset_ctrl_n_reg ; ram_di_reg[15]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.171     ; 3.153      ;
; 8.318 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.173     ; 3.151      ;
; 8.318 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.173     ; 3.151      ;
; 8.318 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.173     ; 3.151      ;
; 8.318 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.165     ; 3.159      ;
; 8.319 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.159     ; 3.164      ;
; 8.319 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.159     ; 3.164      ;
; 8.319 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.159     ; 3.164      ;
; 8.319 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.159     ; 3.164      ;
; 8.319 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.159     ; 3.164      ;
; 8.319 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.159     ; 3.164      ;
; 8.319 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.175     ; 3.148      ;
; 8.319 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.175     ; 3.148      ;
+-------+------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                         ;
+--------+-------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node         ; To Node                                                                                         ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 12.524 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vsync_reg                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.178     ; 4.634      ;
; 12.524 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.177     ; 4.635      ;
; 12.524 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.177     ; 4.635      ;
; 12.525 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|hsync_reg                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.178     ; 4.633      ;
; 12.525 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.177     ; 4.634      ;
; 12.525 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.177     ; 4.634      ;
; 12.525 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.177     ; 4.634      ;
; 12.525 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.177     ; 4.634      ;
; 12.525 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.178     ; 4.633      ;
; 12.525 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.178     ; 4.633      ;
; 12.546 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.230     ; 4.560      ;
; 12.546 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.230     ; 4.560      ;
; 12.548 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.209     ; 4.579      ;
; 12.562 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.209     ; 4.565      ;
; 13.048 ; sdram_reset_n_reg ; half_scandouble_enable_reg                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.165     ; 4.249      ;
; 13.048 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.165     ; 4.249      ;
; 13.048 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[1]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.165     ; 4.249      ;
; 13.048 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[2]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.165     ; 4.249      ;
; 13.048 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[3]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.165     ; 4.249      ;
; 13.048 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[4]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.165     ; 4.249      ;
; 13.048 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[5]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.165     ; 4.249      ;
; 13.048 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[6]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.165     ; 4.249      ;
; 13.048 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[7]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.165     ; 4.249      ;
; 13.048 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[8]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.165     ; 4.249      ;
; 13.048 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[9]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.165     ; 4.249      ;
; 13.048 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[10]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.165     ; 4.249      ;
; 13.048 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.160     ; 4.254      ;
; 13.048 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.160     ; 4.254      ;
; 13.048 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.160     ; 4.254      ;
; 13.048 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.160     ; 4.254      ;
; 13.048 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.159     ; 4.255      ;
; 13.048 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.160     ; 4.254      ;
; 13.048 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.160     ; 4.254      ;
; 13.048 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.160     ; 4.254      ;
; 13.048 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.160     ; 4.254      ;
; 13.048 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[10]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.161     ; 4.253      ;
; 13.048 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.161     ; 4.253      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|buffer_select_reg                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.162     ; 4.242      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[127] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.161     ; 4.243      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[126] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.161     ; 4.243      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[125] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.161     ; 4.243      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[124] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.161     ; 4.243      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[123] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.161     ; 4.243      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[122] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.161     ; 4.243      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[121] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.161     ; 4.243      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[120] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.161     ; 4.243      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[119] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.161     ; 4.243      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[118] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.161     ; 4.243      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[117] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.161     ; 4.243      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[116] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.161     ; 4.243      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[115] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.161     ; 4.243      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[114] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.161     ; 4.243      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[113] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.160     ; 4.244      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[112] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.160     ; 4.244      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[111] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.160     ; 4.244      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[110] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.160     ; 4.244      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[109] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.160     ; 4.244      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[108] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.160     ; 4.244      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[107] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.160     ; 4.244      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[106] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.160     ; 4.244      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[105] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.160     ; 4.244      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[104] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.160     ; 4.244      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[103] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.160     ; 4.244      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[102] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.160     ; 4.244      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[101] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.160     ; 4.244      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[100] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.160     ; 4.244      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[99]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.160     ; 4.244      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[98]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.161     ; 4.243      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[97]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.161     ; 4.243      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[96]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.161     ; 4.243      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[95]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.161     ; 4.243      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[94]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.161     ; 4.243      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[93]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.161     ; 4.243      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[92]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.161     ; 4.243      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[91]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.161     ; 4.243      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[90]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.161     ; 4.243      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[89]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.161     ; 4.243      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[88]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.161     ; 4.243      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[87]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.161     ; 4.243      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[86]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.161     ; 4.243      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[85]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.161     ; 4.243      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[84]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.161     ; 4.243      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[83]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.160     ; 4.244      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[82]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.160     ; 4.244      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[81]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.160     ; 4.244      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[80]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.160     ; 4.244      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[79]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.160     ; 4.244      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[78]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.160     ; 4.244      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[77]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.160     ; 4.244      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[76]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.160     ; 4.244      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[75]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.160     ; 4.244      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[74]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.160     ; 4.244      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[73]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.160     ; 4.244      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[72]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.160     ; 4.244      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[71]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.160     ; 4.244      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[70]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.160     ; 4.244      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[69]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.160     ; 4.244      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[68]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.160     ; 4.244      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[67]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.160     ; 4.244      ;
; 13.058 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[66]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.159     ; 4.245      ;
+--------+-------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                       ;
+-------+------------------------+----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                                  ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 2.493 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.176      ; 2.884      ;
; 2.493 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.176      ; 2.884      ;
; 2.493 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.176      ; 2.884      ;
; 2.493 ; sdram_reset_ctrl_n_reg ; seq_reg[5]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.176      ; 2.884      ;
; 2.493 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.176      ; 2.884      ;
; 2.493 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.176      ; 2.884      ;
; 2.493 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.176      ; 2.884      ;
; 2.494 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.175      ; 2.884      ;
; 2.494 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.175      ; 2.884      ;
; 2.494 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[0]                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.175      ; 2.884      ;
; 2.494 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[1]                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.175      ; 2.884      ;
; 2.504 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.167      ; 2.886      ;
; 2.504 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.167      ; 2.886      ;
; 2.504 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.169      ; 2.888      ;
; 2.504 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.169      ; 2.888      ;
; 2.504 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.169      ; 2.888      ;
; 2.504 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.167      ; 2.886      ;
; 2.504 ; sdram_reset_ctrl_n_reg ; ram_do_reg[5]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.167      ; 2.886      ;
; 2.504 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.153      ; 2.872      ;
; 2.504 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.153      ; 2.872      ;
; 2.504 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.153      ; 2.872      ;
; 2.504 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.153      ; 2.872      ;
; 2.504 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_act                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.153      ; 2.872      ;
; 2.504 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.153      ; 2.872      ;
; 2.504 ; sdram_reset_ctrl_n_reg ; ram_do_reg[15]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.167      ; 2.886      ;
; 2.504 ; sdram_reset_ctrl_n_reg ; ram_do_reg[25]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.169      ; 2.888      ;
; 2.504 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.167      ; 2.886      ;
; 2.504 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.169      ; 2.888      ;
; 2.504 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.169      ; 2.888      ;
; 2.504 ; sdram_reset_ctrl_n_reg ; ram_do_reg[12]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.167      ; 2.886      ;
; 2.504 ; sdram_reset_ctrl_n_reg ; ram_do_reg[9]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.169      ; 2.888      ;
; 2.504 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.167      ; 2.886      ;
; 2.504 ; sdram_reset_ctrl_n_reg ; ram_do_reg[11]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.167      ; 2.886      ;
; 2.504 ; sdram_reset_ctrl_n_reg ; ram_do_reg[19]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.167      ; 2.886      ;
; 2.504 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.167      ; 2.886      ;
; 2.504 ; sdram_reset_ctrl_n_reg ; ram_do_reg[13]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.167      ; 2.886      ;
; 2.504 ; sdram_reset_ctrl_n_reg ; ram_do_reg[8]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.169      ; 2.888      ;
; 2.504 ; sdram_reset_ctrl_n_reg ; ram_do_reg[20]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.167      ; 2.886      ;
; 2.504 ; sdram_reset_ctrl_n_reg ; ram_di_reg[6]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.163      ; 2.882      ;
; 2.504 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.163      ; 2.882      ;
; 2.504 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.163      ; 2.882      ;
; 2.504 ; sdram_reset_ctrl_n_reg ; ram_di_reg[14]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.163      ; 2.882      ;
; 2.505 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.164      ; 2.884      ;
; 2.505 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.164      ; 2.884      ;
; 2.505 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.164      ; 2.884      ;
; 2.505 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.164      ; 2.884      ;
; 2.505 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.164      ; 2.884      ;
; 2.505 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.164      ; 2.884      ;
; 2.505 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.164      ; 2.884      ;
; 2.505 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.164      ; 2.884      ;
; 2.505 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.164      ; 2.884      ;
; 2.505 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.164      ; 2.884      ;
; 2.505 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.163      ; 2.883      ;
; 2.505 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.163      ; 2.883      ;
; 2.505 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.163      ; 2.883      ;
; 2.505 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.163      ; 2.883      ;
; 2.505 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.164      ; 2.884      ;
; 2.505 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.165      ; 2.885      ;
; 2.505 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.164      ; 2.884      ;
; 2.505 ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.164      ; 2.884      ;
; 2.505 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.165      ; 2.885      ;
; 2.505 ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.165      ; 2.885      ;
; 2.505 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.165      ; 2.885      ;
; 2.505 ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.165      ; 2.885      ;
; 2.505 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.164      ; 2.884      ;
; 2.505 ; sdram_reset_ctrl_n_reg ; ram_di_reg[11]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.164      ; 2.884      ;
; 2.505 ; sdram_reset_ctrl_n_reg ; ram_di_reg[12]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.164      ; 2.884      ;
; 2.505 ; sdram_reset_ctrl_n_reg ; ram_di_reg[15]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.165      ; 2.885      ;
; 2.505 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.163      ; 2.883      ;
; 2.505 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.163      ; 2.883      ;
; 2.505 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.163      ; 2.883      ;
; 2.506 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.177      ; 2.898      ;
; 2.506 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.177      ; 2.898      ;
; 2.506 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.177      ; 2.898      ;
; 2.506 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.177      ; 2.898      ;
; 2.506 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.177      ; 2.898      ;
; 2.506 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.177      ; 2.898      ;
; 2.506 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.172      ; 2.893      ;
; 2.506 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.172      ; 2.893      ;
; 2.507 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.161      ; 2.883      ;
; 2.507 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.161      ; 2.883      ;
; 2.507 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.161      ; 2.883      ;
; 2.507 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.161      ; 2.883      ;
; 2.507 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.161      ; 2.883      ;
; 2.507 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.165      ; 2.887      ;
; 2.719 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.150      ; 3.001      ;
; 2.719 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.150      ; 3.001      ;
; 2.720 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.150      ; 3.002      ;
; 2.720 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.150      ; 3.002      ;
; 2.853 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.168      ; 3.236      ;
; 2.853 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.168      ; 3.236      ;
; 2.853 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.168      ; 3.236      ;
; 2.853 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.168      ; 3.236      ;
; 2.853 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.168      ; 3.236      ;
; 2.853 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.168      ; 3.236      ;
; 2.853 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.168      ; 3.236      ;
; 2.853 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.168      ; 3.236      ;
; 2.853 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.168      ; 3.236      ;
; 2.904 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.168      ; 3.287      ;
; 2.904 ; sdram_reset_ctrl_n_reg ; ram_do_reg[14]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.168      ; 3.287      ;
+-------+------------------------+----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                         ;
+-------+-------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node         ; To Node                                                                                         ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|buffer_select_reg                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.175      ; 3.802      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[127] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.176      ; 3.803      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[126] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.176      ; 3.803      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[125] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.176      ; 3.803      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[124] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.176      ; 3.803      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[123] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.176      ; 3.803      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[122] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.176      ; 3.803      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[121] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.176      ; 3.803      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[120] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.176      ; 3.803      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[119] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.176      ; 3.803      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[118] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.176      ; 3.803      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[117] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.176      ; 3.803      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[116] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.176      ; 3.803      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[115] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.176      ; 3.803      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[114] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.176      ; 3.803      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[113] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 3.804      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[112] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 3.804      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[111] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 3.804      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[110] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 3.804      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[109] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 3.804      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[108] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 3.804      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[107] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 3.804      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[106] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 3.804      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[105] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 3.804      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[104] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 3.804      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[103] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 3.804      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[102] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 3.804      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[101] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 3.804      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[100] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 3.804      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[99]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 3.804      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[98]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.176      ; 3.803      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[97]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.176      ; 3.803      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[96]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.176      ; 3.803      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[95]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.176      ; 3.803      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[94]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.176      ; 3.803      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[93]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.176      ; 3.803      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[92]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.176      ; 3.803      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[91]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.176      ; 3.803      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[90]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.176      ; 3.803      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[89]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.176      ; 3.803      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[88]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.176      ; 3.803      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[87]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.176      ; 3.803      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[86]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.176      ; 3.803      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[85]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.176      ; 3.803      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[84]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.176      ; 3.803      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[83]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 3.804      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[82]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 3.804      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[81]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 3.804      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[80]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 3.804      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[79]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 3.804      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[78]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 3.804      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[77]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 3.804      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[76]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 3.804      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[75]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 3.804      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[74]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 3.804      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[73]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 3.804      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[72]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 3.804      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[71]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 3.804      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[70]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 3.804      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[69]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 3.804      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[68]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 3.804      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[67]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.177      ; 3.804      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[66]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 3.805      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[65]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 3.805      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[64]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 3.805      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[63]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 3.805      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[62]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 3.805      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[61]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 3.805      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[60]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 3.805      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[59]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 3.805      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[58]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 3.805      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[57]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 3.805      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[56]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 3.805      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[55]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 3.805      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[54]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 3.805      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[53]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 3.805      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[52]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 3.805      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[51]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 3.805      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[50]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 3.805      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[49]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 3.805      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[48]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 3.805      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[47]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 3.805      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[46]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 3.805      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[45]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 3.805      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[44]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 3.805      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[43]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 3.805      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[42]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 3.805      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[41]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 3.805      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[15]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 3.805      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[14]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 3.805      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[13]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 3.805      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[12]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 3.805      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[11]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 3.805      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[10]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 3.805      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[9]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 3.805      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[8]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 3.805      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[7]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 3.805      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[6]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 3.805      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[5]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 3.805      ;
; 3.412 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[4]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.178      ; 3.805      ;
+-------+-------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                             ;
+-------+---------------------------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                                                                                         ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 4.369 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|state                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.161      ; 4.745      ;
; 4.369 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|busy                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.161      ; 4.745      ;
; 4.369 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|ss_n[0]                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.161      ; 4.745      ;
; 4.369 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[5]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.175      ; 4.759      ;
; 4.369 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[6]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.175      ; 4.759      ;
; 4.370 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[5]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.177      ; 4.762      ;
; 4.370 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[2]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.177      ; 4.762      ;
; 4.370 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[3]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.177      ; 4.762      ;
; 4.370 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[15]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.173      ; 4.758      ;
; 4.370 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|delay_line:serout_clock_delay|shift_reg[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.162      ; 4.747      ;
; 4.370 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|delay_line:serout_clock_delay|shift_reg[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.162      ; 4.747      ;
; 4.370 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_clock_reg                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.162      ; 4.747      ;
; 4.370 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_clock_last_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.162      ; 4.747      ;
; 4.370 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_holding_full_reg                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.162      ; 4.747      ;
; 4.370 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_active_reg                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.162      ; 4.747      ;
; 4.370 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serial_out_reg                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.162      ; 4.747      ;
; 4.370 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[8]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.171      ; 4.756      ;
; 4.370 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|irqst_reg[3]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.162      ; 4.747      ;
; 4.370 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[5]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.177      ; 4.762      ;
; 4.370 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[14]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.173      ; 4.758      ;
; 4.370 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|irqen_reg[2]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.161      ; 4.746      ;
; 4.370 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[16]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.175      ; 4.760      ;
; 4.370 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|mosi~en                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.160      ; 4.745      ;
; 4.371 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[27]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.183      ; 4.769      ;
; 4.371 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[15]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.187      ; 4.773      ;
; 4.371 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[7]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.182      ; 4.768      ;
; 4.371 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[7]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.182      ; 4.768      ;
; 4.371 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[6]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.182      ; 4.768      ;
; 4.371 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[2]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.182      ; 4.768      ;
; 4.371 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[3]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.182      ; 4.768      ;
; 4.371 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[9]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.182      ; 4.768      ;
; 4.371 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[14]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.187      ; 4.773      ;
; 4.371 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[6]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.182      ; 4.768      ;
; 4.371 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[3]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.182      ; 4.768      ;
; 4.371 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[19]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.183      ; 4.769      ;
; 4.371 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[13]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.187      ; 4.773      ;
; 4.371 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[8]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.187      ; 4.773      ;
; 4.371 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[0]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.182      ; 4.768      ;
; 4.371 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[0]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.186      ; 4.772      ;
; 4.371 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[2]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.182      ; 4.768      ;
; 4.372 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[15]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.171      ; 4.758      ;
; 4.372 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[15]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.171      ; 4.758      ;
; 4.372 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[25]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 4.768      ;
; 4.372 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[27]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.171      ; 4.758      ;
; 4.372 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[27]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 4.768      ;
; 4.372 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[10]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.171      ; 4.758      ;
; 4.372 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[12]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.171      ; 4.758      ;
; 4.372 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[7]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 4.768      ;
; 4.372 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[7]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 4.768      ;
; 4.372 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[9]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 4.768      ;
; 4.372 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[6]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 4.768      ;
; 4.372 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[6]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 4.768      ;
; 4.372 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[22]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 4.768      ;
; 4.372 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[22]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 4.768      ;
; 4.372 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[11]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.171      ; 4.758      ;
; 4.372 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[11]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.171      ; 4.758      ;
; 4.372 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[21]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.171      ; 4.758      ;
; 4.372 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[21]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.171      ; 4.758      ;
; 4.372 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[3]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 4.768      ;
; 4.372 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[3]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 4.768      ;
; 4.372 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[19]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.171      ; 4.758      ;
; 4.372 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[19]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.171      ; 4.758      ;
; 4.372 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[13]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.171      ; 4.758      ;
; 4.372 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[13]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.171      ; 4.758      ;
; 4.372 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[0]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 4.768      ;
; 4.372 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[20]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 4.768      ;
; 4.372 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[20]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 4.768      ;
; 4.372 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[18]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.171      ; 4.758      ;
; 4.372 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[18]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.171      ; 4.758      ;
; 4.372 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[2]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 4.768      ;
; 4.372 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[2]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 4.768      ;
; 4.373 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[25]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.170      ; 4.758      ;
; 4.373 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[25]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.170      ; 4.758      ;
; 4.373 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[27]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.170      ; 4.758      ;
; 4.373 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[27]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.170      ; 4.758      ;
; 4.373 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[26]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.171      ; 4.759      ;
; 4.373 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[26]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.171      ; 4.759      ;
; 4.373 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[10]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.171      ; 4.759      ;
; 4.373 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[10]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.171      ; 4.759      ;
; 4.373 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[12]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.171      ; 4.759      ;
; 4.373 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[12]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.171      ; 4.759      ;
; 4.373 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[22]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.170      ; 4.758      ;
; 4.373 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[22]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.170      ; 4.758      ;
; 4.373 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[11]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.171      ; 4.759      ;
; 4.373 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[21]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.170      ; 4.758      ;
; 4.373 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[19]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.170      ; 4.758      ;
; 4.373 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[19]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.170      ; 4.758      ;
; 4.373 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[13]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.171      ; 4.759      ;
; 4.373 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[20]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.170      ; 4.758      ;
; 4.373 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[20]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.170      ; 4.758      ;
; 4.373 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[14]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.170      ; 4.758      ;
; 4.373 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[18]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.170      ; 4.758      ;
; 4.373 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[18]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.170      ; 4.758      ;
; 4.373 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[16]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.173      ; 4.761      ;
; 4.373 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[8]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.171      ; 4.759      ;
; 4.380 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_8BIT_WRITE_ENABLE_reg                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.184      ; 4.779      ;
; 4.381 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[23]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.185      ; 4.781      ;
; 4.381 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[13]                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 4.776      ;
; 4.381 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[25]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.185      ; 4.781      ;
; 4.381 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[30]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.188      ; 4.784      ;
+-------+---------------------------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                         ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                          ; Clock Edge ; Target                                                    ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; 5.518 ; 5.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[13]                                            ;
; 5.518 ; 5.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[14]                                            ;
; 5.518 ; 5.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[6]                                             ;
; 5.518 ; 5.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[8]                                             ;
; 5.518 ; 5.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ;
; 5.518 ; 5.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ;
; 5.518 ; 5.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_act                      ;
; 5.518 ; 5.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ;
; 5.518 ; 5.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_act                      ;
; 5.518 ; 5.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[0]                                             ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[10]                                            ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[11]                                            ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[12]                                            ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[15]                                            ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[1]                                             ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[2]                                             ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[3]                                             ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[4]                                             ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[5]                                             ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[7]                                             ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[9]                                             ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[0]                                             ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[10]                                            ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[11]                                            ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[12]                                            ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[13]                                            ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[14]                                            ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[15]                                            ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[16]                                            ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[17]                                            ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[18]                                            ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[19]                                            ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[1]                                             ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[20]                                            ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[21]                                            ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[22]                                            ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[23]                                            ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[24]                                            ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[25]                                            ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[26]                                            ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[27]                                            ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[28]                                            ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[29]                                            ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[2]                                             ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[30]                                            ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[31]                                            ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[3]                                             ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[4]                                             ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[5]                                             ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[6]                                             ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[7]                                             ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[8]                                             ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[9]                                             ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_reg                      ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_req                    ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_reg                      ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[0]                                           ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[1]                                           ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel[0]                     ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_act                    ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_complete_reg                                ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_reg                                         ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[2]                                                ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[3]                                                ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[4]                                                ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[5]                                                ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[6]                                                ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[7]                                                ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|sdram_rdy                     ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[0]                                                ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[10]                                               ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[11]                                               ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[1]                                                ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[8]                                                ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[9]                                                ;
; 5.623 ; 5.778        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[13]                  ;
; 5.623 ; 5.778        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[14]                  ;
; 5.623 ; 5.778        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[15]                  ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+-----------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                               ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                          ; Clock Edge ; Target                                                                                          ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------------------------+
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[5]                 ;
; 8.432 ; 8.648        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; half_scandouble_enable_reg                                                                      ;
; 8.432 ; 8.648        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]                         ;
; 8.432 ; 8.648        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[0]                  ;
; 8.432 ; 8.648        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[10]                 ;
; 8.432 ; 8.648        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[1]                  ;
; 8.432 ; 8.648        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[2]                  ;
; 8.432 ; 8.648        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[3]                  ;
; 8.432 ; 8.648        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[4]                  ;
; 8.432 ; 8.648        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[5]                  ;
; 8.432 ; 8.648        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[6]                  ;
; 8.432 ; 8.648        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[7]                  ;
; 8.432 ; 8.648        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[8]                  ;
; 8.432 ; 8.648        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[9]                  ;
; 8.432 ; 8.648        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[10]                ;
; 8.432 ; 8.648        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[1]                 ;
; 8.432 ; 8.648        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[2]                 ;
; 8.432 ; 8.648        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[3]                 ;
; 8.432 ; 8.648        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[4]                 ;
; 8.432 ; 8.648        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[6]                 ;
; 8.432 ; 8.648        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[7]                 ;
; 8.432 ; 8.648        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[8]                 ;
; 8.432 ; 8.648        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[9]                 ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|buffer_select_reg                     ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                         ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                         ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[0]   ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[100] ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[101] ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[102] ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[103] ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[104] ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[105] ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[106] ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[107] ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[108] ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[109] ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[10]  ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[110] ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[111] ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[112] ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[113] ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[114] ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[115] ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[116] ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[117] ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[118] ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[119] ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[11]  ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[120] ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[121] ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[122] ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[123] ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[124] ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[125] ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[126] ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[127] ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[12]  ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[13]  ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[14]  ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[15]  ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[1]   ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[2]   ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[3]   ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[41]  ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[42]  ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[43]  ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[44]  ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[45]  ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[46]  ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[47]  ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[48]  ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[49]  ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[4]   ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[50]  ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[51]  ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[52]  ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[53]  ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[54]  ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[55]  ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[56]  ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[57]  ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[58]  ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[59]  ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[5]   ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[60]  ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[61]  ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[62]  ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[63]  ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[64]  ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[65]  ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[66]  ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[67]  ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[68]  ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[69]  ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[6]   ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[70]  ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[71]  ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[72]  ;
; 8.434 ; 8.650        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[73]  ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                         ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                          ; Clock Edge ; Target                                                                                                                   ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------+
; 17.158 ; 17.374       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p2[12]                                                                                       ;
; 17.158 ; 17.374       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p2[13]                                                                                       ;
; 17.158 ; 17.374       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p2[14]                                                                                       ;
; 17.158 ; 17.374       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p2[15]                                                                                       ;
; 17.158 ; 17.374       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p2[16]                                                                                       ;
; 17.158 ; 17.374       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p2[17]                                                                                       ;
; 17.158 ; 17.374       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p2[18]                                                                                       ;
; 17.158 ; 17.374       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p2[19]                                                                                       ;
; 17.158 ; 17.374       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p2[20]                                                                                       ;
; 17.158 ; 17.374       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p2[21]                                                                                       ;
; 17.158 ; 17.374       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p2[22]                                                                                       ;
; 17.158 ; 17.374       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p2[23]                                                                                       ;
; 17.158 ; 17.374       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_lpf_p2[12]                                                                                       ;
; 17.158 ; 17.374       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_lpf_p2[13]                                                                                       ;
; 17.158 ; 17.374       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_lpf_p2[14]                                                                                       ;
; 17.158 ; 17.374       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_lpf_p2[15]                                                                                       ;
; 17.158 ; 17.374       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_lpf_p2[16]                                                                                       ;
; 17.158 ; 17.374       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_lpf_p2[17]                                                                                       ;
; 17.158 ; 17.374       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_lpf_p2[18]                                                                                       ;
; 17.158 ; 17.374       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_lpf_p2[19]                                                                                       ;
; 17.158 ; 17.374       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_lpf_p2[20]                                                                                       ;
; 17.158 ; 17.374       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_lpf_p2[21]                                                                                       ;
; 17.158 ; 17.374       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_lpf_p2[22]                                                                                       ;
; 17.158 ; 17.374       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_lpf_p2[23]                                                                                       ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[13]                ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[12]          ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[13]          ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[15]          ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[9]           ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|antic_fetch_real_reg        ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg              ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|write_enable_reg            ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[8]                  ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[9]                  ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_destination_reg[0]        ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_destination_reg[1]        ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_destination_reg[2]        ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                       ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|last_line_of_instruction_reg        ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|pmbase_reg[3]                       ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|pmbase_reg[4]                       ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|pmbase_reg[5]                       ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|pmbase_reg[6]                       ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|pmbase_reg[7]                       ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[20][0] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[20][1] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[20][2] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[20][3] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[20][4] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[20][5] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[20][6] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[20][7] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[27][0] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[27][1] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[27][2] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[27][3] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[27][4] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[27][6] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[27][7] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[28][0] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[28][1] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[28][2] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[28][3] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[28][4] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[28][5] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[28][6] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[28][7] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[30][2] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[31][0] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[31][1] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[31][2] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[31][3] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[31][4] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[31][5] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[31][6] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[31][7] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[34][0] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[34][1] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[34][2] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[34][3] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[34][4] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[34][5] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[34][6] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[34][7] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[38][0] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[38][1] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[38][2] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[38][3] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[38][4] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[38][5] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[38][6] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[38][7] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[40][0] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[40][1] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[40][2] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[40][3] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[40][4] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[40][5] ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                    ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                         ; Clock Edge ; Target                                                                                              ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------+
; 17.426 ; 17.426       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.426 ; 17.426       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.426 ; 17.426       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.426 ; 17.426       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]                      ;
; 17.426 ; 17.426       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 17.428 ; 17.428       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.428 ; 17.428       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.437 ; 17.437       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.482 ; 17.482       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.491 ; 17.491       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.491 ; 17.491       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.493 ; 17.493       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.493 ; 17.493       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.493 ; 17.493       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.493 ; 17.493       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]                      ;
; 17.493 ; 17.493       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'                                                                                                                         ;
+---------+--------------+----------------+------------------+----------+------------+-----------------------------------------------------------------------------------------+
; Slack   ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                                                  ;
+---------+--------------+----------------+------------------+----------+------------+-----------------------------------------------------------------------------------------+
; 99.837  ; 99.837       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 99.837  ; 99.837       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 99.888  ; 99.888       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                        ;
; 99.920  ; 99.920       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 100.000 ; 100.000      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                        ;
; 100.000 ; 100.000      ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                        ;
; 100.079 ; 100.079      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 100.112 ; 100.112      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                        ;
; 100.162 ; 100.162      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 100.162 ; 100.162      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 196.000 ; 200.000      ; 4.000          ; Port Rate        ; FPGA_CLK ; Rise       ; FPGA_CLK                                                                                ;
+---------+--------------+----------------+------------------+----------+------------+-----------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                              ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.654 ; 2.761 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.634 ; 2.741 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.634 ; 2.741 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.634 ; 2.741 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.648 ; 2.755 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.651 ; 2.758 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.649 ; 2.756 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.645 ; 2.752 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.654 ; 2.761 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.642 ; 2.749 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.648 ; 2.755 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.637 ; 2.744 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.637 ; 2.744 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.627 ; 2.734 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.626 ; 2.733 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.616 ; 2.723 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.626 ; 2.733 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; 5.686 ; 6.281 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; 3.518 ; 3.767 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; 4.474 ; 4.781 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; 4.301 ; 4.749 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; 4.053 ; 4.412 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; 5.686 ; 6.281 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; 5.312 ; 5.935 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; 3.269 ; 3.527 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; 4.211 ; 4.470 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; 3.950 ; 4.299 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; 3.911 ; 4.216 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; 5.312 ; 5.935 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; 6.461 ; 6.565 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; 6.310 ; 6.477 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; 4.229 ; 4.513 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                 ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; -1.730 ; -1.838 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; -1.749 ; -1.857 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; -1.749 ; -1.857 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; -1.749 ; -1.857 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; -1.763 ; -1.871 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; -1.767 ; -1.875 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; -1.765 ; -1.873 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; -1.761 ; -1.869 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; -1.769 ; -1.877 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; -1.757 ; -1.865 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; -1.763 ; -1.871 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; -1.752 ; -1.860 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; -1.752 ; -1.860 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; -1.742 ; -1.850 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; -1.740 ; -1.848 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; -1.730 ; -1.838 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; -1.740 ; -1.848 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; -2.562 ; -2.798 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; -2.562 ; -2.798 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; -3.449 ; -3.723 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; -3.284 ; -3.692 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; -3.042 ; -3.368 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; -2.699 ; -2.954 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; -2.324 ; -2.568 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; -2.324 ; -2.568 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; -3.229 ; -3.474 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; -2.898 ; -3.219 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; -2.942 ; -3.231 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; -2.627 ; -2.913 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; -5.399 ; -5.504 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; -5.260 ; -5.422 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; -3.262 ; -3.539 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                      ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 4.590 ; 4.140 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 3.323 ; 3.087 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 3.313 ; 3.077 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 3.313 ; 3.077 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 3.313 ; 3.077 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 3.317 ; 3.081 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 3.326 ; 3.090 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 3.335 ; 3.099 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 4.590 ; 4.140 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 3.336 ; 3.100 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 3.346 ; 3.110 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 3.323 ; 3.087 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 4.578 ; 4.128 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 3.325 ; 3.089 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 4.578 ; 4.128 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 4.590 ; 4.140 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 3.335 ; 3.099 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 4.660 ; 4.212 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 3.607 ; 3.350 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 3.607 ; 3.350 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 3.607 ; 3.350 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 4.637 ; 4.189 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 4.633 ; 4.185 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 2.563 ; 2.365 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 3.507 ; 3.264 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 3.519 ; 3.276 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 3.639 ; 3.382 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 4.657 ; 4.209 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 3.644 ; 3.387 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 3.644 ; 3.387 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 3.634 ; 3.377 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 4.660 ; 4.212 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 3.626 ; 3.369 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 3.636 ; 3.379 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 4.155 ; 4.606 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 3.794 ; 4.242 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 4.155 ; 4.606 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 3.335 ; 3.099 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 3.345 ; 3.109 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 6.349 ; 6.633 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 5.037 ; 4.830 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 5.099 ; 4.586 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 7.288 ; 7.363 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 3.878 ; 4.179 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 9.378 ;       ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 9.107 ; Fall       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]        ; FPGA_CLK   ; 5.382 ; 5.730 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]       ; FPGA_CLK   ; 2.808 ; 2.778 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]       ; FPGA_CLK   ; 5.382 ; 5.730 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]       ; FPGA_CLK   ; 2.578 ; 2.528 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]       ; FPGA_CLK   ; 5.360 ; 5.708 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]        ; FPGA_CLK   ; 5.266 ; 5.559 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]       ; FPGA_CLK   ; 5.266 ; 5.559 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]       ; FPGA_CLK   ; 2.506 ; 2.389 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]       ; FPGA_CLK   ; 2.516 ; 2.399 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]       ; FPGA_CLK   ; 2.506 ; 2.389 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_HS          ; FPGA_CLK   ; 5.255 ; 5.548 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_R[*]        ; FPGA_CLK   ; 2.496 ; 2.379 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[0]       ; FPGA_CLK   ; 2.484 ; 2.367 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[1]       ; FPGA_CLK   ; 2.494 ; 2.377 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[2]       ; FPGA_CLK   ; 2.496 ; 2.379 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[3]       ; FPGA_CLK   ; 2.486 ; 2.369 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_VS          ; FPGA_CLK   ; 2.495 ; 2.378 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                              ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 2.555 ; 2.323 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 2.565 ; 2.333 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 2.555 ; 2.323 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 2.555 ; 2.323 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 2.555 ; 2.323 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 2.559 ; 2.327 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 2.567 ; 2.335 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 2.577 ; 2.345 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 3.871 ; 3.422 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 2.578 ; 2.346 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 2.588 ; 2.356 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 2.565 ; 2.333 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 2.567 ; 2.335 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 2.567 ; 2.335 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 3.859 ; 3.410 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 3.871 ; 3.422 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 2.577 ; 2.345 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 1.847 ; 1.650 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 2.848 ; 2.595 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 2.848 ; 2.595 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 2.848 ; 2.595 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 3.920 ; 3.473 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 3.917 ; 3.470 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 1.847 ; 1.650 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 2.749 ; 2.510 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 2.760 ; 2.521 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 2.880 ; 2.627 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 3.940 ; 3.493 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 2.885 ; 2.632 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 2.885 ; 2.632 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 2.875 ; 2.622 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 3.942 ; 3.495 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 2.866 ; 2.613 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 2.876 ; 2.623 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 3.017 ; 3.454 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 3.017 ; 3.454 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 3.364 ; 3.804 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 2.577 ; 2.345 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 2.587 ; 2.355 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 5.599 ; 5.886 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 4.236 ; 4.037 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 4.282 ; 3.785 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 6.494 ; 6.578 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 3.106 ; 3.398 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 8.700 ;       ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 8.434 ; Fall       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]        ; FPGA_CLK   ; 1.861 ; 1.812 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]       ; FPGA_CLK   ; 2.089 ; 2.060 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]       ; FPGA_CLK   ; 4.664 ; 5.013 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]       ; FPGA_CLK   ; 1.861 ; 1.812 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]       ; FPGA_CLK   ; 4.643 ; 4.992 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]        ; FPGA_CLK   ; 1.786 ; 1.670 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]       ; FPGA_CLK   ; 4.547 ; 4.841 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]       ; FPGA_CLK   ; 1.786 ; 1.670 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]       ; FPGA_CLK   ; 1.796 ; 1.680 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]       ; FPGA_CLK   ; 1.786 ; 1.670 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_HS          ; FPGA_CLK   ; 4.536 ; 4.830 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_R[*]        ; FPGA_CLK   ; 1.765 ; 1.649 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[0]       ; FPGA_CLK   ; 1.765 ; 1.649 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[1]       ; FPGA_CLK   ; 1.775 ; 1.659 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[2]       ; FPGA_CLK   ; 1.776 ; 1.660 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[3]       ; FPGA_CLK   ; 1.766 ; 1.650 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_VS          ; FPGA_CLK   ; 1.775 ; 1.659 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                                      ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.403 ; 2.403 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.136 ; 3.136 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.136 ; 3.136 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.136 ; 3.136 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.179 ; 3.179 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.567 ; 3.567 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.896 ; 3.896 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.912 ; 3.912 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.939 ; 3.939 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.594 ; 3.594 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.192 ; 3.192 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.773 ; 2.773 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.773 ; 2.773 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.763 ; 2.763 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.413 ; 2.413 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.403 ; 2.403 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.413 ; 2.413 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 4.598 ; 4.222 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                              ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.381 ; 1.381 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.084 ; 2.084 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.084 ; 2.084 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.084 ; 2.084 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.127 ; 2.127 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.499 ; 2.499 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.814 ; 2.814 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.830 ; 2.830 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.857 ; 2.857 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.525 ; 2.525 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.140 ; 2.140 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.737 ; 1.737 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.737 ; 1.737 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.727 ; 1.727 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 1.391 ; 1.391 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.381 ; 1.381 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.391 ; 1.391 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.705 ; 3.344 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                             ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.308     ; 2.379     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.973     ; 3.044     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.973     ; 3.044     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.973     ; 3.044     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.050     ; 3.121     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.412     ; 3.483     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.679     ; 3.750     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.735     ; 3.806     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.758     ; 3.829     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.390     ; 3.461     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.027     ; 3.098     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.626     ; 2.697     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.626     ; 2.697     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.616     ; 2.687     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.318     ; 2.389     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.308     ; 2.379     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.318     ; 2.389     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.983     ; 4.359     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                                     ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.358     ; 1.494     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.997     ; 2.133     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.997     ; 2.133     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.997     ; 2.133     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.071     ; 2.207     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.418     ; 2.554     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.675     ; 2.811     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.728     ; 2.864     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.750     ; 2.886     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.397     ; 2.533     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.049     ; 2.185     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.665     ; 1.801     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.665     ; 1.801     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.655     ; 1.791     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 1.368     ; 1.504     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.358     ; 1.494     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.368     ; 1.504     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.114     ; 3.475     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+


---------------------------------------------
; Slow 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+---------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup Summary                                                                      ;
+--------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                          ; Slack  ; End Point TNS ;
+--------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 6.706  ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 7.484  ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 14.262 ; 0.000         ;
+--------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold Summary                                                                      ;
+--------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                          ; Slack ; End Point TNS ;
+--------------------------------------------------------------------------------+-------+---------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.180 ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.187 ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.188 ; 0.000         ;
+--------------------------------------------------------------------------------+-------+---------------+


+---------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery Summary                                                                   ;
+--------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                          ; Slack  ; End Point TNS ;
+--------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 9.054  ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 9.710  ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 14.990 ; 0.000         ;
+--------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal Summary                                                                   ;
+--------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                          ; Slack ; End Point TNS ;
+--------------------------------------------------------------------------------+-------+---------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1.243 ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 1.703 ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 2.151 ; 0.000         ;
+--------------------------------------------------------------------------------+-------+---------------+


+---------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width Summary                                                        ;
+--------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                          ; Slack  ; End Point TNS ;
+--------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.605  ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 8.476  ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.206 ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]  ; 17.437 ; 0.000         ;
; FPGA_CLK                                                                       ; 99.405 ; 0.000         ;
+--------------------------------------------------------------------------------+--------+---------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                        ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                         ; To Node                                      ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 6.706 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.107     ; 4.767      ;
; 6.754 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.107     ; 4.719      ;
; 6.853 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.107     ; 4.620      ;
; 6.918 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.104     ; 4.558      ;
; 6.967 ; sdram_reset_n_reg                                                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.107     ; 4.506      ;
; 6.977 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.104     ; 4.499      ;
; 6.988 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.104     ; 4.488      ;
; 6.988 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.107     ; 4.485      ;
; 7.000 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.107     ; 4.473      ;
; 7.014 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.104     ; 4.462      ;
; 7.021 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.109     ; 4.450      ;
; 7.046 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[5]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.101     ; 4.433      ;
; 7.051 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.104     ; 4.425      ;
; 7.053 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.110     ; 4.417      ;
; 7.072 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.108     ; 4.400      ;
; 7.087 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.109     ; 4.384      ;
; 7.096 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.104     ; 4.380      ;
; 7.101 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.110     ; 4.369      ;
; 7.128 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.116     ; 4.336      ;
; 7.135 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.109     ; 4.336      ;
; 7.166 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.109     ; 4.305      ;
; 7.176 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.116     ; 4.288      ;
; 7.179 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[6]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.101     ; 4.300      ;
; 7.180 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.116     ; 4.284      ;
; 7.194 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.105     ; 4.281      ;
; 7.200 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.110     ; 4.270      ;
; 7.209 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.104     ; 4.267      ;
; 7.219 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.116     ; 4.245      ;
; 7.222 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.113     ; 4.245      ;
; 7.228 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.116     ; 4.236      ;
; 7.230 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[14]                                                                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.104     ; 4.246      ;
; 7.234 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.109     ; 4.237      ;
; 7.259 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[5]                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.104     ; 4.217      ;
; 7.263 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[4]                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.101     ; 4.216      ;
; 7.264 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.108     ; 4.208      ;
; 7.264 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[11]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.115     ; 4.201      ;
; 7.265 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.107     ; 4.208      ;
; 7.266 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[8]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.105     ; 4.209      ;
; 7.266 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.113     ; 4.201      ;
; 7.267 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.116     ; 4.197      ;
; 7.271 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.113     ; 4.196      ;
; 7.275 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.116     ; 4.189      ;
; 7.275 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.113     ; 4.192      ;
; 7.294 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.105     ; 4.181      ;
; 7.295 ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.110     ; 4.175      ;
; 7.299 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.106     ; 4.175      ;
; 7.302 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.107     ; 4.171      ;
; 7.304 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.113     ; 4.163      ;
; 7.305 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[5]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.103     ; 4.172      ;
; 7.306 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[15]                                                                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.104     ; 4.170      ;
; 7.306 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.110     ; 4.164      ;
; 7.310 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.106     ; 4.164      ;
; 7.311 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.113     ; 4.156      ;
; 7.314 ; sdram_reset_n_reg                                                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.110     ; 4.156      ;
; 7.315 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.113     ; 4.152      ;
; 7.317 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[11]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.115     ; 4.148      ;
; 7.319 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.113     ; 4.148      ;
; 7.322 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.105     ; 4.153      ;
; 7.324 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.107     ; 4.149      ;
; 7.327 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.116     ; 4.137      ;
; 7.335 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.107     ; 4.138      ;
; 7.335 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.110     ; 4.135      ;
; 7.337 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.107     ; 4.136      ;
; 7.338 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.113     ; 4.129      ;
; 7.340 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.113     ; 4.127      ;
; 7.341 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.108     ; 4.131      ;
; 7.343 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|antic_fetch_real_reg                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.104     ; 4.133      ;
; 7.343 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.113     ; 4.124      ;
; 7.347 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.110     ; 4.123      ;
; 7.348 ; sdram_reset_n_reg                                                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.109     ; 4.123      ;
; 7.349 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.106     ; 4.125      ;
; 7.352 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[4]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.101     ; 4.127      ;
; 7.356 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.110     ; 4.114      ;
; 7.357 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.105     ; 4.118      ;
; 7.358 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.106     ; 4.116      ;
; 7.361 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.107     ; 4.112      ;
; 7.361 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.113     ; 4.106      ;
; 7.364 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.113     ; 4.103      ;
; 7.366 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.116     ; 4.098      ;
; 7.368 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.112     ; 4.100      ;
; 7.369 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.106     ; 4.105      ;
; 7.369 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.109     ; 4.102      ;
; 7.380 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[13]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.113     ; 4.087      ;
; 7.381 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.109     ; 4.090      ;
; 7.382 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.113     ; 4.085      ;
; 7.385 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.108     ; 4.087      ;
; 7.389 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.113     ; 4.078      ;
; 7.389 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[9]                             ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.109     ; 4.082      ;
; 7.389 ; sdram_reset_n_reg                                                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.116     ; 4.075      ;
; 7.391 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.113     ; 4.076      ;
; 7.392 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.113     ; 4.075      ;
; 7.396 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[11]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.106     ; 4.078      ;
; 7.399 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[8]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.108     ; 4.073      ;
; 7.401 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.105     ; 4.074      ;
; 7.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.111     ; 4.067      ;
; 7.410 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.116     ; 4.054      ;
; 7.414 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.112     ; 4.054      ;
; 7.415 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[4]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.114     ; 4.051      ;
; 7.416 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.118     ; 4.046      ;
; 7.417 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.107     ; 4.056      ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                               ;
+-------+----------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                  ; To Node                                                                                                                                                    ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 7.484 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.088     ; 4.055      ;
; 7.508 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.085     ; 4.034      ;
; 7.578 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[37]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.097     ; 3.952      ;
; 7.597 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[31]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.095     ; 3.935      ;
; 7.609 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.086     ; 3.932      ;
; 7.612 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.088     ; 3.927      ;
; 7.640 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.096     ; 3.891      ;
; 7.653 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.095     ; 3.879      ;
; 7.665 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[35]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.095     ; 3.867      ;
; 7.675 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[35]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.095     ; 3.857      ;
; 7.706 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[11]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.091     ; 3.830      ;
; 7.732 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[0]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.097     ; 3.798      ;
; 7.749 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[26]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.085     ; 3.793      ;
; 7.750 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.099     ; 3.778      ;
; 7.755 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[0]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.096     ; 3.776      ;
; 7.774 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[0]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.100     ; 3.753      ;
; 7.774 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[1]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.100     ; 3.753      ;
; 7.775 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.097     ; 3.755      ;
; 7.776 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.103     ; 3.748      ;
; 7.777 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[5]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.099     ; 3.751      ;
; 7.780 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[37]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.096     ; 3.751      ;
; 7.794 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[0]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.095     ; 3.738      ;
; 7.794 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[1]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.095     ; 3.738      ;
; 7.794 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[2]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.095     ; 3.738      ;
; 7.794 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[3]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.095     ; 3.738      ;
; 7.794 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[4]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.095     ; 3.738      ;
; 7.794 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[5]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.095     ; 3.738      ;
; 7.794 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[6]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.095     ; 3.738      ;
; 7.794 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[7]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.095     ; 3.738      ;
; 7.801 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[40]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.095     ; 3.731      ;
; 7.802 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[0]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.095     ; 3.730      ;
; 7.802 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[1]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.095     ; 3.730      ;
; 7.802 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[2]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.095     ; 3.730      ;
; 7.802 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[3]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.095     ; 3.730      ;
; 7.802 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[4]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.095     ; 3.730      ;
; 7.802 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[5]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.095     ; 3.730      ;
; 7.802 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[6]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.095     ; 3.730      ;
; 7.802 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[7]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.095     ; 3.730      ;
; 7.811 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.097     ; 3.719      ;
; 7.814 ; ram_do_reg[5]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.086     ; 3.727      ;
; 7.830 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[42]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.097     ; 3.700      ;
; 7.831 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[19]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.096     ; 3.700      ;
; 7.833 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[4]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.098     ; 3.696      ;
; 7.859 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[31]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.094     ; 3.674      ;
; 7.867 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[37]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.097     ; 3.663      ;
; 7.868 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.086     ; 3.673      ;
; 7.876 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[2]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.098     ; 3.653      ;
; 7.876 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[3]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.098     ; 3.653      ;
; 7.892 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[0]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.099     ; 3.636      ;
; 7.892 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[1]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.099     ; 3.636      ;
; 7.892 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[2]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.099     ; 3.636      ;
; 7.892 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[3]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.099     ; 3.636      ;
; 7.892 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[4]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.099     ; 3.636      ;
; 7.892 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[5]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.099     ; 3.636      ;
; 7.892 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[6]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.099     ; 3.636      ;
; 7.892 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[7]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.099     ; 3.636      ;
; 7.893 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[6]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.096     ; 3.638      ;
; 7.893 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[7]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.096     ; 3.638      ;
; 7.894 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.084     ; 3.649      ;
; 7.915 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[20]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.085     ; 3.627      ;
; 7.917 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[19]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.097     ; 3.613      ;
; 7.920 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer3|delay_line:underflow0_delay|shift_reg[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.096     ; 3.611      ;
; 7.928 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[35]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.094     ; 3.605      ;
; 7.929 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[5]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.094     ; 3.604      ;
; 7.946 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[5]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.101     ; 3.580      ;
; 7.946 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[2]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.101     ; 3.580      ;
; 7.946 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[1]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.101     ; 3.580      ;
; 7.946 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[0]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.101     ; 3.580      ;
; 7.946 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[3]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.101     ; 3.580      ;
; 7.946 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[4]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.101     ; 3.580      ;
; 7.946 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[6]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.101     ; 3.580      ;
; 7.946 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[7]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.101     ; 3.580      ;
; 7.949 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[0]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.095     ; 3.583      ;
; 7.949 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[1]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.095     ; 3.583      ;
; 7.949 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[2]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.095     ; 3.583      ;
; 7.949 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[3]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.095     ; 3.583      ;
; 7.949 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[4]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.095     ; 3.583      ;
; 7.949 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[5]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.095     ; 3.583      ;
; 7.949 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[6]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.095     ; 3.583      ;
; 7.949 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[7]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.095     ; 3.583      ;
; 7.955 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[1]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.092     ; 3.580      ;
; 7.972 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[1]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.099     ; 3.556      ;
; 7.972 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[0]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.099     ; 3.556      ;
; 7.972 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[2]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.099     ; 3.556      ;
; 7.972 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[3]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.099     ; 3.556      ;
; 7.972 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[4]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.099     ; 3.556      ;
; 7.972 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|compare_latch_reg[5]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.099     ; 3.556      ;
; 7.981 ; ram_do_reg[5]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.084     ; 3.562      ;
; 7.984 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[31]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.096     ; 3.547      ;
; 7.990 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[1]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.099     ; 3.538      ;
; 7.990 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[5]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.099     ; 3.538      ;
; 7.990 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[4]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.099     ; 3.538      ;
; 7.990 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[0]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.099     ; 3.538      ;
; 7.990 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[2]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.099     ; 3.538      ;
; 7.990 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[3]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.099     ; 3.538      ;
; 7.997 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer2|count_reg[0]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.097     ; 3.533      ;
; 7.997 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer2|count_reg[1]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.097     ; 3.533      ;
; 7.997 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer2|count_reg[2]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.097     ; 3.533      ;
; 7.997 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer2|count_reg[3]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.097     ; 3.533      ;
; 7.997 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer2|count_reg[4]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.097     ; 3.533      ;
+-------+----------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                ; To Node                                                                                                                                                                       ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 14.262 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.084     ; 3.054      ;
; 14.322 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.084     ; 2.994      ;
; 14.343 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.084     ; 2.973      ;
; 14.375 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.055     ; 2.970      ;
; 14.390 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.055     ; 2.955      ;
; 14.418 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.085     ; 2.897      ;
; 14.438 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.055     ; 2.907      ;
; 14.444 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.054     ; 2.902      ;
; 14.454 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.084     ; 2.862      ;
; 14.496 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.055     ; 2.849      ;
; 14.553 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.053     ; 2.794      ;
; 14.554 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.053     ; 2.793      ;
; 14.560 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.054     ; 2.786      ;
; 14.561 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.054     ; 2.785      ;
; 14.569 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.053     ; 2.778      ;
; 14.572 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.054     ; 2.774      ;
; 14.579 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.085     ; 2.736      ;
; 14.610 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.068     ; 2.722      ;
; 14.633 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.069     ; 2.698      ;
; 14.635 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.068     ; 2.697      ;
; 14.647 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.055     ; 2.698      ;
; 14.666 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.054     ; 2.680      ;
; 14.674 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.068     ; 2.658      ;
; 14.677 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.054     ; 2.669      ;
; 14.678 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.053     ; 2.669      ;
; 14.687 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.055     ; 2.658      ;
; 14.702 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.083     ; 2.615      ;
; 14.707 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.053     ; 2.640      ;
; 14.717 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.054     ; 2.629      ;
; 14.725 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.069     ; 2.606      ;
; 14.730 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.054     ; 2.616      ;
; 14.730 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.055     ; 2.615      ;
; 14.733 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.054     ; 2.613      ;
; 14.733 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.069     ; 2.598      ;
; 14.737 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.054     ; 2.609      ;
; 14.740 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.054     ; 2.606      ;
; 14.741 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.055     ; 2.604      ;
; 14.742 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.054     ; 2.604      ;
; 14.748 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.053     ; 2.599      ;
; 14.754 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hsync_reg                                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[0]                                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.620      ;
; 14.754 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hsync_reg                                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[1]                                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.620      ;
; 14.754 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hsync_reg                                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[2]                                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.620      ;
; 14.754 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hsync_reg                                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[3]                                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.620      ;
; 14.754 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hsync_reg                                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[4]                                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.620      ;
; 14.754 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hsync_reg                                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[5]                                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.620      ;
; 14.754 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hsync_reg                                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[6]                                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.620      ;
; 14.754 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hsync_reg                                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[7]                                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.620      ;
; 14.754 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hsync_reg                                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[8]                                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.620      ;
; 14.754 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hsync_reg                                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[9]                                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.620      ;
; 14.754 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hsync_reg                                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[10]                                                                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.073     ; 2.620      ;
; 14.755 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.084     ; 2.561      ;
; 14.765 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.084     ; 2.551      ;
; 14.768 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.053     ; 2.579      ;
; 14.789 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.055     ; 2.556      ;
; 14.794 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.054     ; 2.552      ;
; 14.801 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.054     ; 2.545      ;
; 14.802 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.068     ; 2.530      ;
; 14.839 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.069     ; 2.492      ;
; 14.860 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.084     ; 2.456      ;
; 14.863 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.053     ; 2.484      ;
; 14.865 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.054     ; 2.481      ;
; 14.880 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.069     ; 2.451      ;
; 14.936 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.069     ; 2.395      ;
; 14.946 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.053     ; 2.401      ;
; 14.946 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.069     ; 2.385      ;
; 14.978 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.070     ; 2.352      ;
; 14.979 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.055     ; 2.366      ;
; 15.002 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.056     ; 2.342      ;
; 15.016 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.055     ; 2.329      ;
; 15.028 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.215     ; 2.204      ;
; 15.037 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.055     ; 2.308      ;
; 15.044 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.054     ; 2.302      ;
; 15.048 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.056     ; 2.296      ;
; 15.057 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.055     ; 2.288      ;
; 15.123 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.215     ; 2.109      ;
; 15.134 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[3]                                                                         ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_datain_reg0 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; 0.108      ; 2.443      ;
; 15.143 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[3]                                                                         ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_datain_reg0 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; 0.107      ; 2.433      ;
; 15.155 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.054     ; 2.191      ;
; 15.165 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.055     ; 2.180      ;
; 15.172 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.054     ; 2.174      ;
; 15.183 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.084     ; 2.133      ;
; 15.202 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.216     ; 2.029      ;
; 15.205 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.215     ; 2.027      ;
; 15.224 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.085     ; 2.091      ;
; 15.231 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.052     ; 2.117      ;
; 15.245 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.216     ; 1.986      ;
; 15.247 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0]                                                                         ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_datain_reg0 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; 0.108      ; 2.330      ;
; 15.269 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.217     ; 1.961      ;
; 15.271 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0]                                                                         ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_datain_reg0 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; 0.107      ; 2.305      ;
; 15.283 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.055     ; 2.062      ;
; 15.286 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.054     ; 2.060      ;
; 15.302 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]                                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.219     ; 1.926      ;
; 15.319 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.215     ; 1.913      ;
; 15.337 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.084     ; 1.979      ;
; 15.338 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.055     ; 2.007      ;
; 15.339 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.056     ; 2.005      ;
; 15.348 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.054     ; 1.998      ;
; 15.348 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.218     ; 1.881      ;
; 15.393 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.054     ; 1.953      ;
; 15.424 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]                                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.218     ; 1.805      ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                ;
+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                  ; To Node                                                                                                                                                    ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 0.180 ; ram_do_reg[9]                                                                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[9]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.097      ; 0.381      ;
; 0.184 ; ram_do_reg[31]                                                                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[31]                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.096      ; 0.384      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vblank_reg                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vblank_reg                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_ready_reg                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_ready_reg                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|state_reg[0]           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|state_reg[0]           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|state_reg[1]           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|state_reg[1]           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vscrol_last_enabled_reg                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vscrol_last_enabled_reg                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|last_line_of_instruction_reg                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|last_line_of_instruction_reg                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|nmist_reg[6]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|nmist_reg[6]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|shift_pressed_reg      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|shift_pressed_reg      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|break_pressed_reg      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|break_pressed_reg      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|control_pressed_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|control_pressed_reg    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wsync_reg                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wsync_reg                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_refresh_count|value_reg[1]               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_refresh_count|value_reg[1]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_refresh_count|value_reg[2]               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_refresh_count|value_reg[2]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_refresh_count|value_reg[3]               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_refresh_count|value_reg[3]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[1]                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[1]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[2]                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[2]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[3]                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[3]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[4]                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[4]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[5]                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[5]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[6]                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[6]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[7]                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[7]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[0]                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[0]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|pmg_dma_state_reg[2]                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|pmg_dma_state_reg[2]                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|pmg_dma_state_reg[0]                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|pmg_dma_state_reg[0]                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile0|shift_reg[7]                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile0|shift_reg[7]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pl_reg[1]                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pl_reg[1]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player3|shift_reg[7]                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player3|shift_reg[7]                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|count_reg[1]                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|count_reg[1]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[7]                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[7]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|count_reg[1]                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|count_reg[1]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|shift_reg[6]                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|shift_reg[6]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pl_reg[0]                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pl_reg[0]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pf_reg[0]                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pf_reg[0]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pf_reg[0]                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pf_reg[0]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p2pl_reg[3]                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p2pl_reg[3]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pl_reg[2]                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pl_reg[2]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pl_reg[2]                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pl_reg[2]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pf_reg[2]                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pf_reg[2]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pl_reg[3]                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pl_reg[3]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[5]                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[5]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[4]                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[4]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[6]                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[6]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[7]                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[7]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0]                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Ireg                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Ireg                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Dreg                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Dreg                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|skctl_reg[0]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|skctl_reg[0]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[1]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[1]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[3]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[3]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[4]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[4]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[6]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[6]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[7]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[7]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|delay_line:underflow0_delay|shift_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|delay_line:underflow0_delay|shift_reg[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf3_reg[5]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf3_reg[5]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf3_reg[0]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf3_reg[0]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf3_reg[1]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf3_reg[1]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf3_reg[2]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf3_reg[2]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf3_reg[3]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf3_reg[3]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf3_reg[6]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf3_reg[6]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf3_reg[7]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf3_reg[7]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|irqst_reg[1]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|irqst_reg[1]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf3_reg[3]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf3_reg[3]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf3_reg[7]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf3_reg[7]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf3_reg[6]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf3_reg[6]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|serial_out_reg                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|serial_out_reg                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf0_reg[7]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf0_reg[7]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pot_reset_reg                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pot_reset_reg                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|irqst_reg[5]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|irqst_reg[5]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|serout_clock_reg                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|serout_clock_reg                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|irqst_reg[4]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|irqst_reg[4]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|irqst_reg[0]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|irqst_reg[0]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|irqst_reg[0]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|irqst_reg[0]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig0_reg                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig0_reg                                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig2_reg                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig2_reg                                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig1_reg                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig1_reg                                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|irqst_reg[2]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|irqst_reg[2]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|irqst_reg[7]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|irqst_reg[7]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|chan3_output_reg                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|chan3_output_reg                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|chan2_output_reg                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|chan2_output_reg                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|chan3_output_reg                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|chan3_output_reg                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|chan0_output_reg                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|chan0_output_reg                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|highpass0_reg                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|highpass0_reg                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_count_reg[2]                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_count_reg[2]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_count_reg[3]                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_count_reg[3]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[0]                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[0]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[20]                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[20]                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[2]                                                                                                          ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[2]                                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[3]                                                                                                          ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[3]                                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[10]                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[10]                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[18]                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[18]                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[8]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[8]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[9]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[9]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[14]                                                                                                           ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[14]                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[16]                                                                                                           ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[16]                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[17]                                                                                                           ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[17]                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[24]                                                                                                           ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[24]                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[19]                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[19]                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                                                                                          ;
+-------+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                       ; To Node                                                                                         ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 0.187 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|buffer_select_reg                     ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|buffer_select_reg                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_hsync_reg                         ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_hsync_reg                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.307      ;
; 0.192 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[46]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[45]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.312      ;
; 0.193 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[108] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[107] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.313      ;
; 0.193 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[105] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[104] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.313      ;
; 0.193 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[56]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[55]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.313      ;
; 0.193 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[27]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[26]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.313      ;
; 0.193 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[17]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[16]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.313      ;
; 0.193 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[15]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[14]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.313      ;
; 0.193 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[2]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[1]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.313      ;
; 0.194 ; half_scandouble_enable_reg                                                                      ; half_scandouble_enable_reg                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[123] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[122] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[122] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[121] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[121] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[120] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[113] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[112] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[111] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[110] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[109] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[108] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[107] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[106] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[106] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[105] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[92]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[91]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[88]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[87]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[87]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[86]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[86]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[85]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[85]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[84]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[79]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[78]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[77]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[76]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[68]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[67]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[63]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[62]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[61]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[60]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[60]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[59]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[59]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[58]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[58]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[57]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[51]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[50]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[50]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[49]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[47]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[46]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[43]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[42]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[35]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[34]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[34]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[33]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[33]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[32]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[26]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[25]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[25]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[24]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[23]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[22]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[22]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[21]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[7]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[6]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[6]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[5]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[4]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[3]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[127] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[126] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[124] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[123] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[120] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[119] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[102] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[101] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[101] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[100] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[94]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[93]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[91]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[90]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[90]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[89]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[78]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[77]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[76]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[75]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[75]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[74]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[73]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[72]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[57]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[56]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[48]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[47]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[42]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[41]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[40]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[39]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[31]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[30]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[14]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[13]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[12]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[11]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[11]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[10]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.196 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[125] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[124] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.316      ;
; 0.196 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[116] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[115] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.316      ;
; 0.196 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[104] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[103] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.316      ;
; 0.196 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[83]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[82]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.316      ;
; 0.196 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[71]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[70]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.316      ;
; 0.196 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[36]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[35]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.316      ;
; 0.196 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[30]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[29]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.316      ;
; 0.196 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[24]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[23]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.316      ;
; 0.196 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[20]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[19]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.316      ;
; 0.196 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[8]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[7]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.316      ;
; 0.197 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[55]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[54]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.317      ;
; 0.198 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|hsync_in_reg                          ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|buffer_select_reg                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.318      ;
; 0.205 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[10]                 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[10]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.325      ;
; 0.259 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[41]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[40]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.037      ; 0.380      ;
; 0.260 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[100] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[99]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.380      ;
; 0.261 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[99]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[98]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.380      ;
; 0.261 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[16]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[15]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.381      ;
; 0.262 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[84]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[83]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.037      ; 0.383      ;
; 0.262 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[53]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[52]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.382      ;
; 0.262 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[32]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[31]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.381      ;
; 0.262 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[13]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[12]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.382      ;
; 0.263 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[82]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[81]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.383      ;
; 0.266 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[115] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[114] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.386      ;
; 0.266 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[72]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[71]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.386      ;
; 0.266 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[28]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[27]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.386      ;
; 0.267 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[126] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[125] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.387      ;
; 0.267 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[118] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[117] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.387      ;
; 0.267 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[117] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[116] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.387      ;
; 0.267 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[112] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[111] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.387      ;
; 0.267 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[97]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[96]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.387      ;
; 0.267 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[95]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[94]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.387      ;
; 0.267 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[89]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[88]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.387      ;
; 0.267 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[81]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[80]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.387      ;
; 0.267 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[74]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[73]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.387      ;
+-------+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                    ;
+-------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                       ; To Node                                                   ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 0.188 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_rd_act                                                                            ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_wr_act                                                                            ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                                      ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                           ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                                                                        ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_request_complete_reg                                                                                      ; sdram_request_complete_reg                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_refr_act                                                                          ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.195 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.314      ;
; 0.214 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.333      ;
; 0.225 ; seq_reg[11]                                                                                                     ; seq_reg[0]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.345      ;
; 0.238 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.357      ;
; 0.243 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.362      ;
; 0.270 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[20] ; ram_di_reg[4]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.085      ; 0.459      ;
; 0.270 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[25] ; ram_di_reg[9]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.085      ; 0.459      ;
; 0.270 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[28] ; ram_di_reg[12]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.085      ; 0.459      ;
; 0.271 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[19] ; ram_di_reg[3]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.085      ; 0.460      ;
; 0.272 ; sdram_ctrl:sdram_controller|r_rd_reg                                                                            ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.391      ;
; 0.273 ; sdram_ctrl:sdram_controller|r_rd_reg                                                                            ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.392      ;
; 0.289 ; seq_reg[8]                                                                                                      ; seq_reg[9]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.409      ;
; 0.292 ; seq_reg[4]                                                                                                      ; seq_reg[5]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.412      ;
; 0.292 ; sdram_ctrl:sdram_controller|r_refr_act                                                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.412      ;
; 0.294 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.413      ;
; 0.294 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.413      ;
; 0.294 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.413      ;
; 0.295 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.414      ;
; 0.295 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.414      ;
; 0.295 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.414      ;
; 0.296 ; sdram_ctrl:sdram_controller|r_psel_dly[0]                                                                       ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.415      ;
; 0.296 ; seq_reg[6]                                                                                                      ; seq_reg[7]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.416      ;
; 0.296 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.415      ;
; 0.296 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.415      ;
; 0.297 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.416      ;
; 0.298 ; seq_reg[0]                                                                                                      ; seq_reg[1]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.418      ;
; 0.299 ; sdram_ctrl:sdram_controller|r_rd_act                                                                            ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.418      ;
; 0.304 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.423      ;
; 0.327 ; sdram_ctrl:sdram_controller|r_rd_act                                                                            ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.446      ;
; 0.329 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[16] ; ram_di_reg[0]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.085      ; 0.518      ;
; 0.332 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[21] ; ram_di_reg[5]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.085      ; 0.521      ;
; 0.335 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[18] ; ram_di_reg[2]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.085      ; 0.524      ;
; 0.340 ; sdram_ctrl:sdram_controller|r_refr_req                                                                          ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.459      ;
; 0.340 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[17] ; ram_di_reg[1]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.085      ; 0.529      ;
; 0.343 ; seq_reg[10]                                                                                                     ; seq_reg[11]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.463      ;
; 0.349 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                                      ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.468      ;
; 0.352 ; seq_reg[9]                                                                                                      ; seq_reg[10]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.472      ;
; 0.361 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                                       ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.480      ;
; 0.363 ; sdram_ctrl:sdram_controller|r_refr_req                                                                          ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.482      ;
; 0.370 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.489      ;
; 0.370 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                                       ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.489      ;
; 0.371 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[23] ; ram_di_reg[7]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.085      ; 0.560      ;
; 0.371 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[27] ; ram_di_reg[11]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.085      ; 0.560      ;
; 0.371 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[29] ; ram_di_reg[13]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.084      ; 0.559      ;
; 0.372 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.491      ;
; 0.372 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[24] ; ram_di_reg[8]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.084      ; 0.560      ;
; 0.373 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[22] ; ram_di_reg[6]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.084      ; 0.561      ;
; 0.373 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[30] ; ram_di_reg[14]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.084      ; 0.561      ;
; 0.378 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[31] ; ram_di_reg[15]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.085      ; 0.567      ;
; 0.381 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                                      ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.500      ;
; 0.385 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.504      ;
; 0.411 ; sdram_ctrl:sdram_controller|r_wr_act                                                                            ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.530      ;
; 0.422 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[11] ; ram_di_reg[11]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.085      ; 0.611      ;
; 0.430 ; sdram_ctrl:sdram_controller|r_refr_req                                                                          ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.549      ;
; 0.435 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[26] ; ram_di_reg[10]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.085      ; 0.624      ;
; 0.443 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.562      ;
; 0.443 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.562      ;
; 0.443 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.562      ;
; 0.444 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.563      ;
; 0.453 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.572      ;
; 0.453 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.572      ;
; 0.454 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.573      ;
; 0.456 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.575      ;
; 0.456 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.575      ;
; 0.457 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.576      ;
; 0.457 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.576      ;
; 0.460 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.579      ;
; 0.465 ; seq_reg[5]                                                                                                      ; seq_reg[6]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.585      ;
; 0.471 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.590      ;
; 0.471 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                                                                       ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.590      ;
; 0.475 ; sdram_ctrl:sdram_controller|r_refr_act                                                                          ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.032      ; 0.591      ;
; 0.477 ; seq_reg[2]                                                                                                      ; seq_reg[3]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.597      ;
; 0.477 ; sdram_ctrl:sdram_controller|r_refr_act                                                                          ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.032      ; 0.593      ;
; 0.483 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[14] ; ram_di_reg[14]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.084      ; 0.671      ;
; 0.491 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[13] ; ram_di_reg[13]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.084      ; 0.679      ;
; 0.492 ; seq_reg[3]                                                                                                      ; seq_reg[4]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.612      ;
; 0.496 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                                       ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.042      ; 0.622      ;
; 0.501 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[10] ; ram_di_reg[10]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.085      ; 0.690      ;
; 0.506 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.625      ;
; 0.506 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.625      ;
; 0.506 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.625      ;
; 0.507 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                                      ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.626      ;
; 0.507 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                                      ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.626      ;
; 0.509 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.628      ;
; 0.509 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.628      ;
; 0.509 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.628      ;
; 0.511 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[5]  ; ram_di_reg[5]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 0.706      ;
+-------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                       ;
+-------+---------------------------------------+----------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                                                                                                                    ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+----------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[31]                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.086     ; 2.487      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[31]                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.086     ; 2.487      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[31]                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.086     ; 2.487      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[31]                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.086     ; 2.487      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.086     ; 2.487      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[12]                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.088     ; 2.485      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_READ_reg                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.088     ; 2.485      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_8BIT_WRITE_ENABLE_reg                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.082     ; 2.491      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[23]                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.080     ; 2.493      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[13]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.093     ; 2.480      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[12]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.093     ; 2.480      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[0]                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.093     ; 2.480      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[0]                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.087     ; 2.486      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[1]                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.087     ; 2.486      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[3]                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.086     ; 2.487      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[8]                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.089     ; 2.484      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[9]                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.089     ; 2.484      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[10]                                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.086     ; 2.487      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[11]                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.093     ; 2.480      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[11]                                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.093     ; 2.480      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[13]                                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.093     ; 2.480      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[13]                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.090     ; 2.483      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[14]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.093     ; 2.480      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[15]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.093     ; 2.480      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[14]                                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.093     ; 2.480      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[14]                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.089     ; 2.484      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[15]                                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.093     ; 2.480      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[16]                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.089     ; 2.484      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[17]                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.089     ; 2.484      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[3]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.086     ; 2.487      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[2]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.086     ; 2.487      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[20]                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.090     ; 2.483      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_reg                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.093     ; 2.480      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[10]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.086     ; 2.487      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[24]                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.089     ; 2.484      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[6]                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.086     ; 2.487      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[5]                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.086     ; 2.487      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[4]                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.086     ; 2.487      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[3]                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.086     ; 2.487      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[2]                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.086     ; 2.487      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[1]                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.086     ; 2.487      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[0]                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.086     ; 2.487      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[23]                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.086     ; 2.487      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[23]                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.086     ; 2.487      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[23]                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.086     ; 2.487      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[23]                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.086     ; 2.487      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[19]                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.080     ; 2.493      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|skctl_reg[3]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.090     ; 2.483      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|skctl_reg[5]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.090     ; 2.483      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|sio_in_reg                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.092     ; 2.481      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|skctl_reg[4]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.090     ; 2.483      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audctl_reg[3]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.095     ; 2.478      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audctl_reg[5]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.095     ; 2.478      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audctl_reg[0]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.095     ; 2.478      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[2]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.090     ; 2.483      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[0]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.090     ; 2.483      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[1]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.090     ; 2.483      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[3]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.090     ; 2.483      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[4]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.090     ; 2.483      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[5]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.090     ; 2.483      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[6]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.090     ; 2.483      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf2_reg[7]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.090     ; 2.483      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer2|delay_line:underflow0_delay|shift_reg[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.095     ; 2.478      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[2]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.094     ; 2.479      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[3]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.094     ; 2.479      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf3_reg[5]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.094     ; 2.479      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer3|delay_line:underflow0_delay|shift_reg[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.095     ; 2.478      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audctl_reg[4]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.095     ; 2.478      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audctl_reg[6]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.095     ; 2.478      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[2]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.094     ; 2.479      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf0_reg[3]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.094     ; 2.479      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[3]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.094     ; 2.479      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[0]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.096     ; 2.477      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[0]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.094     ; 2.479      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[1]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.094     ; 2.479      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[1]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.094     ; 2.479      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[2]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.094     ; 2.479      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[2]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.094     ; 2.479      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[3]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.094     ; 2.479      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[5]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.094     ; 2.479      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[4]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.094     ; 2.479      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[4]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.094     ; 2.479      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[5]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.094     ; 2.479      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[7]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.096     ; 2.477      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[6]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.094     ; 2.479      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[6]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.094     ; 2.479      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[7]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.094     ; 2.479      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|skctl_reg[6]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.090     ; 2.483      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_shift_reg[9]                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.096     ; 2.477      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_shift_reg[8]                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.096     ; 2.477      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_shift_reg[7]                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.096     ; 2.477      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_shift_reg[6]                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.096     ; 2.477      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_shift_reg[5]                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.096     ; 2.477      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_shift_reg[4]                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.096     ; 2.477      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_shift_reg[3]                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.096     ; 2.477      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_shift_reg[2]                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.096     ; 2.477      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_shift_reg[1]                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.096     ; 2.477      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|skctl_reg[7]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.090     ; 2.483      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[15]                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.085     ; 2.488      ;
; 9.054 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[9]                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.083     ; 2.490      ;
+-------+---------------------------------------+----------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                       ;
+-------+------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                                   ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 9.710 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[13]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.129     ; 1.741      ;
; 9.710 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[14]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.129     ; 1.741      ;
; 9.710 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[15]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.129     ; 1.741      ;
; 9.711 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[5]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.143     ; 1.726      ;
; 9.712 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[15]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.183     ; 1.683      ;
; 9.712 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[13]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.183     ; 1.683      ;
; 9.712 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[14]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.183     ; 1.683      ;
; 9.712 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[0]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.138     ; 1.730      ;
; 9.712 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[1]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.138     ; 1.730      ;
; 9.712 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[2]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.138     ; 1.730      ;
; 9.712 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[3]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.140     ; 1.728      ;
; 9.712 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[4]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.145     ; 1.723      ;
; 9.712 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[7]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.139     ; 1.729      ;
; 9.712 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[8]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.131     ; 1.737      ;
; 9.713 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[5]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.197     ; 1.668      ;
; 9.713 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[6]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.139     ; 1.728      ;
; 9.713 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[9]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.137     ; 1.730      ;
; 9.714 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[7]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.193     ; 1.671      ;
; 9.714 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[1]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.192     ; 1.672      ;
; 9.714 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[2]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.192     ; 1.672      ;
; 9.714 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[0]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.192     ; 1.672      ;
; 9.714 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[8]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.185     ; 1.679      ;
; 9.714 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[4]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.199     ; 1.665      ;
; 9.714 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[3]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.194     ; 1.670      ;
; 9.715 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[9]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.191     ; 1.672      ;
; 9.715 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[6]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.193     ; 1.670      ;
; 9.719 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[10]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.131     ; 1.730      ;
; 9.719 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[11]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.131     ; 1.730      ;
; 9.719 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[12]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.131     ; 1.730      ;
; 9.721 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[11]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.185     ; 1.672      ;
; 9.721 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[10]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.185     ; 1.672      ;
; 9.721 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[12]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.185     ; 1.672      ;
; 9.722 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[0]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.115     ; 1.743      ;
; 9.722 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[1]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.115     ; 1.743      ;
; 9.722 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[2]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.115     ; 1.743      ;
; 9.722 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[3]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.115     ; 1.743      ;
; 9.722 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[6]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.109     ; 1.749      ;
; 9.722 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[7]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.109     ; 1.749      ;
; 9.722 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.115     ; 1.743      ;
; 9.722 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.115     ; 1.743      ;
; 9.723 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[4]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.106     ; 1.751      ;
; 9.723 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[5]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.108     ; 1.749      ;
; 9.723 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[8]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.107     ; 1.750      ;
; 9.723 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.113     ; 1.744      ;
; 9.723 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.107     ; 1.750      ;
; 9.725 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.091     ; 1.811      ;
; 9.726 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.092     ; 1.809      ;
; 9.726 ; sdram_reset_ctrl_n_reg ; ram_do_reg[14]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.092     ; 1.809      ;
; 9.758 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.091     ; 1.778      ;
; 9.758 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.091     ; 1.778      ;
; 9.758 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.091     ; 1.778      ;
; 9.758 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.091     ; 1.778      ;
; 9.758 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.091     ; 1.778      ;
; 9.758 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.091     ; 1.778      ;
; 9.758 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.091     ; 1.778      ;
; 9.758 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.091     ; 1.778      ;
; 9.758 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.091     ; 1.778      ;
; 9.840 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.113     ; 1.627      ;
; 9.840 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.113     ; 1.627      ;
; 9.840 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.113     ; 1.627      ;
; 9.840 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.113     ; 1.627      ;
; 9.948 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.088     ; 1.591      ;
; 9.948 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.088     ; 1.591      ;
; 9.948 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.088     ; 1.591      ;
; 9.948 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.088     ; 1.591      ;
; 9.948 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.088     ; 1.591      ;
; 9.948 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.088     ; 1.591      ;
; 9.949 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.098     ; 1.580      ;
; 9.949 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.098     ; 1.580      ;
; 9.949 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.098     ; 1.580      ;
; 9.949 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.098     ; 1.580      ;
; 9.949 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.098     ; 1.580      ;
; 9.949 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.092     ; 1.586      ;
; 9.949 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.094     ; 1.584      ;
; 9.949 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.092     ; 1.586      ;
; 9.951 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.095     ; 1.581      ;
; 9.951 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.095     ; 1.581      ;
; 9.951 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.095     ; 1.581      ;
; 9.951 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.095     ; 1.581      ;
; 9.951 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.095     ; 1.581      ;
; 9.951 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.095     ; 1.581      ;
; 9.951 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.095     ; 1.581      ;
; 9.951 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.095     ; 1.581      ;
; 9.951 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.095     ; 1.581      ;
; 9.951 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.095     ; 1.581      ;
; 9.951 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.092     ; 1.584      ;
; 9.951 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.092     ; 1.584      ;
; 9.951 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.091     ; 1.585      ;
; 9.951 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.091     ; 1.585      ;
; 9.951 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.091     ; 1.585      ;
; 9.951 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.092     ; 1.584      ;
; 9.951 ; sdram_reset_ctrl_n_reg ; ram_do_reg[5]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.092     ; 1.584      ;
; 9.951 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.102     ; 1.574      ;
; 9.951 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.095     ; 1.581      ;
; 9.951 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.102     ; 1.574      ;
; 9.951 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.102     ; 1.574      ;
; 9.951 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.102     ; 1.574      ;
; 9.951 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.095     ; 1.581      ;
; 9.951 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.102     ; 1.574      ;
; 9.951 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.102     ; 1.574      ;
+-------+------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                         ;
+--------+-------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node         ; To Node                                                                                         ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 14.990 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.130     ; 2.280      ;
; 14.990 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.130     ; 2.280      ;
; 14.992 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.114     ; 2.294      ;
; 15.000 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.115     ; 2.285      ;
; 15.014 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vsync_reg                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.101     ; 2.285      ;
; 15.014 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.100     ; 2.286      ;
; 15.014 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.100     ; 2.286      ;
; 15.014 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.100     ; 2.286      ;
; 15.014 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.100     ; 2.286      ;
; 15.014 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.099     ; 2.287      ;
; 15.014 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.099     ; 2.287      ;
; 15.015 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|hsync_reg                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.101     ; 2.284      ;
; 15.015 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.101     ; 2.284      ;
; 15.015 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.101     ; 2.284      ;
; 15.239 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.082     ; 2.126      ;
; 15.239 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[10]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.083     ; 2.125      ;
; 15.239 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.083     ; 2.125      ;
; 15.240 ; sdram_reset_n_reg ; half_scandouble_enable_reg                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.084     ; 2.123      ;
; 15.240 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.084     ; 2.123      ;
; 15.240 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[1]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.084     ; 2.123      ;
; 15.240 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[2]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.084     ; 2.123      ;
; 15.240 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[3]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.084     ; 2.123      ;
; 15.240 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[4]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.084     ; 2.123      ;
; 15.240 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[5]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.084     ; 2.123      ;
; 15.240 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[6]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.084     ; 2.123      ;
; 15.240 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[7]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.084     ; 2.123      ;
; 15.240 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[8]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.084     ; 2.123      ;
; 15.240 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[9]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.084     ; 2.123      ;
; 15.240 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[10]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.084     ; 2.123      ;
; 15.240 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.082     ; 2.125      ;
; 15.240 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.082     ; 2.125      ;
; 15.240 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.082     ; 2.125      ;
; 15.240 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.082     ; 2.125      ;
; 15.240 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.082     ; 2.125      ;
; 15.240 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.082     ; 2.125      ;
; 15.240 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.082     ; 2.125      ;
; 15.240 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.082     ; 2.125      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[127] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.081     ; 2.118      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[126] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.081     ; 2.118      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[125] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.081     ; 2.118      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[124] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.081     ; 2.118      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[123] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.081     ; 2.118      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[122] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.081     ; 2.118      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[121] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.081     ; 2.118      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[120] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.081     ; 2.118      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[119] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.081     ; 2.118      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[118] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.081     ; 2.118      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[117] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.081     ; 2.118      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[116] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.081     ; 2.118      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[115] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.081     ; 2.118      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[114] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.081     ; 2.118      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[113] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.080     ; 2.119      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[112] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.080     ; 2.119      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[111] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.080     ; 2.119      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[110] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.080     ; 2.119      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[109] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.080     ; 2.119      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[108] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.080     ; 2.119      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[107] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.080     ; 2.119      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[106] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.080     ; 2.119      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[105] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.080     ; 2.119      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[104] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.080     ; 2.119      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[103] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.080     ; 2.119      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[102] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.080     ; 2.119      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[101] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.080     ; 2.119      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[100] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.080     ; 2.119      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[98]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.081     ; 2.118      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[97]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.081     ; 2.118      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[96]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.081     ; 2.118      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[95]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.081     ; 2.118      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[94]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.081     ; 2.118      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[93]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.081     ; 2.118      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[92]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.081     ; 2.118      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[91]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.081     ; 2.118      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[90]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.081     ; 2.118      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[89]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.081     ; 2.118      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[88]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.081     ; 2.118      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[87]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.081     ; 2.118      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[86]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.081     ; 2.118      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[85]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.081     ; 2.118      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[84]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.081     ; 2.118      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[81]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.080     ; 2.119      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[80]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.080     ; 2.119      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[66]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.079     ; 2.120      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[65]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.079     ; 2.120      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[64]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.079     ; 2.120      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[63]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.079     ; 2.120      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[62]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.079     ; 2.120      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[61]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.079     ; 2.120      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[60]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.079     ; 2.120      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[59]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.079     ; 2.120      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[58]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.079     ; 2.120      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[57]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.079     ; 2.120      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[56]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.079     ; 2.120      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[55]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.079     ; 2.120      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[54]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.079     ; 2.120      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[52]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.079     ; 2.120      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[51]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.079     ; 2.120      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[50]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.079     ; 2.120      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[49]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.079     ; 2.120      ;
; 15.248 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[48]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.079     ; 2.120      ;
+--------+-------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                       ;
+-------+------------------------+----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                                  ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 1.243 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 1.438      ;
; 1.243 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 1.438      ;
; 1.243 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 1.438      ;
; 1.243 ; sdram_reset_ctrl_n_reg ; seq_reg[5]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 1.438      ;
; 1.243 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 1.438      ;
; 1.243 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 1.438      ;
; 1.243 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 1.438      ;
; 1.243 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 1.438      ;
; 1.243 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 1.438      ;
; 1.243 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[0]                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 1.438      ;
; 1.243 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[1]                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 1.438      ;
; 1.249 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.093      ; 1.446      ;
; 1.249 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.093      ; 1.446      ;
; 1.249 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.093      ; 1.446      ;
; 1.249 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.093      ; 1.446      ;
; 1.249 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.093      ; 1.446      ;
; 1.249 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.093      ; 1.446      ;
; 1.249 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.088      ; 1.441      ;
; 1.249 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.088      ; 1.441      ;
; 1.249 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.090      ; 1.443      ;
; 1.249 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.090      ; 1.443      ;
; 1.249 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.090      ; 1.443      ;
; 1.249 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.088      ; 1.441      ;
; 1.249 ; sdram_reset_ctrl_n_reg ; ram_do_reg[5]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.088      ; 1.441      ;
; 1.249 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.085      ; 1.438      ;
; 1.249 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.085      ; 1.438      ;
; 1.249 ; sdram_reset_ctrl_n_reg ; ram_do_reg[15]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.088      ; 1.441      ;
; 1.249 ; sdram_reset_ctrl_n_reg ; ram_do_reg[25]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.090      ; 1.443      ;
; 1.249 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.088      ; 1.441      ;
; 1.249 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.090      ; 1.443      ;
; 1.249 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.090      ; 1.443      ;
; 1.249 ; sdram_reset_ctrl_n_reg ; ram_do_reg[12]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.088      ; 1.441      ;
; 1.249 ; sdram_reset_ctrl_n_reg ; ram_do_reg[9]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.090      ; 1.443      ;
; 1.249 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.088      ; 1.441      ;
; 1.249 ; sdram_reset_ctrl_n_reg ; ram_do_reg[11]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.088      ; 1.441      ;
; 1.249 ; sdram_reset_ctrl_n_reg ; ram_do_reg[19]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.088      ; 1.441      ;
; 1.249 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.088      ; 1.441      ;
; 1.249 ; sdram_reset_ctrl_n_reg ; ram_do_reg[13]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.088      ; 1.441      ;
; 1.249 ; sdram_reset_ctrl_n_reg ; ram_do_reg[8]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.090      ; 1.443      ;
; 1.249 ; sdram_reset_ctrl_n_reg ; ram_do_reg[20]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.088      ; 1.441      ;
; 1.249 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.085      ; 1.438      ;
; 1.249 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.085      ; 1.438      ;
; 1.249 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.086      ; 1.439      ;
; 1.249 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.086      ; 1.439      ;
; 1.249 ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.086      ; 1.439      ;
; 1.249 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.086      ; 1.439      ;
; 1.249 ; sdram_reset_ctrl_n_reg ; ram_di_reg[11]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.086      ; 1.439      ;
; 1.249 ; sdram_reset_ctrl_n_reg ; ram_di_reg[12]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.086      ; 1.439      ;
; 1.249 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.087      ; 1.440      ;
; 1.249 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.085      ; 1.438      ;
; 1.249 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.085      ; 1.438      ;
; 1.249 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.085      ; 1.438      ;
; 1.250 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.085      ; 1.439      ;
; 1.250 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.085      ; 1.439      ;
; 1.250 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.085      ; 1.439      ;
; 1.250 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.085      ; 1.439      ;
; 1.250 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.085      ; 1.439      ;
; 1.250 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.085      ; 1.439      ;
; 1.250 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.085      ; 1.439      ;
; 1.250 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.085      ; 1.439      ;
; 1.250 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.085      ; 1.439      ;
; 1.250 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.085      ; 1.439      ;
; 1.250 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.082      ; 1.436      ;
; 1.250 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.082      ; 1.436      ;
; 1.250 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.082      ; 1.436      ;
; 1.250 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.082      ; 1.436      ;
; 1.250 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.082      ; 1.436      ;
; 1.250 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.432      ;
; 1.250 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.432      ;
; 1.250 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.432      ;
; 1.250 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.432      ;
; 1.250 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_act                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.432      ;
; 1.250 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.432      ;
; 1.250 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.088      ; 1.442      ;
; 1.250 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.086      ; 1.440      ;
; 1.250 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.086      ; 1.440      ;
; 1.250 ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.086      ; 1.440      ;
; 1.250 ; sdram_reset_ctrl_n_reg ; ram_di_reg[6]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.084      ; 1.438      ;
; 1.250 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.086      ; 1.440      ;
; 1.250 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.084      ; 1.438      ;
; 1.250 ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.086      ; 1.440      ;
; 1.250 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.084      ; 1.438      ;
; 1.250 ; sdram_reset_ctrl_n_reg ; ram_di_reg[14]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.084      ; 1.438      ;
; 1.250 ; sdram_reset_ctrl_n_reg ; ram_di_reg[15]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.086      ; 1.440      ;
; 1.250 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.088      ; 1.442      ;
; 1.339 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.488      ;
; 1.339 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.488      ;
; 1.339 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.488      ;
; 1.339 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.488      ;
; 1.421 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.089      ; 1.614      ;
; 1.421 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.089      ; 1.614      ;
; 1.421 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.089      ; 1.614      ;
; 1.421 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.089      ; 1.614      ;
; 1.421 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.089      ; 1.614      ;
; 1.421 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.089      ; 1.614      ;
; 1.421 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.089      ; 1.614      ;
; 1.421 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.089      ; 1.614      ;
; 1.421 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.089      ; 1.614      ;
; 1.437 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.089      ; 1.630      ;
; 1.437 ; sdram_reset_ctrl_n_reg ; ram_do_reg[14]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.089      ; 1.630      ;
+-------+------------------------+----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                         ;
+-------+-------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node         ; To Node                                                                                         ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 1.703 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|buffer_select_reg                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.101      ; 1.908      ;
; 1.703 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[99]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.102      ; 1.909      ;
; 1.703 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[83]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.102      ; 1.909      ;
; 1.703 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[82]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.102      ; 1.909      ;
; 1.703 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[79]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.102      ; 1.909      ;
; 1.703 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[78]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.102      ; 1.909      ;
; 1.703 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[77]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.102      ; 1.909      ;
; 1.703 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[76]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.102      ; 1.909      ;
; 1.703 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[75]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.102      ; 1.909      ;
; 1.703 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[74]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.102      ; 1.909      ;
; 1.703 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[73]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.102      ; 1.909      ;
; 1.703 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[72]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.102      ; 1.909      ;
; 1.703 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[71]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.102      ; 1.909      ;
; 1.703 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[70]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.102      ; 1.909      ;
; 1.703 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[69]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.102      ; 1.909      ;
; 1.703 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[68]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.102      ; 1.909      ;
; 1.703 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[67]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.102      ; 1.909      ;
; 1.703 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[40]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.104      ; 1.911      ;
; 1.703 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[39]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.104      ; 1.911      ;
; 1.703 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[38]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.104      ; 1.911      ;
; 1.703 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[37]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.104      ; 1.911      ;
; 1.703 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[36]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.104      ; 1.911      ;
; 1.703 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[35]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.104      ; 1.911      ;
; 1.703 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[34]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.104      ; 1.911      ;
; 1.703 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[33]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.104      ; 1.911      ;
; 1.703 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[32]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.104      ; 1.911      ;
; 1.703 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.101      ; 1.908      ;
; 1.703 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.101      ; 1.908      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[127] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.101      ; 1.909      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[126] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.101      ; 1.909      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[125] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.101      ; 1.909      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[124] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.101      ; 1.909      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[123] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.101      ; 1.909      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[122] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.101      ; 1.909      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[121] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.101      ; 1.909      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[120] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.101      ; 1.909      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[119] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.101      ; 1.909      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[118] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.101      ; 1.909      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[117] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.101      ; 1.909      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[116] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.101      ; 1.909      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[115] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.101      ; 1.909      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[114] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.101      ; 1.909      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[113] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.102      ; 1.910      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[112] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.102      ; 1.910      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[111] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.102      ; 1.910      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[110] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.102      ; 1.910      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[109] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.102      ; 1.910      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[108] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.102      ; 1.910      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[107] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.102      ; 1.910      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[106] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.102      ; 1.910      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[105] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.102      ; 1.910      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[104] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.102      ; 1.910      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[103] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.102      ; 1.910      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[102] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.102      ; 1.910      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[101] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.102      ; 1.910      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[100] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.102      ; 1.910      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[98]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.101      ; 1.909      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[97]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.101      ; 1.909      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[96]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.101      ; 1.909      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[95]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.101      ; 1.909      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[94]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.101      ; 1.909      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[93]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.101      ; 1.909      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[92]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.101      ; 1.909      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[91]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.101      ; 1.909      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[90]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.101      ; 1.909      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[89]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.101      ; 1.909      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[88]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.101      ; 1.909      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[87]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.101      ; 1.909      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[86]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.101      ; 1.909      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[85]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.101      ; 1.909      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[84]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.101      ; 1.909      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[81]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.102      ; 1.910      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[80]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.102      ; 1.910      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[66]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 1.911      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[65]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 1.911      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[64]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 1.911      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[63]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 1.911      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[62]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 1.911      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[61]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 1.911      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[60]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 1.911      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[59]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 1.911      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[58]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 1.911      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[57]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 1.911      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[56]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 1.911      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[55]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 1.911      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[54]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 1.911      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[53]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 1.911      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[52]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 1.911      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[51]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 1.911      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[50]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 1.911      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[49]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 1.911      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[48]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 1.911      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[47]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 1.911      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[46]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 1.911      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[45]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 1.911      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[44]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 1.911      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[43]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 1.911      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[42]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 1.911      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[41]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 1.911      ;
; 1.704 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[31]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 1.911      ;
+-------+-------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                             ;
+-------+---------------------------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                                                                                         ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 2.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[5]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.094      ; 2.349      ;
; 2.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[2]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.094      ; 2.349      ;
; 2.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[3]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.094      ; 2.349      ;
; 2.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[5]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.092      ; 2.347      ;
; 2.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[16]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.093      ; 2.348      ;
; 2.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[6]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.092      ; 2.347      ;
; 2.151 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|mosi~en                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.087      ; 2.342      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[27]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.101      ; 2.357      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|state                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.087      ; 2.343      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|busy                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.087      ; 2.343      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|ss_n[0]                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.087      ; 2.343      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[15]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.351      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[15]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.351      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|delay_line:serout_clock_delay|shift_reg[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.088      ; 2.344      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|delay_line:serout_clock_delay|shift_reg[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.088      ; 2.344      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_clock_reg                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.088      ; 2.344      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_clock_last_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.088      ; 2.344      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_holding_full_reg                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.088      ; 2.344      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_active_reg                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.088      ; 2.344      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serial_out_reg                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.088      ; 2.344      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[15]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 2.361      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[25]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 2.356      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[25]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.094      ; 2.350      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[25]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.094      ; 2.350      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[27]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.351      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[27]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.094      ; 2.350      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[27]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 2.356      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[27]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.094      ; 2.350      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[26]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.351      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[26]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.351      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[10]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.351      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[10]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.351      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[10]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.351      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[12]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.351      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[12]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.351      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[12]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.351      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[7]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 2.356      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[7]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 2.356      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[9]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 2.356      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[14]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 2.361      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[6]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 2.356      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[6]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 2.356      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[22]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 2.356      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[22]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.094      ; 2.350      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[22]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.094      ; 2.350      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[22]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 2.356      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[11]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.351      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[11]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.351      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[11]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.351      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[21]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.094      ; 2.350      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[21]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.351      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[21]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.351      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[3]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 2.356      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[3]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 2.356      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|irqst_reg[3]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.088      ; 2.344      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[19]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.351      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[19]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.094      ; 2.350      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[19]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.351      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[19]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.094      ; 2.350      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[19]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.101      ; 2.357      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[5]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.093      ; 2.349      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[13]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 2.361      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[13]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.351      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[13]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.351      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[13]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.351      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[8]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 2.361      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[0]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 2.356      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[0]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 2.360      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[20]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 2.356      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[20]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.094      ; 2.350      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[20]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.094      ; 2.350      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[20]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 2.356      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[14]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.094      ; 2.350      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[18]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.351      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[18]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.094      ; 2.350      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[18]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.094      ; 2.350      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[18]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.351      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|irqen_reg[2]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.088      ; 2.344      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[2]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 2.356      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[2]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 2.356      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[16]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.097      ; 2.353      ;
; 2.152 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[8]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.351      ;
; 2.153 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[15]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.089      ; 2.346      ;
; 2.153 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[8]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.088      ; 2.345      ;
; 2.153 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[7]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 2.357      ;
; 2.153 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[7]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 2.357      ;
; 2.153 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[6]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 2.357      ;
; 2.153 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[2]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 2.357      ;
; 2.153 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[3]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 2.357      ;
; 2.153 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[9]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 2.357      ;
; 2.153 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[6]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 2.357      ;
; 2.153 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[3]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 2.357      ;
; 2.153 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[0]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 2.357      ;
; 2.153 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[14]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.089      ; 2.346      ;
; 2.153 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[2]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 2.357      ;
; 2.159 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[8]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.092      ; 2.355      ;
; 2.159 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[9]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.092      ; 2.355      ;
; 2.159 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[14]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.092      ; 2.355      ;
; 2.159 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[16]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.092      ; 2.355      ;
; 2.159 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[17]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.092      ; 2.355      ;
+-------+---------------------------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                         ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                          ; Clock Edge ; Target                                                    ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[15]                                            ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[1]                                             ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[4]                                             ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[5]                                             ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[7]                                             ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[9]                                             ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[11]                                            ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[12]                                            ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[13]                                            ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[15]                                            ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[16]                                            ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[17]                                            ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[18]                                            ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[19]                                            ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[20]                                            ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[21]                                            ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[22]                                            ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[23]                                            ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[24]                                            ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[26]                                            ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[27]                                            ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[28]                                            ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[29]                                            ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[30]                                            ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[31]                                            ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[4]                                             ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[5]                                             ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[7]                                             ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_reg                      ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_req                    ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_reg                      ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[0]                                             ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[10]                                            ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[11]                                            ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[12]                                            ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[13]                                            ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[14]                                            ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[2]                                             ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[3]                                             ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[6]                                             ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[8]                                             ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[0]                                             ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[10]                                            ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[14]                                            ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[1]                                             ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[25]                                            ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[2]                                             ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[3]                                             ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[6]                                             ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[8]                                             ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[9]                                             ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_act                      ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_act                      ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ;
; 5.607 ; 5.823        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[0]                                           ;
; 5.607 ; 5.823        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[1]                                           ;
; 5.607 ; 5.823        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel[0]                     ;
; 5.607 ; 5.762        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[10]                  ;
; 5.607 ; 5.762        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[11]                  ;
; 5.607 ; 5.762        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[12]                  ;
; 5.607 ; 5.762        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[13]                  ;
; 5.607 ; 5.762        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[14]                  ;
; 5.607 ; 5.762        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[15]                  ;
; 5.607 ; 5.823        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_act                    ;
; 5.607 ; 5.823        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ;
; 5.607 ; 5.823        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ;
; 5.607 ; 5.823        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_complete_reg                                ;
; 5.607 ; 5.823        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_reg                                         ;
; 5.607 ; 5.823        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[2]                                                ;
; 5.607 ; 5.823        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[3]                                                ;
; 5.607 ; 5.823        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[4]                                                ;
; 5.607 ; 5.823        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[5]                                                ;
; 5.607 ; 5.823        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[6]                                                ;
; 5.607 ; 5.823        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[7]                                                ;
; 5.608 ; 5.824        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ;
; 5.608 ; 5.824        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ;
; 5.608 ; 5.824        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ;
; 5.608 ; 5.824        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ;
; 5.608 ; 5.763        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[5]                   ;
; 5.608 ; 5.824        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ;
; 5.608 ; 5.824        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|sdram_rdy                     ;
; 5.608 ; 5.824        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[0]                                                ;
; 5.608 ; 5.824        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[10]                                               ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+-----------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                              ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                          ; Clock Edge ; Target                                                                                                                                                                         ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 8.476 ; 8.706        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_address_reg0 ;
; 8.476 ; 8.706        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg       ;
; 8.476 ; 8.706        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_address_reg0 ;
; 8.476 ; 8.706        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg       ;
; 8.476 ; 8.706        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_address_reg0 ;
; 8.476 ; 8.706        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg       ;
; 8.476 ; 8.706        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_address_reg0 ;
; 8.476 ; 8.706        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg       ;
; 8.478 ; 8.708        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 8.478 ; 8.708        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_datain_reg0  ;
; 8.478 ; 8.708        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 8.478 ; 8.708        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_datain_reg0  ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; half_scandouble_enable_reg                                                                                                                                                     ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|buffer_select_reg                                                                                                    ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                        ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                        ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                        ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                        ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                        ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                        ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                        ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[0]                                                                                  ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[10]                                                                                 ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[114]                                                                                ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[115]                                                                                ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[116]                                                                                ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[117]                                                                                ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[118]                                                                                ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[119]                                                                                ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[11]                                                                                 ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[120]                                                                                ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[121]                                                                                ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[122]                                                                                ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[123]                                                                                ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[124]                                                                                ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[125]                                                                                ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[126]                                                                                ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[127]                                                                                ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[12]                                                                                 ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[13]                                                                                 ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[14]                                                                                 ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[15]                                                                                 ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[1]                                                                                  ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[2]                                                                                  ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[32]                                                                                 ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[33]                                                                                 ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[34]                                                                                 ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[35]                                                                                 ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[36]                                                                                 ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[37]                                                                                 ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[38]                                                                                 ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[39]                                                                                 ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[3]                                                                                  ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[40]                                                                                 ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[41]                                                                                 ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[42]                                                                                 ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[43]                                                                                 ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[44]                                                                                 ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[45]                                                                                 ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[46]                                                                                 ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[47]                                                                                 ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[48]                                                                                 ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[49]                                                                                 ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[4]                                                                                  ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[50]                                                                                 ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[51]                                                                                 ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[52]                                                                                 ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[53]                                                                                 ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[54]                                                                                 ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[55]                                                                                 ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[56]                                                                                 ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[57]                                                                                 ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[58]                                                                                 ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[59]                                                                                 ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[5]                                                                                  ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[60]                                                                                 ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[61]                                                                                 ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[62]                                                                                 ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[63]                                                                                 ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[64]                                                                                 ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[65]                                                                                 ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[66]                                                                                 ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[67]                                                                                 ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[68]                                                                                 ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[69]                                                                                 ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[6]                                                                                  ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[70]                                                                                 ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[71]                                                                                 ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[72]                                                                                 ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[73]                                                                                 ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[74]                                                                                 ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[75]                                                                                 ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[76]                                                                                 ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[77]                                                                                 ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[78]                                                                                 ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[79]                                                                                 ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[7]                                                                                  ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[82]                                                                                 ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[83]                                                                                 ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[84]                                                                                 ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                       ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                          ; Clock Edge ; Target                                                                                                                                                                                 ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a0~porta_address_reg0                                                                                   ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a11~porta_address_reg0                                                                                  ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a14~porta_address_reg0                                                                                  ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a17~porta_address_reg0                                                                                  ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a21~porta_address_reg0                                                                                  ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a22~porta_address_reg0                                                                                  ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a2~porta_address_reg0                                                                                   ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a4~porta_address_reg0                                                                                   ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a5~porta_address_reg0                                                                                   ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a6~porta_address_reg0                                                                                   ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a7~porta_address_reg0                                                                                   ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a8~porta_address_reg0                                                                                   ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_9f41:auto_generated|ram_block1a0~porta_address_reg0                                                       ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_9f41:auto_generated|ram_block1a0~porta_we_reg                                                             ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_9f41:auto_generated|ram_block1a0~porta_address_reg0                                                       ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_9f41:auto_generated|ram_block1a0~porta_we_reg                                                             ;
; 17.207 ; 17.437       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer:pokey_mixer_l|altsyncram:Ram0_rtl_0|altsyncram_kt71:auto_generated|ram_block1a0~porta_address_reg0 ;
; 17.207 ; 17.437       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer:pokey_mixer_l|altsyncram:Ram0_rtl_0|altsyncram_kt71:auto_generated|ram_block1a7~porta_address_reg0 ;
; 17.207 ; 17.437       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a10~porta_address_reg0                                                                                  ;
; 17.207 ; 17.437       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a1~porta_address_reg0                                                                                   ;
; 17.207 ; 17.437       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a20~porta_address_reg0                                                                                  ;
; 17.207 ; 17.437       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a3~porta_address_reg0                                                                                   ;
; 17.207 ; 17.437       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_9f41:auto_generated|ram_block1a0~porta_address_reg0                                                      ;
; 17.207 ; 17.437       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_9f41:auto_generated|ram_block1a0~porta_we_reg                                                            ;
; 17.207 ; 17.437       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_9f41:auto_generated|ram_block1a0~porta_address_reg0                                                        ;
; 17.207 ; 17.437       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_9f41:auto_generated|ram_block1a0~porta_we_reg                                                              ;
; 17.208 ; 17.438       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer:pokey_mixer_r|altsyncram:Ram0_rtl_0|altsyncram_kt71:auto_generated|ram_block1a0~porta_address_reg0 ;
; 17.208 ; 17.438       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_9f41:auto_generated|ram_block1a0~porta_datain_reg0                                                        ;
; 17.208 ; 17.438       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_9f41:auto_generated|ram_block1a0~porta_datain_reg0                                                        ;
; 17.209 ; 17.439       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer:pokey_mixer_r|altsyncram:Ram0_rtl_0|altsyncram_kt71:auto_generated|ram_block1a7~porta_address_reg0 ;
; 17.209 ; 17.439       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_9f41:auto_generated|ram_block1a0~porta_datain_reg0                                                       ;
; 17.209 ; 17.439       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_9f41:auto_generated|ram_block1a0~porta_datain_reg0                                                         ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[0]                                                                 ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[19]                                                                ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[24]                                                                ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[35]                                                                ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[37]                                                                ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[39]                                                                ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[40]                                                                ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[42]                                                                ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[5]                                                                 ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[6]                                                                 ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|dac_out                                                                                                                                                               ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p1[10]                                                                                                                                                     ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p1[11]                                                                                                                                                     ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p1[12]                                                                                                                                                     ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p1[2]                                                                                                                                                      ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p1[3]                                                                                                                                                      ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p1[4]                                                                                                                                                      ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p1[5]                                                                                                                                                      ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p1[6]                                                                                                                                                      ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p1[7]                                                                                                                                                      ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p1[8]                                                                                                                                                      ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p1[9]                                                                                                                                                      ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p2[12]                                                                                                                                                     ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p2[13]                                                                                                                                                     ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p2[14]                                                                                                                                                     ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p2[15]                                                                                                                                                     ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p2[16]                                                                                                                                                     ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p2[17]                                                                                                                                                     ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p2[18]                                                                                                                                                     ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p2[19]                                                                                                                                                     ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p2[20]                                                                                                                                                     ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p2[21]                                                                                                                                                     ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p2[22]                                                                                                                                                     ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p2[23]                                                                                                                                                     ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_lpf_p2[12]                                                                                                                                                     ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_lpf_p2[13]                                                                                                                                                     ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_lpf_p2[14]                                                                                                                                                     ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_lpf_p2[15]                                                                                                                                                     ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_lpf_p2[16]                                                                                                                                                     ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_lpf_p2[17]                                                                                                                                                     ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_lpf_p2[18]                                                                                                                                                     ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_lpf_p2[19]                                                                                                                                                     ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_lpf_p2[20]                                                                                                                                                     ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_lpf_p2[21]                                                                                                                                                     ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_lpf_p2[22]                                                                                                                                                     ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_lpf_p2[23]                                                                                                                                                     ;
; 17.246 ; 17.462       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[17][1]                                                     ;
; 17.246 ; 17.462       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[18][1]                                                     ;
; 17.246 ; 17.462       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[19][1]                                                     ;
; 17.246 ; 17.462       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[20][1]                                                     ;
; 17.246 ; 17.462       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[21][1]                                                     ;
; 17.246 ; 17.462       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[22][1]                                                     ;
; 17.246 ; 17.462       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[23][1]                                                     ;
; 17.246 ; 17.462       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[24][1]                                                     ;
; 17.246 ; 17.462       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[25][1]                                                     ;
; 17.246 ; 17.462       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[26][1]                                                     ;
; 17.246 ; 17.462       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[27][1]                                                     ;
; 17.246 ; 17.462       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Dreg                                                                       ;
; 17.246 ; 17.462       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Ireg                                                                       ;
; 17.246 ; 17.462       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[21]                                                                ;
; 17.246 ; 17.462       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[27]                                                                ;
; 17.246 ; 17.462       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[31]                                                                ;
; 17.246 ; 17.462       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]                                                                ;
; 17.246 ; 17.462       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[3]                                                                 ;
; 17.246 ; 17.462       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                                                 ;
; 17.246 ; 17.462       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|processInt                                                                 ;
; 17.246 ; 17.462       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p1[13]                                                                                                                                                     ;
; 17.246 ; 17.462       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p1[14]                                                                                                                                                     ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                    ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                         ; Clock Edge ; Target                                                                                              ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------+
; 17.437 ; 17.437       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.437 ; 17.437       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.437 ; 17.437       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.437 ; 17.437       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]                      ;
; 17.437 ; 17.437       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 17.451 ; 17.451       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.458 ; 17.458       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.458 ; 17.458       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.462 ; 17.462       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.462 ; 17.462       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.468 ; 17.468       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.483 ; 17.483       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.483 ; 17.483       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.483 ; 17.483       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.483 ; 17.483       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]                      ;
; 17.483 ; 17.483       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'                                                                                                                         ;
+---------+--------------+----------------+------------------+----------+------------+-----------------------------------------------------------------------------------------+
; Slack   ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                                                  ;
+---------+--------------+----------------+------------------+----------+------------+-----------------------------------------------------------------------------------------+
; 99.405  ; 99.405       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 99.405  ; 99.405       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 99.439  ; 99.439       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                        ;
; 99.450  ; 99.450       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 100.000 ; 100.000      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                        ;
; 100.000 ; 100.000      ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                        ;
; 100.549 ; 100.549      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 100.561 ; 100.561      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                        ;
; 100.592 ; 100.592      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 100.592 ; 100.592      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 196.000 ; 200.000      ; 4.000          ; Port Rate        ; FPGA_CLK ; Rise       ; FPGA_CLK                                                                                ;
+---------+--------------+----------------+------------------+----------+------------+-----------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                              ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.495 ; 2.053 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.474 ; 2.032 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.474 ; 2.032 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.474 ; 2.032 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 1.486 ; 2.044 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 1.491 ; 2.049 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 1.489 ; 2.047 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 1.485 ; 2.043 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 1.495 ; 2.053 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 1.487 ; 2.045 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 1.493 ; 2.051 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.487 ; 2.045 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.487 ; 2.045 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.477 ; 2.035 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 1.475 ; 2.033 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.465 ; 2.023 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.475 ; 2.033 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; 3.156 ; 3.534 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; 2.015 ; 2.506 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; 2.579 ; 3.006 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; 2.415 ; 2.874 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; 2.282 ; 2.743 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; 3.156 ; 3.534 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; 2.968 ; 3.372 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; 1.838 ; 2.371 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; 2.404 ; 2.833 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; 2.206 ; 2.684 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; 2.208 ; 2.691 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; 2.968 ; 3.372 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; 3.459 ; 4.296 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; 3.416 ; 4.223 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; 2.422 ; 2.826 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                 ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; -0.999 ; -1.557 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; -1.008 ; -1.566 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; -1.008 ; -1.566 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; -1.008 ; -1.566 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; -1.020 ; -1.578 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; -1.025 ; -1.583 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; -1.023 ; -1.581 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; -1.019 ; -1.577 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; -1.029 ; -1.587 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; -1.021 ; -1.579 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; -1.027 ; -1.585 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; -1.021 ; -1.579 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; -1.021 ; -1.579 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; -1.011 ; -1.569 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; -1.009 ; -1.567 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; -0.999 ; -1.557 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; -1.009 ; -1.567 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; -1.513 ; -1.999 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; -1.513 ; -1.999 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; -2.042 ; -2.451 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; -1.884 ; -2.324 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; -1.756 ; -2.204 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; -1.565 ; -2.029 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; -1.343 ; -1.870 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; -1.343 ; -1.870 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; -1.885 ; -2.312 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; -1.662 ; -2.128 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; -1.699 ; -2.177 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; -1.521 ; -2.012 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; -2.902 ; -3.727 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; -2.859 ; -3.658 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; -1.908 ; -2.318 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                      ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 2.588 ; 2.294 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 1.607 ; 1.456 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 1.597 ; 1.446 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 1.597 ; 1.446 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 1.597 ; 1.446 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 1.596 ; 1.445 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 1.604 ; 1.453 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 1.613 ; 1.462 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 2.588 ; 2.294 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 1.615 ; 1.464 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 1.625 ; 1.474 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 1.607 ; 1.456 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 2.582 ; 2.288 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 1.609 ; 1.458 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 2.582 ; 2.288 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 2.594 ; 2.300 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 1.619 ; 1.468 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 2.640 ; 2.362 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 1.753 ; 1.607 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 1.753 ; 1.607 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 1.753 ; 1.607 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 2.627 ; 2.349 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 2.622 ; 2.344 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 1.163 ; 1.075 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 1.685 ; 1.535 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 1.695 ; 1.545 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 1.780 ; 1.634 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 2.640 ; 2.362 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 1.780 ; 1.634 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 1.780 ; 1.634 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 1.770 ; 1.624 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 2.638 ; 2.360 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 1.762 ; 1.616 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 1.772 ; 1.626 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 2.064 ; 2.005 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 1.871 ; 1.835 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 2.064 ; 2.005 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 1.619 ; 1.468 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 1.629 ; 1.478 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 3.371 ; 3.934 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 2.271 ; 2.491 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 2.164 ; 2.322 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 3.739 ; 4.336 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 1.913 ; 1.796 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 8.371 ;       ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 8.318 ; Fall       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]        ; FPGA_CLK   ; 2.932 ; 3.400 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]       ; FPGA_CLK   ; 1.316 ; 1.335 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]       ; FPGA_CLK   ; 2.932 ; 3.400 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]       ; FPGA_CLK   ; 1.131 ; 1.193 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]       ; FPGA_CLK   ; 2.917 ; 3.385 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]        ; FPGA_CLK   ; 2.885 ; 3.318 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]       ; FPGA_CLK   ; 2.885 ; 3.318 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]       ; FPGA_CLK   ; 1.108 ; 1.074 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]       ; FPGA_CLK   ; 1.118 ; 1.084 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]       ; FPGA_CLK   ; 1.108 ; 1.074 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_HS          ; FPGA_CLK   ; 2.873 ; 3.306 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_R[*]        ; FPGA_CLK   ; 1.099 ; 1.065 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[0]       ; FPGA_CLK   ; 1.086 ; 1.052 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[1]       ; FPGA_CLK   ; 1.096 ; 1.062 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[2]       ; FPGA_CLK   ; 1.099 ; 1.065 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[3]       ; FPGA_CLK   ; 1.089 ; 1.055 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_VS          ; FPGA_CLK   ; 1.097 ; 1.063 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                              ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 1.178 ; 1.029 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 1.189 ; 1.040 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 1.179 ; 1.030 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 1.179 ; 1.030 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 1.179 ; 1.030 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 1.178 ; 1.029 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 1.186 ; 1.037 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 1.195 ; 1.046 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 2.192 ; 1.898 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 1.197 ; 1.048 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 1.207 ; 1.058 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 1.189 ; 1.040 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 1.191 ; 1.042 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 1.191 ; 1.042 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 2.186 ; 1.892 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 2.198 ; 1.904 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 1.201 ; 1.052 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 0.768 ; 0.680 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 1.334 ; 1.190 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 1.334 ; 1.190 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 1.334 ; 1.190 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 2.232 ; 1.954 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 2.227 ; 1.949 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 0.768 ; 0.680 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 1.266 ; 1.118 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 1.276 ; 1.128 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 1.361 ; 1.217 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 2.245 ; 1.967 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 1.361 ; 1.217 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 1.361 ; 1.217 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 1.351 ; 1.207 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 2.243 ; 1.965 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 1.343 ; 1.199 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 1.353 ; 1.209 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 1.444 ; 1.412 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 1.444 ; 1.412 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 1.630 ; 1.576 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 1.201 ; 1.052 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 1.211 ; 1.062 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 2.961 ; 3.520 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 1.841 ; 2.053 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 1.729 ; 1.880 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 3.310 ; 3.901 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 1.487 ; 1.376 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 7.998 ;       ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 7.944 ; Fall       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]        ; FPGA_CLK   ; 0.736 ; 0.798 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]       ; FPGA_CLK   ; 0.920 ; 0.939 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]       ; FPGA_CLK   ; 2.537 ; 3.005 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]       ; FPGA_CLK   ; 0.736 ; 0.798 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]       ; FPGA_CLK   ; 2.522 ; 2.990 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]        ; FPGA_CLK   ; 0.711 ; 0.677 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]       ; FPGA_CLK   ; 2.488 ; 2.921 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]       ; FPGA_CLK   ; 0.711 ; 0.677 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]       ; FPGA_CLK   ; 0.721 ; 0.687 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]       ; FPGA_CLK   ; 0.711 ; 0.677 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_HS          ; FPGA_CLK   ; 2.477 ; 2.910 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_R[*]        ; FPGA_CLK   ; 0.690 ; 0.656 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[0]       ; FPGA_CLK   ; 0.690 ; 0.656 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[1]       ; FPGA_CLK   ; 0.700 ; 0.666 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[2]       ; FPGA_CLK   ; 0.702 ; 0.668 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[3]       ; FPGA_CLK   ; 0.692 ; 0.658 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_VS          ; FPGA_CLK   ; 0.700 ; 0.666 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                                      ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.924 ; 1.897 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.270 ; 2.243 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.270 ; 2.243 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.270 ; 2.243 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.309 ; 2.282 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.500 ; 2.473 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.648 ; 2.621 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.676 ; 2.649 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.688 ; 2.661 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.489 ; 2.462 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.302 ; 2.275 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.098 ; 2.071 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.098 ; 2.071 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.088 ; 2.061 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 1.934 ; 1.907 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.924 ; 1.897 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.934 ; 1.907 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.133 ; 2.757 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                              ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 0.632 ; 0.632 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 0.964 ; 0.964 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 0.964 ; 0.964 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 0.964 ; 0.964 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 1.003 ; 1.003 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 1.185 ; 1.185 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 1.328 ; 1.328 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 1.354 ; 1.354 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 1.366 ; 1.366 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 1.175 ; 1.175 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 0.996 ; 0.996 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 0.800 ; 0.800 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 0.800 ; 0.800 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 0.790 ; 0.790 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 0.642 ; 0.642 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 0.632 ; 0.632 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 0.642 ; 0.642 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.605 ; 2.244 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                             ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.964     ; 1.964     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.345     ; 2.345     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.345     ; 2.345     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.345     ; 2.345     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.393     ; 2.393     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.597     ; 2.597     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.753     ; 2.753     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.783     ; 2.783     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.801     ; 2.801     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.591     ; 2.591     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.383     ; 2.383     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.154     ; 2.154     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.154     ; 2.154     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.144     ; 2.144     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 1.974     ; 1.974     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.964     ; 1.964     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.974     ; 1.974     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.931     ; 3.307     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                                     ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 0.670     ; 0.787     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.036     ; 1.153     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.036     ; 1.153     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.036     ; 1.153     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 1.083     ; 1.200     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 1.279     ; 1.396     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 1.428     ; 1.545     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 1.457     ; 1.574     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 1.475     ; 1.592     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 1.274     ; 1.391     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 1.074     ; 1.191     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 0.854     ; 0.971     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 0.854     ; 0.971     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 0.844     ; 0.961     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 0.680     ; 0.797     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 0.670     ; 0.787     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 0.680     ; 0.797     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.412     ; 2.773     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+


---------------------------------------------
; Fast 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+---------------------------------------------------------------------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary                                                                                                         ;
+---------------------------------------------------------------------------------+--------+-------+----------+---------+---------------------+
; Clock                                                                           ; Setup  ; Hold  ; Recovery ; Removal ; Minimum Pulse Width ;
+---------------------------------------------------------------------------------+--------+-------+----------+---------+---------------------+
; Worst-case Slack                                                                ; 0.049  ; 0.180 ; 5.854    ; 1.243   ; 5.517               ;
;  FPGA_CLK                                                                       ; N/A    ; N/A   ; N/A      ; N/A     ; 99.405              ;
;  \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.049  ; 0.188 ; 7.443    ; 1.243   ; 5.517               ;
;  \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 2.268  ; 0.180 ; 5.854    ; 2.151   ; 17.158              ;
;  \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 10.118 ; 0.187 ; 12.134   ; 1.703   ; 8.431               ;
;  \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]  ; N/A    ; N/A   ; N/A      ; N/A     ; 17.423              ;
; Design-wide TNS                                                                 ; 0.0    ; 0.0   ; 0.0      ; 0.0     ; 0.0                 ;
;  FPGA_CLK                                                                       ; N/A    ; N/A   ; N/A      ; N/A     ; 0.000               ;
;  \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000  ; 0.000 ; 0.000    ; 0.000   ; 0.000               ;
;  \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000  ; 0.000 ; 0.000    ; 0.000   ; 0.000               ;
;  \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000  ; 0.000 ; 0.000    ; 0.000   ; 0.000               ;
;  \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]  ; N/A    ; N/A   ; N/A      ; N/A     ; 0.000               ;
+---------------------------------------------------------------------------------+--------+-------+----------+---------+---------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                              ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 3.046 ; 3.153 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.025 ; 3.132 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.025 ; 3.132 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.025 ; 3.132 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.036 ; 3.143 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.040 ; 3.147 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.038 ; 3.145 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.034 ; 3.141 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.046 ; 3.153 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.032 ; 3.139 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.036 ; 3.143 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.024 ; 3.131 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.024 ; 3.131 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.014 ; 3.121 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 3.012 ; 3.119 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 3.002 ; 3.109 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 3.012 ; 3.119 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; 6.415 ; 6.835 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; 4.015 ; 4.221 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; 5.075 ; 5.301 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; 4.900 ; 5.203 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; 4.624 ; 4.861 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; 6.415 ; 6.835 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; 6.008 ; 6.437 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; 3.738 ; 3.948 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; 4.790 ; 4.942 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; 4.515 ; 4.739 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; 4.431 ; 4.674 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; 6.008 ; 6.437 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; 7.279 ; 7.561 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; 7.135 ; 7.445 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; 4.810 ; 4.949 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                 ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; -0.999 ; -1.557 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; -1.008 ; -1.566 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; -1.008 ; -1.566 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; -1.008 ; -1.566 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; -1.020 ; -1.578 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; -1.025 ; -1.583 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; -1.023 ; -1.581 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; -1.019 ; -1.577 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; -1.029 ; -1.587 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; -1.021 ; -1.579 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; -1.027 ; -1.585 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; -1.021 ; -1.579 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; -1.021 ; -1.579 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; -1.011 ; -1.569 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; -1.009 ; -1.567 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; -0.999 ; -1.557 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; -1.009 ; -1.567 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; -1.513 ; -1.999 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; -1.513 ; -1.999 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; -2.042 ; -2.451 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; -1.884 ; -2.324 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; -1.756 ; -2.204 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; -1.565 ; -2.029 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; -1.343 ; -1.870 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; -1.343 ; -1.870 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; -1.885 ; -2.312 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; -1.662 ; -2.128 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; -1.699 ; -2.177 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; -1.521 ; -2.012 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; -2.902 ; -3.727 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; -2.859 ; -3.658 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; -1.908 ; -2.318 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                      ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 4.590 ; 4.140 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 3.323 ; 3.087 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 3.313 ; 3.077 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 3.313 ; 3.077 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 3.313 ; 3.077 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 3.317 ; 3.081 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 3.326 ; 3.090 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 3.335 ; 3.099 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 4.590 ; 4.140 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 3.336 ; 3.100 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 3.346 ; 3.110 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 3.323 ; 3.087 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 4.578 ; 4.128 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 3.325 ; 3.089 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 4.578 ; 4.128 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 4.590 ; 4.140 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 3.335 ; 3.099 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 4.660 ; 4.212 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 3.607 ; 3.350 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 3.607 ; 3.350 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 3.607 ; 3.350 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 4.637 ; 4.189 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 4.633 ; 4.185 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 2.563 ; 2.365 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 3.507 ; 3.264 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 3.519 ; 3.276 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 3.639 ; 3.382 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 4.657 ; 4.209 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 3.644 ; 3.387 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 3.644 ; 3.387 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 3.634 ; 3.377 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 4.660 ; 4.212 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 3.626 ; 3.369 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 3.636 ; 3.379 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 4.166 ; 4.606 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 3.794 ; 4.242 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 4.166 ; 4.606 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 3.335 ; 3.099 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 3.345 ; 3.109 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 6.349 ; 6.633 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 5.037 ; 4.869 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 5.099 ; 4.662 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 7.288 ; 7.372 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 3.878 ; 4.179 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 9.378 ;       ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 9.107 ; Fall       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]        ; FPGA_CLK   ; 5.382 ; 5.730 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]       ; FPGA_CLK   ; 2.808 ; 2.778 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]       ; FPGA_CLK   ; 5.382 ; 5.730 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]       ; FPGA_CLK   ; 2.578 ; 2.528 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]       ; FPGA_CLK   ; 5.360 ; 5.708 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]        ; FPGA_CLK   ; 5.266 ; 5.559 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]       ; FPGA_CLK   ; 5.266 ; 5.559 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]       ; FPGA_CLK   ; 2.506 ; 2.389 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]       ; FPGA_CLK   ; 2.516 ; 2.399 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]       ; FPGA_CLK   ; 2.506 ; 2.389 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_HS          ; FPGA_CLK   ; 5.255 ; 5.548 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_R[*]        ; FPGA_CLK   ; 2.496 ; 2.379 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[0]       ; FPGA_CLK   ; 2.484 ; 2.367 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[1]       ; FPGA_CLK   ; 2.494 ; 2.377 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[2]       ; FPGA_CLK   ; 2.496 ; 2.379 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[3]       ; FPGA_CLK   ; 2.486 ; 2.369 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_VS          ; FPGA_CLK   ; 2.495 ; 2.378 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                              ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 1.178 ; 1.029 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 1.189 ; 1.040 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 1.179 ; 1.030 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 1.179 ; 1.030 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 1.179 ; 1.030 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 1.178 ; 1.029 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 1.186 ; 1.037 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 1.195 ; 1.046 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 2.192 ; 1.898 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 1.197 ; 1.048 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 1.207 ; 1.058 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 1.189 ; 1.040 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 1.191 ; 1.042 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 1.191 ; 1.042 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 2.186 ; 1.892 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 2.198 ; 1.904 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 1.201 ; 1.052 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 0.768 ; 0.680 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 1.334 ; 1.190 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 1.334 ; 1.190 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 1.334 ; 1.190 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 2.232 ; 1.954 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 2.227 ; 1.949 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 0.768 ; 0.680 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 1.266 ; 1.118 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 1.276 ; 1.128 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 1.361 ; 1.217 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 2.245 ; 1.967 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 1.361 ; 1.217 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 1.361 ; 1.217 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 1.351 ; 1.207 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 2.243 ; 1.965 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 1.343 ; 1.199 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 1.353 ; 1.209 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 1.444 ; 1.412 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 1.444 ; 1.412 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 1.630 ; 1.576 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 1.201 ; 1.052 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 1.211 ; 1.062 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 2.961 ; 3.520 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 1.841 ; 2.053 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 1.729 ; 1.880 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 3.310 ; 3.901 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 1.487 ; 1.376 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 7.998 ;       ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 7.944 ; Fall       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]        ; FPGA_CLK   ; 0.736 ; 0.798 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]       ; FPGA_CLK   ; 0.920 ; 0.939 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]       ; FPGA_CLK   ; 2.537 ; 3.005 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]       ; FPGA_CLK   ; 0.736 ; 0.798 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]       ; FPGA_CLK   ; 2.522 ; 2.990 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]        ; FPGA_CLK   ; 0.711 ; 0.677 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]       ; FPGA_CLK   ; 2.488 ; 2.921 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]       ; FPGA_CLK   ; 0.711 ; 0.677 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]       ; FPGA_CLK   ; 0.721 ; 0.687 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]       ; FPGA_CLK   ; 0.711 ; 0.677 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_HS          ; FPGA_CLK   ; 2.477 ; 2.910 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_R[*]        ; FPGA_CLK   ; 0.690 ; 0.656 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[0]       ; FPGA_CLK   ; 0.690 ; 0.656 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[1]       ; FPGA_CLK   ; 0.700 ; 0.666 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[2]       ; FPGA_CLK   ; 0.702 ; 0.668 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[3]       ; FPGA_CLK   ; 0.692 ; 0.658 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_VS          ; FPGA_CLK   ; 0.700 ; 0.666 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                     ;
+----------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; Pin            ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
+----------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; VGA_VS         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_HS         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[0]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[1]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[2]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[3]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[0]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[1]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[2]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[3]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[0]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[1]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[2]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[3]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; AUDIO_L        ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; AUDIO_R        ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_BA[0]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_BA[1]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_CS_N     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_RAS_N    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_CAS_N    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_WE_N     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQM_n[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQM_n[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_CLK      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[0]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[1]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[2]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[3]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[4]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[5]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[6]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[7]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[8]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[9]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[10]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[11]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[12]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SD_CLK         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SD_CMD         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SD_DAT3        ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[0]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[1]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[2]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[3]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[4]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[5]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[6]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[7]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[8]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[9]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[10]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[11]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[12]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[13]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[14]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[15]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+----------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+


+-----------------------------------------------------------------+
; Input Transition Times                                          ;
+--------------+--------------+-----------------+-----------------+
; Pin          ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+--------------+--------------+-----------------+-----------------+
; PS2M_CLK     ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; PS2M_DAT     ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY1_n[5]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY2_n[5]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[0]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[1]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[2]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[3]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[4]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[5]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[6]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[7]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[8]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[9]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[10] ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[11] ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[12] ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[13] ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[14] ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[15] ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; FPGA_CLK     ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY1_n[4]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY2_n[4]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY1_n[1]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY1_n[0]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY2_n[3]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY1_n[2]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY2_n[2]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY2_n[0]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY2_n[1]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY1_n[3]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SD_DAT0      ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; PS2K_CLK     ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; PS2K_DAT     ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
+--------------+--------------+-----------------+-----------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin            ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; VGA_VS         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_HS         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.00154 V          ; 0.08 V                               ; 0.145 V                              ; 7.32e-09 s                  ; 7.58e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.00154 V         ; 0.08 V                              ; 0.145 V                             ; 7.32e-09 s                 ; 7.58e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[0]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.46e-07 V                   ; 3.09 V              ; -0.011 V            ; 0.146 V                              ; 0.189 V                              ; 1.76e-09 s                  ; 1.77e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.46e-07 V                  ; 3.09 V             ; -0.011 V           ; 0.146 V                             ; 0.189 V                             ; 1.76e-09 s                 ; 1.77e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[1]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.46e-07 V                   ; 3.08 V              ; -0.00108 V          ; 0.089 V                              ; 0.161 V                              ; 7.68e-09 s                  ; 7.97e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.46e-07 V                  ; 3.08 V             ; -0.00108 V         ; 0.089 V                             ; 0.161 V                             ; 7.68e-09 s                 ; 7.97e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[2]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.46e-07 V                   ; 3.09 V              ; -0.013 V            ; 0.091 V                              ; 0.178 V                              ; 1.33e-09 s                  ; 1.36e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.46e-07 V                  ; 3.09 V             ; -0.013 V           ; 0.091 V                             ; 0.178 V                             ; 1.33e-09 s                 ; 1.36e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[3]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.46e-07 V                   ; 3.08 V              ; -0.00108 V          ; 0.089 V                              ; 0.161 V                              ; 7.68e-09 s                  ; 7.97e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.46e-07 V                  ; 3.08 V             ; -0.00108 V         ; 0.089 V                             ; 0.161 V                             ; 7.68e-09 s                 ; 7.97e-09 s                 ; Yes                       ; Yes                       ;
; VGA_G[0]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.00154 V          ; 0.08 V                               ; 0.145 V                              ; 7.32e-09 s                  ; 7.58e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.00154 V         ; 0.08 V                              ; 0.145 V                             ; 7.32e-09 s                 ; 7.58e-09 s                 ; Yes                       ; Yes                       ;
; VGA_G[1]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_G[2]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_G[3]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_R[0]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_R[1]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_R[2]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_R[3]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; AUDIO_L        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.46e-07 V                   ; 3.08 V              ; -0.00108 V          ; 0.089 V                              ; 0.161 V                              ; 7.68e-09 s                  ; 7.97e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.46e-07 V                  ; 3.08 V             ; -0.00108 V         ; 0.089 V                             ; 0.161 V                             ; 7.68e-09 s                 ; 7.97e-09 s                 ; Yes                       ; Yes                       ;
; AUDIO_R        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.46e-07 V                   ; 3.09 V              ; -0.011 V            ; 0.146 V                              ; 0.189 V                              ; 1.76e-09 s                  ; 1.77e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.46e-07 V                  ; 3.09 V             ; -0.011 V           ; 0.146 V                             ; 0.189 V                             ; 1.76e-09 s                 ; 1.77e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_BA[0]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_BA[1]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.08 V              ; -0.00469 V          ; 0.309 V                              ; 0.24 V                               ; 5.8e-09 s                   ; 4.65e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.08 V             ; -0.00469 V         ; 0.309 V                             ; 0.24 V                              ; 5.8e-09 s                  ; 4.65e-09 s                 ; No                        ; Yes                       ;
; SDRAM_CS_N     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_RAS_N    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_CAS_N    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.08 V              ; -0.00469 V          ; 0.309 V                              ; 0.24 V                               ; 5.8e-09 s                   ; 4.65e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.08 V             ; -0.00469 V         ; 0.309 V                             ; 0.24 V                              ; 5.8e-09 s                  ; 4.65e-09 s                 ; No                        ; Yes                       ;
; SDRAM_WE_N     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQM_n[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQM_n[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_CLK      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[6]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[7]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.08 V              ; -0.00469 V          ; 0.309 V                              ; 0.24 V                               ; 5.8e-09 s                   ; 4.65e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.08 V             ; -0.00469 V         ; 0.309 V                             ; 0.24 V                              ; 5.8e-09 s                  ; 4.65e-09 s                 ; No                        ; Yes                       ;
; SDRAM_A[8]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[9]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[10]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[11]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[12]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.08 V              ; -0.00469 V          ; 0.309 V                              ; 0.24 V                               ; 5.8e-09 s                   ; 4.65e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.08 V             ; -0.00469 V         ; 0.309 V                             ; 0.24 V                              ; 5.8e-09 s                  ; 4.65e-09 s                 ; No                        ; Yes                       ;
; SD_CLK         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; SD_CMD         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.00154 V          ; 0.08 V                               ; 0.145 V                              ; 7.32e-09 s                  ; 7.58e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.00154 V         ; 0.08 V                              ; 0.145 V                             ; 7.32e-09 s                 ; 7.58e-09 s                 ; Yes                       ; Yes                       ;
; SD_DAT3        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[0]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[1]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[2]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[3]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.08 V              ; -0.00384 V          ; 0.283 V                              ; 0.244 V                              ; 6.17e-09 s                  ; 4.9e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.08 V             ; -0.00384 V         ; 0.283 V                             ; 0.244 V                             ; 6.17e-09 s                 ; 4.9e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[4]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.08 V              ; -0.00384 V          ; 0.283 V                              ; 0.244 V                              ; 6.17e-09 s                  ; 4.9e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.08 V             ; -0.00384 V         ; 0.283 V                             ; 0.244 V                             ; 6.17e-09 s                 ; 4.9e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[5]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[6]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.12 V              ; -0.0417 V           ; 0.221 V                              ; 0.245 V                              ; 1.09e-09 s                  ; 8.59e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.12 V             ; -0.0417 V          ; 0.221 V                             ; 0.245 V                             ; 1.09e-09 s                 ; 8.59e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[7]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.12 V              ; -0.0417 V           ; 0.221 V                              ; 0.245 V                              ; 1.09e-09 s                  ; 8.59e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.12 V             ; -0.0417 V          ; 0.221 V                             ; 0.245 V                             ; 1.09e-09 s                 ; 8.59e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[8]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[9]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.08 V              ; -0.00384 V          ; 0.283 V                              ; 0.244 V                              ; 6.17e-09 s                  ; 4.9e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.08 V             ; -0.00384 V         ; 0.283 V                             ; 0.244 V                             ; 6.17e-09 s                 ; 4.9e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[10]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[11]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[12]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[13]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.08 V              ; -0.00384 V          ; 0.283 V                              ; 0.244 V                              ; 6.17e-09 s                  ; 4.9e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.08 V             ; -0.00384 V         ; 0.283 V                             ; 0.244 V                             ; 6.17e-09 s                 ; 4.9e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[14]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[15]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin            ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; VGA_VS         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_HS         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.47 V              ; -0.0076 V           ; 0.323 V                              ; 0.334 V                              ; 4.77e-09 s                  ; 5.17e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 3.1e-07 V                   ; 3.47 V             ; -0.0076 V          ; 0.323 V                             ; 0.334 V                             ; 4.77e-09 s                 ; 5.17e-09 s                 ; No                        ; No                        ;
; VGA_B[0]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.1e-07 V                    ; 3.51 V              ; -0.0419 V           ; 0.296 V                              ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.1e-07 V                   ; 3.51 V             ; -0.0419 V          ; 0.296 V                             ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; VGA_B[1]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.1e-07 V                    ; 3.47 V              ; -0.00709 V          ; 0.326 V                              ; 0.34 V                               ; 5.02e-09 s                  ; 5.43e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.1e-07 V                   ; 3.47 V             ; -0.00709 V         ; 0.326 V                             ; 0.34 V                              ; 5.02e-09 s                 ; 5.43e-09 s                 ; No                        ; No                        ;
; VGA_B[2]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.1e-07 V                    ; 3.52 V              ; -0.0514 V           ; 0.253 V                              ; 0.324 V                              ; 8.77e-10 s                  ; 8.98e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 2.1e-07 V                   ; 3.52 V             ; -0.0514 V          ; 0.253 V                             ; 0.324 V                             ; 8.77e-10 s                 ; 8.98e-10 s                 ; No                        ; No                        ;
; VGA_B[3]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.1e-07 V                    ; 3.47 V              ; -0.00709 V          ; 0.326 V                              ; 0.34 V                               ; 5.02e-09 s                  ; 5.43e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.1e-07 V                   ; 3.47 V             ; -0.00709 V         ; 0.326 V                             ; 0.34 V                              ; 5.02e-09 s                 ; 5.43e-09 s                 ; No                        ; No                        ;
; VGA_G[0]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.47 V              ; -0.0076 V           ; 0.323 V                              ; 0.334 V                              ; 4.77e-09 s                  ; 5.17e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 3.1e-07 V                   ; 3.47 V             ; -0.0076 V          ; 0.323 V                             ; 0.334 V                             ; 4.77e-09 s                 ; 5.17e-09 s                 ; No                        ; No                        ;
; VGA_G[1]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_G[2]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_G[3]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_R[0]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_R[1]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_R[2]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_R[3]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; AUDIO_L        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.1e-07 V                    ; 3.47 V              ; -0.00709 V          ; 0.326 V                              ; 0.34 V                               ; 5.02e-09 s                  ; 5.43e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.1e-07 V                   ; 3.47 V             ; -0.00709 V         ; 0.326 V                             ; 0.34 V                              ; 5.02e-09 s                 ; 5.43e-09 s                 ; No                        ; No                        ;
; AUDIO_R        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.1e-07 V                    ; 3.51 V              ; -0.0419 V           ; 0.296 V                              ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.1e-07 V                   ; 3.51 V             ; -0.0419 V          ; 0.296 V                             ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; SDRAM_BA[0]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_BA[1]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.48 V              ; -0.0142 V           ; 0.362 V                              ; 0.291 V                              ; 3.89e-09 s                  ; 3.25e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.9e-07 V                   ; 3.48 V             ; -0.0142 V          ; 0.362 V                             ; 0.291 V                             ; 3.89e-09 s                 ; 3.25e-09 s                 ; No                        ; No                        ;
; SDRAM_CS_N     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_RAS_N    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_CAS_N    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.48 V              ; -0.0142 V           ; 0.362 V                              ; 0.291 V                              ; 3.89e-09 s                  ; 3.25e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.9e-07 V                   ; 3.48 V             ; -0.0142 V          ; 0.362 V                             ; 0.291 V                             ; 3.89e-09 s                 ; 3.25e-09 s                 ; No                        ; No                        ;
; SDRAM_WE_N     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_DQM_n[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_DQM_n[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_CLK      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[6]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[7]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.48 V              ; -0.0142 V           ; 0.362 V                              ; 0.291 V                              ; 3.89e-09 s                  ; 3.25e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.9e-07 V                   ; 3.48 V             ; -0.0142 V          ; 0.362 V                             ; 0.291 V                             ; 3.89e-09 s                 ; 3.25e-09 s                 ; No                        ; No                        ;
; SDRAM_A[8]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[9]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[10]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[11]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[12]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.48 V              ; -0.0142 V           ; 0.362 V                              ; 0.291 V                              ; 3.89e-09 s                  ; 3.25e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.9e-07 V                   ; 3.48 V             ; -0.0142 V          ; 0.362 V                             ; 0.291 V                             ; 3.89e-09 s                 ; 3.25e-09 s                 ; No                        ; No                        ;
; SD_CLK         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SD_CMD         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.47 V              ; -0.0076 V           ; 0.323 V                              ; 0.334 V                              ; 4.77e-09 s                  ; 5.17e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 3.1e-07 V                   ; 3.47 V             ; -0.0076 V          ; 0.323 V                             ; 0.334 V                             ; 4.77e-09 s                 ; 5.17e-09 s                 ; No                        ; No                        ;
; SD_DAT3        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[0]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[1]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[2]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[3]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.48 V              ; -0.0136 V           ; 0.352 V                              ; 0.346 V                              ; 4.12e-09 s                  ; 3.34e-09 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.48 V             ; -0.0136 V          ; 0.352 V                             ; 0.346 V                             ; 4.12e-09 s                 ; 3.34e-09 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[4]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.48 V              ; -0.0136 V           ; 0.352 V                              ; 0.346 V                              ; 4.12e-09 s                  ; 3.34e-09 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.48 V             ; -0.0136 V          ; 0.352 V                             ; 0.346 V                             ; 4.12e-09 s                 ; 3.34e-09 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[5]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[6]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.57 V              ; -0.0645 V           ; 0.332 V                              ; 0.165 V                              ; 6.78e-10 s                  ; 6.19e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.57 V             ; -0.0645 V          ; 0.332 V                             ; 0.165 V                             ; 6.78e-10 s                 ; 6.19e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[7]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.57 V              ; -0.0645 V           ; 0.332 V                              ; 0.165 V                              ; 6.78e-10 s                  ; 6.19e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.57 V             ; -0.0645 V          ; 0.332 V                             ; 0.165 V                             ; 6.78e-10 s                 ; 6.19e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[8]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[9]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.48 V              ; -0.0136 V           ; 0.352 V                              ; 0.346 V                              ; 4.12e-09 s                  ; 3.34e-09 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.48 V             ; -0.0136 V          ; 0.352 V                             ; 0.346 V                             ; 4.12e-09 s                 ; 3.34e-09 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[10]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[11]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[12]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[13]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.48 V              ; -0.0136 V           ; 0.352 V                              ; 0.346 V                              ; 4.12e-09 s                  ; 3.34e-09 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.48 V             ; -0.0136 V          ; 0.352 V                             ; 0.346 V                             ; 4.12e-09 s                 ; 3.34e-09 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[14]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[15]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Transfers                                                                                                                                                                                             ;
+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                                     ; To Clock                                                                       ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+----------+----------+----------+----------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1826     ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 10141    ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 7344     ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 3823582  ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 31       ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 1164     ; 0        ; 0        ; 0        ;
+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Transfers                                                                                                                                                                                              ;
+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                                     ; To Clock                                                                       ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+----------+----------+----------+----------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1826     ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 10141    ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 7344     ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 3823582  ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 31       ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 1164     ; 0        ; 0        ; 0        ;
+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Recovery Transfers                                                                                                                                                                                          ;
+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                                     ; To Clock                                                                       ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+----------+----------+----------+----------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 146      ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 508      ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 2301     ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 174      ; 0        ; 0        ; 0        ;
+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Removal Transfers                                                                                                                                                                                           ;
+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                                     ; To Clock                                                                       ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+----------+----------+----------+----------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 146      ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 508      ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 2301     ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 174      ; 0        ; 0        ; 0        ;
+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design


---------------
; Report RSKM ;
---------------
No dedicated SERDES Receiver circuitry present in device or used in design


+------------------------------------------------+
; Unconstrained Paths                            ;
+---------------------------------+-------+------+
; Property                        ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks                  ; 0     ; 0    ;
; Unconstrained Clocks            ; 0     ; 0    ;
; Unconstrained Input Ports       ; 29    ; 29   ;
; Unconstrained Input Port Paths  ; 61    ; 61   ;
; Unconstrained Output Ports      ; 55    ; 55   ;
; Unconstrained Output Port Paths ; 72    ; 72   ;
+---------------------------------+-------+------+


+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II 32-bit TimeQuest Timing Analyzer
    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
    Info: Processing started: Sat Aug  2 12:36:20 2014
Info: Command: quartus_sta atari800core -c atari800core
Info: qsta_default_script.tcl version: #1
Info (11104): Parallel Compilation has detected 4 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 2 of the 2 physical processors detected instead.
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (332104): Reading SDC File: 'atari800core.sdc'
Info (332110): Deriving PLL clocks
    Info (332110): create_generated_clock -source {\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 3 -duty_cycle 50.00 -name {\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]} {\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]}
    Info (332110): create_generated_clock -source {\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]} -duty_cycle 50.00 -name {\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]} {\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]}
    Info (332110): create_generated_clock -source {\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 3 -phase 236.25 -duty_cycle 50.00 -name {\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]} {\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]}
    Info (332110): create_generated_clock -source {\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -duty_cycle 50.00 -name {\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]} {\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]}
    Info (332110): create_generated_clock -source {\gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 11 -multiply_by 63 -duty_cycle 50.00 -name {\gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]} {\gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]}
Info (332151): Clock uncertainty is not calculated until you update the timing netlist.
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Analyzing Slow 1200mV 85C Model
Info (332146): Worst-case setup slack is 0.049
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.049         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     2.268         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    10.118         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case hold slack is 0.453
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.453         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.453         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):     0.454         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case recovery slack is 5.854
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     5.854         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     7.443         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    12.134         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case removal slack is 2.790
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     2.790         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     3.809         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):     4.783         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
Info (332146): Worst-case minimum pulse width slack is 5.517
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     5.517         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     8.433         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):    17.158         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    17.423         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    99.862         0.000 FPGA_CLK 
Info: Analyzing Slow 1200mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info (332146): Worst-case setup slack is 0.706
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.706         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     2.858         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    10.480         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case hold slack is 0.402
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.402         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.402         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.402         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case recovery slack is 6.355
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     6.355         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     7.792         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    12.524         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case removal slack is 2.493
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     2.493         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     3.412         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):     4.369         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
Info (332146): Worst-case minimum pulse width slack is 5.518
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     5.518         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     8.431         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):    17.158         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    17.426         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    99.837         0.000 FPGA_CLK 
Info: Analyzing Fast 1200mV 0C Model
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info (332146): Worst-case setup slack is 6.706
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     6.706         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     7.484         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    14.262         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case hold slack is 0.180
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.180         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.187         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):     0.188         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case recovery slack is 9.054
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     9.054         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     9.710         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    14.990         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case removal slack is 1.243
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     1.243         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     1.703         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):     2.151         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
Info (332146): Worst-case minimum pulse width slack is 5.605
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     5.605         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     8.476         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):    17.206         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    17.437         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    99.405         0.000 FPGA_CLK 
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 486 megabytes
    Info: Processing ended: Sat Aug  2 12:36:39 2014
    Info: Elapsed time: 00:00:19
    Info: Total CPU time (on all processors): 00:00:23


